Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes a wiring substrate including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers and having a cavity penetrating through a portion of the plurality of insulating layers, a passive component disposed in the cavity and including an external electrode electrically connected to at least one of the plurality of wiring layers, and a bridge disposed on the passive component in the cavity and including one or more circuit layers electrically connected to the external electrode.

Abstract: A semiconductor package including: a first wiring structure; a semiconductor chip disposed on the first wiring structure; a second wiring structure disposed on the semiconductor chip and including a cavity; and a filling member between the first wiring structure and the second wiring structure and in the cavity, wherein an uppermost end of the filling member and an uppermost end of the second wiring structure are located at the same level.

Abstract: A circuit board for a light-emitting diode assembly according to an embodiment includes a substrate layer having a first surface and a second surface facing each other, a conductive circuit layer disposed on the first surface of the substrate layer and having a single-layered structure, and an insulating layer formed on the first surface of the substrate layer to cover the conductive circuit layer. Channel resistance, luminous efficiency and luminous uniformity can be improved through a side connection of a dimming zone while vias or contacts are omitted.

Abstract: Methods of manufacture are described. A method includes forming a first cavity in a substrate and placing a backplane in the first cavity. At least one layer of dielectric material is formed over the substrate and the backplane. A second cavity is formed in the at least one layer of the dielectric material to expose at least a portion of a surface of the backplane. A heat conductive material is placed in the second cavity and in contact with the at least the portion of the surface of the backplane.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.

Abstract: A process for producing an internal cavity in a CMC article and mandrels used therewith. The process entails incorporating a mandrel made of a material that is substantially absorbed during thermal treatment of a preform to form the CMC article. The mandrel material is preferably reactive with one or more constituents of the CMC preform during the thermal treatment. The material is preferably silicon or a silicon alloy.

Abstract: An electronic component and a circuit board having the same mounted thereon. The electronic component includes: a base part; a coil part provided on the base part and including a coil formed by disposing conductive patterns in a spiral shape and an external terminal connected to an end portion of the coil; and a cover part including an external electrode having a first surface contacting an upper surface of the external terminal and a second surface opposing the first surface and a magnetic material part provided on the coil part, made of a magnetic material, and exposing the second surface, wherein a surface area of the first surface is larger than a surface area of the second surface.

Abstract: An example method for attaching a ball grid array chip to a circuit board includes providing an adapter for attaching a chip with a plurality of solder balls to a circuit board, the adapter having an adapter substrate made from a material having substantially the same coefficient of thermal expansion as the substrate used in the chip and having at least one electrical contact site on a mounting surface of the adapter substrate for engaging a solder ball on the ball grid array chip and a plurality of lead wires extending from each side of the adapter substrate. At least one of the lead wires is electrically connected to at least one electrical contact site on the adapter substrate.

Abstract: A photovoltaic module and its manufacturing method. The module includes a first support wafer made of sintered silicon and a second layer of single-crystal silicon.

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: The disclosed light emitting diode includes a substrate provided, at a surface thereof, with protrusions, a buffer layer formed over the entirety of the surface of the substrate, a first semiconductor layer formed over the buffer layer, an active layer formed on a portion of the first semiconductor layer, a second semiconductor layer formed over the active layer, a first electrode pad formed on another portion of the first semiconductor layer, except for the portion where the active layer is formed, and a second electrode pad formed on the second semiconductor layer. Each protrusion has a side surface inclined from the surface of the substrate at a first angle, and another side surface inclined from the surface of the substrate at a second angle different from the first angle.

Abstract: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.

Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.

Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

Abstract: A method for manufacturing a semiconductor package includes the steps of forming first circuit patterns on an upper surface of a carrier substrate. Bumps are formed in recesses defined on the upper surface of the carrier substrate. An insulation layer is formed on the upper surface of the carrier substrate to cover the first circuit patterns. Second circuit patterns are formed on an upper surface of the insulation layer so as to be electrically connected with the first circuit patterns. The carrier substrate is then separated from the insulation layer.

Abstract: A method of processing a wafer includes establishing a fine of symmetry defining left and right die areas on a front side of the wafer and left and right die areas on a back side. A first mask is used to form a first interconnection layer on the left and right die areas comprising a first portion on the left die area and second portion different than the first portion on the right die area. A second mask is used to form a second interconnection layer on the left and right die areas comprising a third portion on the left die area and fourth portion different than the third portion on the right die area. The first mask is reused to form a third interconnection layer on the left and right die areas on a back side, and the second mask to form a fourth interconnection layer on the left and right die areas on a back side.

Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package comprises a substrate, a first metal layer, a first dielectric layer, a first upper electrode, a first protective layer, a second metal layer and a second protective layer. The substrate has at least one via structure. The first metal layer is disposed on a first surface of the substrate, and comprises a first lower electrode. The first dielectric layer is disposed on the first lower electrode. The first upper electrode is disposed on the first dielectric layer, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor. The first protective layer encapsulates the first capacitor. The second metal layer is disposed on the first protective layer, and comprises a first inductor. The second protective layer encapsulates the first inductor.

Abstract: A semiconductor mounting substrate according to the present invention comprises: a substrate; a semiconductor device, mounted on this substrate; solder bumps, which connect the semiconductor device and the substrate; a first resin, filled in a space between the semiconductor device and the substrate; and electronic components, mounted on a face side of the semiconductor device where the semiconductor device is mounted, wherein bond strength reinforcing resin section is provided at least between a side face in the vicinity of a corner part of the semiconductor device and a substrate surface of the substrate in a position corresponding to the corner part.

Abstract: A method for fabricating AlxGa1-xN-cladding-free nonpolar III-nitride based laser diodes or light emitting diodes. Due to the absence of polarization fields in the nonpolar crystal planes, these nonpolar devices have thick quantum wells that function as an optical waveguide to effectively confine the optical mode to the active region and eliminate the need for Al-containing waveguide cladding layers.

Abstract: The electronic device comprises an ESD device (20) for protection against electrostatic discharge and provided with suitable protection elements (22) in combination with an integrated circuit (10). The integrated circuit (10) is particularly a so-called bridging circuit or driver circuit for external devices such as SIM cards, memory sticks, USB busses or 12C busses. The ESD device (20) is provided with a chip scale package in that the bumps (40) can be placed on a printed circuit board directly. The integrated circuit (10) is stacked on the ESD device (20).

Abstract: An integrated circuit (IC) includes a substrate having a semiconducting surface, a first array of devices on and in the semiconducting surface including first and second coacting current conducting nodes, a plurality of layers disposed on the substrate and including at a electrically conductive layers and dielectric layer, and a plurality of bump pads on or in the top surface of the dielectric layers. In the IC, the electrically conductive layers define electrical traces, where a first portion of the electrical traces contact a first portion of the bump pads exclusively to a portion of the first coacting current conducting nodes, where a second portion of the electrical traces contact a second portion of the bump pads exclusively to a portion of the second coacting current conducting nodes, and where the electrical traces are electrically isolated from one another by the dielectric layers.

Abstract: The outer peripheral portion of a substrate is provided with a first peripheral edge and a second peripheral edge. The first peripheral edge is provided on the edge portion of a first upper surface of the substrate on which a light-emitting diode element is mounted. The second peripheral edge is formed either on an extension of an imaginary line connecting an edge of the light-emitting facet of the light-emitting diode element and the first peripheral edge or inwardly of the extension. The second peripheral edge is located at a position where the first peripheral edge blocks direct light from the light-emitting diode element. This configuration prevents the second upper surface of the substrate provided between the first peripheral edge and the second peripheral edge from becoming deteriorated due to the direct light.

Abstract: An apparatus having a substrate, an LED light source attached to the substrate, an electrical connector attached to the substrate and electrically connected to the LED light source, a potting material on the substrate and covering at least a portion of the electrical connector; and a barrier separating the potting material from the LED light source, the barrier having a height that exceeds the thickness of the potting material on the substrate.

Abstract: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Abstract: A semiconductor process is provided. First, a silicon base is provided. Next, a surface of the silicon base is partially exposed and at least a stair structure is formed on the silicon base by etching the surface of the silicon base. The stair structure has a first notch with a first depth and a second notch with a second depth. The first depth is smaller than the second depth, and a diameter of the first notch is larger than a diameter of the second notch. A final insulating layer and a metal seed layer are sequentially formed on the stair structure. A patterned photoresist layer is formed on the metal seed layer. A circuit layer coving exposed portions of the metal seed layer located above the first notch is formed. The patterned photoresist layer and portions of the metal seed layer disposed below the patterned photoresist layer are then removed.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

Abstract: A semiconductor package in which an electronic device chip is provided in a cavity of a silicon substrate stacked product constituted by stacking a plurality of silicon substrates.

Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.

Abstract: A substrate with which a semiconductor device with excellent electric characteristics and high reliability can be manufactured is provided. An aspect of the invention is a method for manufacturing a substrate for manufacturing a semiconductor device: a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are stacked in this order over a surface of a semiconductor substrate by a thermal CVD method, and then a weakened layer is formed at a given depth of the semiconductor substrate; the semiconductor substrate and a substrate having an insulating surface are arranged to face each other, and the second silicon oxide film provided for the semiconductor substrate and a supporting substrate are bonded to each other; and the semiconductor substrate is separated at the weakened layer by heat treatment, whereby a semiconductor film separated from the semiconductor substrate is left over the substrate having the insulating surface.

Abstract: A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.

Abstract: A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive layer formed on the lower insulating layer; an upper insulating layer formed on the electrically conductive layer, the upper insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; and a semiconductor layer formed on the upper insulating layer.

Abstract: A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.

Abstract: A memory device and a manufacturing method thereof are provided. The manufacturing method of memory device includes the following steps. Firstly, a substrate having a substrate surface is provided. Next, at least two memory units separated via a space are formed on the substrate. Then, an insulating layer covering the memory units and the substrate surface is formed. After that, a mask layer only covering the bottom of the insulating layer is formed on the insulating layer. Afterwards, the part of the insulating layer partially covered by the mask layer is etched. Then, the mask layer is removed. Next, the part of the insulating layer where the mask layer is removed is etched. Lastly, a protecting layer is formed on the memory units and in the space between the memory units.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are ref lowed and fused together.

Abstract: An integrated circuit package system is provided including forming an external interconnect, providing a contoured integrated circuit die having both an extension and a base portion with the extension extending beyond the base portion, placing the contoured integrated circuit die with the base portion coplanar with the external interconnect and the extension overhanging the external interconnect, connecting the contoured integrated circuit die and the external interconnect, and forming a package encapsulation over the contoured integrated circuit die and the external interconnect with both partially exposed.

Abstract: A single-crystal silicon region on insulator on silicon intended to receive at least one component, the insulator having overthicknesses.

Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.

Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.

Abstract: A semiconductor light-emitting device according to an embodiment of the present invention includes chip LEDs formed on a silicon submount, in which a wiring pattern having a chip connecting terminal portion connecting the chip LEDs, an external connecting terminal portion connecting an external unit, and a plurality of lead portions connecting a corresponding chip connecting terminal portion and a corresponding external connecting terminal portion is formed on the silicon submount, and an area of the chip connecting terminal portions is made larger than an area of a region where the chip connecting terminal portion overlaps with the chip LEDs. Accordingly, a semiconductor light-emitting device of high heat radiation property and heat resistance can be provided.

Abstract: Methods are disclosed for providing reduced particle generating silicon carbide. The silicon carbide articles may be used as component parts in apparatus used to process semiconductor wafers. The reduced particle generation during semiconductor processing reduces contamination on semiconductor wafers thus increasing their yield.

Abstract: A structure for sufficiently alleviating the thermal stress between an LSI and substrate and allowing the LSI to be detached from a substrate easily is provided. In a flip-chip type assembly according to the present invention, an interposer made of silicon intervenes between the device and the substrate. The LSI and the interposer are connected with a solder and, the interposer and the substrate are connected with a conductive resin. The conductive resin alleviates the thermal stress between the substrate and the interposer. The LSI can be detached easily by heating the solder. The thermal stress between the LSI and the interposer can be reduced because both of them are made of silicon.

Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.

Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.