Packaging, Interconnects, And Markings For Semiconductor Or Other Solid-state Devices (epo) Patents (Class 257/E23.001)

  • Patent number: 9041220
    Abstract: A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: May 26, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Brian M. Henderson, Shiqun Gu
  • Patent number: 9006901
    Abstract: A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached on the third contact pad, and a plurality of conductive structures electrically connecting electrodes at a front surface of the semiconductor chip with the corresponding first contact pads in the first sets of first contact pads.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: April 14, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yuping Gong, Yan Xun Xue, Ming-Chen Lu, Ping Huang, Jun Lu, Hamza Yilmaz
  • Patent number: 9000587
    Abstract: A wafer-level package device and techniques for fabricating the device are described that include embedding a silicon chip onto an active device wafer or a passive device wafer, where the embedded silicon chip is a thin chip (e.g., <50 ?m). In implementations, the wafer-level package device that employs the techniques of the present disclosure includes an active device wafer, a thin integrated circuit chip, an encapsulation structure covering at least a portion of the active device wafer and the thin integrated circuit chip, a redistribution layer structure, and at least one solder bump for providing electrical interconnectivity. Once the wafer is singulated into semiconductor devices, each semiconductor device including the embedded thin integrated circuit chip may be mounted to a printed circuit board.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 7, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Amit S. Kelkar, Vivek S. Sridharan
  • Patent number: 8994159
    Abstract: To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: March 31, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Nakamura, Akira Muto, Nobuya Koike, Atsushi Nishikizawa, Yukihiro Sato, Katsuhiko Funatsu
  • Patent number: 8994185
    Abstract: A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. A conductive micro via array is formed outside a footprint of the semiconductor die and over the semiconductor die and encapsulant. A first through-mold-hole (TMH) is formed including a step-through-hole structure through the encapsulant to expose the conductive micro via array. An insulating layer is formed over the semiconductor die and the encapsulant. A micro via array is formed through the insulating layer and outside the footprint of the semiconductor die. A conductive layer is formed over the insulating layer. A conductive ring is formed comprising the conductive micro via array. A second TMH is formed partially through the encapsulant to a recessed surface of the encapsulant. A third TMH is formed through the encapsulant and extending from the recessed surface of the encapsulant to the conductive micro via array.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen
  • Patent number: 8994184
    Abstract: A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Reza A. Pagaila
  • Patent number: 8975738
    Abstract: A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 8946718
    Abstract: A semiconductor having an active layer; a gate insulating film in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second, nitride insulating film. A first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Masahiko Hayakawa, Shunpei Yamazaki
  • Patent number: 8933565
    Abstract: Integrated circuits having electrically conductive traces are described. The electrically conductive traces may be formed of multiple electrically conductive layers. One or more of the multiple electrically conductive layers may have a cut formed therein to form a gap in that electrically conductive layer. One or more electrical conductive layers of the electrical conductive traces may bridge the gap.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: January 13, 2015
    Assignee: Sand 9, Inc.
    Inventors: Guiti Zolfagharkhani, Jan H. Kuypers
  • Patent number: 8928143
    Abstract: To prevent two contacts that have different heights, share at least one interlayer insulating film and are disposed close to each other from being short-circuited to each other due to misalignment thereof, a semiconductor device according to the invention has a recess in an interlayer insulating film in which a first contact having a lower height, the recess being formed by the upper surface of the first contact, and a silicon nitride sidewall is formed in the recess to extend from the upper surface of the first contact and along the side surface of the recess.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: January 6, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kazuo Yamazaki
  • Patent number: 8916416
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: December 23, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Glenn Omandam, Yaojian Lin, Hin Hwa Goh
  • Patent number: 8907492
    Abstract: Power supply plugs, which couple a power supply active region to a power supply metal interconnect, include a plurality of first plugs, which are arranged at first pitches of a predetermined length, and a second plug, which is spaced apart from the closest one of the first plugs by a center-to-center distance different from an integral multiple of the predetermined length. Among the power supply plugs, the second plug is closest to a third plug, which is an interconnect plug closest to the power supply active region and the power supply metal interconnect.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: December 9, 2014
    Assignee: Panasonic Corporation
    Inventor: Kazuyuki Nakanishi
  • Patent number: 8907459
    Abstract: A three-dimensional semiconductor integrated circuit device is provided. A first semiconductor chip includes a solid-state circuit and is smaller than a base, and is stacked on the base. The first chip is buried by a first filling material having approximately the same contour as the base. Buried electrodes that penetrate through the first chip along its thickness direction are formed in the first chip. A second semiconductor chip includes a solid-state circuit and is smaller than the base, and is stacked on the first chip. The second chip is buried by a second filling material having approximately the same contour as the base. Buried electrodes that penetrate through the second chip along its thickness direction are formed in the second chip. The first and second filling materials have processibilities required for forming the buried electrodes and thermal expansion coefficients equivalent to those of the first and second chips, respectively.
    Type: Grant
    Filed: January 15, 2007
    Date of Patent: December 9, 2014
    Assignee: Zycube Co., Ltd.
    Inventor: Manabu Bonkohara
  • Patent number: 8890305
    Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: November 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Yoichiro Kurita
  • Patent number: 8884427
    Abstract: A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 11, 2014
    Assignee: Invensas Corporation
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Michael Newman, Terrence Caskey
  • Patent number: 8853845
    Abstract: A component including at least one active element hermetically encapsulated in a cavity formed between a support and a cover, in which the support and the cover are made from an electrically conductive material, and are insulated electrically from one another, and include a first electrical connection between the active element and the support, and a second electrical connection, separate from the first connection, between the active element and the cover, and in which: the active element is securely attached to the support through a dielectric layer positioned between the support and the active element, and between the support and the cover; the second electrical connection includes a second portion of electrically conductive material electrically connected to the cover, positioned on the dielectric layer and electrically in contact with an electrically conductive sealing bead providing hermetic secure attachment of the cover to the support.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 7, 2014
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, Sorin CRM S.A.S.
    Inventors: Jean-Charles Souriau, Guy-Michel Parat, Renzo Dal Molin
  • Patent number: 8846446
    Abstract: In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pyoung-Wan Kim, Teak-Hoon Lee, Chul-Yong Jang
  • Patent number: 8836105
    Abstract: A method of assembling a semiconductor device includes providing a substrate having an array of substrate elements linked by substrate corner elements and separated by slots extending between the corner elements. Semiconductor dies are positioned on the substrate elements. A cap, frame and contact structure is provided that has a corresponding array of caps supported by corner legs linking the caps to frame corner elements, frame elements linking the frame corner elements, and sets of electrical contact elements supported by the frame elements. The cap, frame and contact structure is fitted on the substrate with the caps extending over corresponding dies, the frame corner elements extending over the substrate corner elements, and the sets of electrical contact elements disposed in the slots. The dies are connected electrically with the electrical contact elements and the assembly is encapsulated and singulated. Singulating removes the frame elements.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: September 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Baoguan Yin, Junhua Luo, Deguo Sun
  • Patent number: 8829665
    Abstract: A semiconductor chip includes a semiconductor substrate with a top surface and a bottom surface. An active layer may be formed on the top surface of the semiconductor substrate and may comprise one or more signal pads and one or more chip selection pads on an upper surface of the active layer. First and second through electrodes may be formed to pass through the semiconductor substrate and the active layer, with the first through electrodes being electrically connected with the signal pads and the second through electrodes being electrically connected with the chip selection pads. A side electrode may be formed on a side surface of the semiconductor chip in such a way as to be connected with a second through electrode.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: September 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Ju Heon Yang
  • Patent number: 8829684
    Abstract: An integrated circuit package has a host integrated circuit with an active front side that is surface-mounted on a support and an inactive backside. Conductive pathways extend between the front and back sides of the integrated circuit. A redistribution layer on the back side of the host integrated circuit provides conductive traces and contact pads. The traces of the redistribution layer establish connection between the conductive pathways and the contact pads. At least one additional component is surface-mounted on the back side of the host integrated circuit by electrical connection to the contact pads of the redistribution layer to provide a compact three-dimensional structure. In an alternative embodiment, the additional components can be mounted on the active side.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: September 9, 2014
    Assignee: Microsemi Semiconductor Limited
    Inventors: Piers Tremlett, Michael Anthony Higgins, Martin McHugh
  • Patent number: 8816477
    Abstract: A semiconductor package includes a semiconductor chip having a front surface and a back surface facing away from the front surface; a through electrode formed in the semiconductor chip and passing through the front surface and the back surface; and a contamination preventing layer formed in the semiconductor chip, the through electrode passing through the contamination preventing layer.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: August 26, 2014
    Assignee: SK Hynix Inc.
    Inventor: Ho Young Son
  • Patent number: 8810018
    Abstract: A stacked integrated circuit package system is provided forming a first molded chip comprises attaching a conductor on a wafer, applying an encapsulant around the conductor, and exposing a surface of the conductor in the encapsulant, attaching a first electrical interconnect on the conductor of the first molded chip and stacking an integrated circuit device on the first molded chip with an electrical connector of the integrated circuit device connected to the conductor of the first molded chip with the first electrical interconnect.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: August 19, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jong-Woo Ha, Sang-Ho Lee, Soo-San Park
  • Patent number: 8796845
    Abstract: An electronic device according to the invention includes: a substrate; an MEMS structure formed above the substrate; and a covering structure defining a cavity in which the MEMS structure is arranged, wherein the covering structure has a first covering layer covering from above the cavity and having a through-hole in communication with the cavity and a second covering layer formed above the first covering layer and closing the through-hole, the first covering layer has a first region located above at least the MEMS structure and a second region located around the first region, the first covering layer is thinner in the first region than in the second region, and a distance between the substrate and the first covering layer in the first region is longer than a distance between the substrate and the first covering layer in the second region.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: August 5, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Yoko Kanemoto, Akira Sato, Shogo Inaba
  • Patent number: 8796830
    Abstract: In an embodiment, an IC assembly comprises an IC having a top surface comprising a plurality of input/output terminations, a plurality of leads arranged around the IC, a plurality of bond wires, and an encapsulant. Each lead has a first surface and a second surface opposite the first surface, and has a feature protruding from the first surface proximate an inward end of the lead nearest the IC. The feature extends from the first surface to approximately a plane that includes a bottom surface of the IC. Each bond wire connects a respective lead to a respective I/O terminal on the IC. The encapsulant seals the bond wires, the IC, and a first portion of the leads that includes the feature. The feature creates on offset from the bottom of the IC to permit the encapsulant to surround the first portion.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: August 5, 2014
    Assignee: Google Inc.
    Inventor: Joseph C. Fjelstad
  • Patent number: 8791532
    Abstract: The sensor assembly comprises a substrate (1), such as a flexible printed circuit board, and a sensor chip (2) flip-chip mounted to the substrate (1), with a first side (3) of the sensor chip (2) facing the substrate (1). A sensing area (4) and contact pads (5) are integrated on the first side (3) of the sensor chip (2) and located in a chamber (17) between the substrate (1) and the sensor chip (2). Chamber (17) is bordered along at least two sides by a dam (16). Underfill (18) and/or solder flux is arranged between the sensor chip (2) and the substrate (1), and the dam (16) prevents the underfill from entering the chamber (17). An opening (19) extends from the chamber to the environment and is located between the substrate (1) and the sensor chip (2) or extends through the sensor chip (2).
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: July 29, 2014
    Assignee: Sensirion AG
    Inventors: Markus Graf, Werner Hunziker, Franziska Brem, Felix Mayer
  • Patent number: 8791561
    Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: July 29, 2014
    Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.
    Inventors: Sadahiro Kishii, Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi, Masato Tanaka, Akio Rokugawa
  • Patent number: 8772083
    Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.
    Type: Grant
    Filed: September 10, 2011
    Date of Patent: July 8, 2014
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Andrew K W Leung, Roden R. Topacio, Yu-Ling Hsieh, Yip Seng Low
  • Patent number: 8772944
    Abstract: A semiconductor substrate includes a via-hole that extends from a first surface to a second surface. An electrode pad layer that serves as the bottom of the via-hole is disposed on the second surface. An insulating layer is formed on the first surface of the semiconductor substrate and the sidewall of the via-hole. A metal layer is formed on the first surface of the semiconductor substrate and the sidewall of the via-hole with the insulating layer interposed therebetween and is directly formed on the bottom of the via-hole. An inclined surface is formed on the sidewall of the via-hole such that the bottom of the via-hole has a smaller opening size than the open end of the via-hole. The inclined surface has asperities.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: July 8, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tadanori Suto
  • Patent number: 8772942
    Abstract: A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: July 8, 2014
    Assignees: International Business Machines Corporation, Toshiba America Electronic Components, Inc.
    Inventors: Daniel C. Edelstein, Takeshi Nogami, Kazumichi Tsumura, Takamasa Usui
  • Patent number: 8759981
    Abstract: A multilayer system includes first and second functional layers, for example, semiconductor layers. A third or intermediate layer is disposed between the first and second functional layers and adheres relatively well to the first and second layers yet has relatively little or no detrimental effect on the functionality of the first and second layers. The third layer is applied to the first layer. Anchoring elements are provided which are partly embedded in the third layer, and the second layer is secured to the third layer by the anchoring elements. This structure yields good adhesion between the three layers, because the third layer adheres relatively well to the first layer and the third layer and the second layer are mechanically bonded together relatively strongly by the anchoring elements.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: June 24, 2014
    Assignee: Micronas GmbH
    Inventors: Heinz Peter Frerichs, Herbert Verhoeven
  • Patent number: 8754517
    Abstract: Disclosed herein is a double side cooling power semiconductor module including: a first cooler having a concave part formed in one surface thereof in a thickness direction; a first semiconductor chip mounted on the concave part of the first cooler; a second cooler having one surface and the other surface and formed on one surface of the first cooler so that one surface thereof contacts the first semiconductor chip; a circuit board formed on the other surface of the second cooler; a second semiconductor chip mounted on the circuit board; and a flexible substrate having a circuit layer electrically connecting the first and second semiconductor chips to each other.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: June 17, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kwang Soo Kim, Young Ki Lee, Ji Hyun Park, Bum Seok Suh
  • Patent number: 8753975
    Abstract: A method includes forming a trench/via in a layer of insulating material, forming a first layer comprised of silicon or germanium on the insulating material in the trench/via, forming a copper-based seed layer on the first layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: June 17, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Larry Zhao, Ming He, Sean Lin, John Iacoponi, Errol Todd Ryan
  • Patent number: 8754412
    Abstract: An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xiaojun Yu, Anda C. Mocuta, Toshiaki Kirihata
  • Patent number: 8749068
    Abstract: A mounting method of sequentially mounting elements on a substrate includes a mounting process of mounting one element, which is taken out by a take-out part from an accommodating part in which the elements are accommodated, on a first contact region of the surface of the substrate where a liquid is coated. The method further includes a coating process of coating a liquid, by a coating part movably provided together with the take-out part, on a contact region of the surface of the substrate different from the first contact region when the one element is mounted on the first region.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: June 10, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Michikazu Nakamura, Masahiko Sugiyama, Dai Shinozaki, Naoki Akiyama
  • Patent number: 8742558
    Abstract: A method of protecting sensitive components prior to, during or subsequent to advanced die packaging processing includes applying a metal stack layer such as titanium/copper (Ti/Cu) onto the front surface of a die assembly such that the die assembly front surface is covered with the metal stack layer. A layer of titanium/copper/titanium (Ti/Cu/Ti) or a solder alloy is also applied to the back surface of the die assembly such that the back surface of the die assembly is covered with the Ti/Cu/Ti layer or solder alloy. The front surface metal stack layer and the back surface Ti/Cu/Ti layer or solder alloy prevent degradation of die metallization prior to, during or subsequent to the advanced die packaging processing.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: June 3, 2014
    Assignee: General Electric Company
    Inventors: Paul Alan McConnelee, Arun Virupaksha Gowda, Elizabeth Ann Burke, Kevin Matthew Durocher
  • Patent number: 8736002
    Abstract: The sensor assembly comprises a substrate (1), such as a flexible printed circuit board, and a sensor chip (2) flip-chip mounted to the substrate (1), with a first side (3) of the sensor chip (2) facing the substrate (1). A sensing area (4) and contact pads (5) are integrated on the first side (3) of the sensor chip (2). Underfill (18) and/or solder flux is arranged between the sensor chip (2) and the substrate (1). The sensor chip (2) extends over an edge (12) of the substrate (1), with the edge (12) of the substrate (1) extending between the contact pads (5) and the sensing area (4) over the whole sensor chip (2). A dam (16) can be provided along the edge (12) of the substrate (1) for even better separation of the underfill (18) and the sensing area (4). This de sign allows for a simple alignment of the sensor chip on the substrate (1) and prevents underfill (18) from covering the sensing area (4).
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: May 27, 2014
    Assignee: Sensirion AG
    Inventors: Markus Graf, Werner Hunziker, Franziska Brem, Felix Mayer
  • Patent number: 8729684
    Abstract: An interposer chip may include a substrate, a plurality of upper terminals, a plurality of lower terminals, a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals, a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals and a cut test pattern disposed between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Lyeol Park, Sung-Dong Cho, Sin-Woo Kang
  • Patent number: 8716108
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a circuit substrate having an active side opposite to an inactive portion; attaching a nonconductive cover to the active side; forming a separation-gap partially cutting into the nonconductive cover and the circuit substrate to a kerf depth; attaching a back-grinding tape to the nonconductive cover; removing a portion of the inactive portion; and exposing the nonconductive cover by removing the back-grinding tape.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: May 6, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Hun Teak Lee, DaeWook Yang, Yeongbeom Ko
  • Patent number: 8703542
    Abstract: The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung
  • Patent number: 8703539
    Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsiun Lee, Kai-Chiang Wu
  • Patent number: 8704353
    Abstract: A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first plurality of electrically non-functional interconnects on a back side of the first semiconductor chip. Additional chips may be stacked on the first semiconductor chip.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 22, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Su, Bryan Black, Neil McLellan, Joe Siegel, Michael Alfano
  • Patent number: 8704365
    Abstract: An integrated circuit packaging system includes: a carrier, having a carrier top side and a carrier bottom side, without an active device attached to the carrier bottom side; an interconnect over the carrier; and a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation, and with the carrier top side partially exposed with the cavity.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: April 22, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: DongSam Park, Dongjin Jung
  • Patent number: 8698273
    Abstract: A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: April 15, 2014
    Assignee: Panasonic Corporation
    Inventors: Tomoaki Ikegami, Hidetoshi Nishimura, Kazuyuki Nakanishi
  • Patent number: 8698293
    Abstract: A multi-chip package comprises a first chip accommodated in a first housing and a second chip accommodated in a second housing. The first housing and the second housing are arranged in a laterally spaced-apart relationship defining a gap between the first housing and the second housing. An interconnecting structure is configured to span the gap and to electrically couple the first chip and the second chip.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 15, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl
  • Patent number: 8685796
    Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: April 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichiro Kurita, Koji Soejima, Masaya Kawano
  • Patent number: 8680662
    Abstract: A microelectronic assembly can include a first microelectronic device and a second microelectronic device. Each microelectronic device has a die structure including at least one semiconductor die and each of the microelectronic devices has a first surface, a second surface remote from the first surface and at least one edge surface extending at angles other than a right angle away from the first and second surfaces. At least one electrically conductive element extends along the first surface onto at least one of the edge surfaces and onto the second surface. At least one conductive element of the first microelectronic device can be conductively bonded to the at least one conductive element of the second microelectronic device to provide an electrically conductive path therebetween.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: March 25, 2014
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Ilyas Mohammed, Laura Mirkarimi, Moshe Kriman
  • Patent number: 8680551
    Abstract: A vertically conducting LED comprising, in a layered arrangement: a highly thermally conductive submount wherein the highly conductive submount has a thermal conductivity of at least 100 W/m0K; a p-type layer comprising Al1-x-yInyGax N wherein 0?x?1 and 0?y?1; a quantum well layer comprising Al1-x-yInyGaxN wherein 0?x?1 and 0?y?1; an n-type layer comprising Al1-x-yInyGaxN wherein 0?x?1 and 0?y?1; and an n-type contact layer wherein the LED has a peak emission at 200-365 nm.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: March 25, 2014
    Assignee: Nitek, Inc.
    Inventors: Vinod Adivarahan, Qhalid Fareed, Asif Khan
  • Patent number: 8680666
    Abstract: A wire bond free power module assembly consists of a plurality of individual thin packages each consisting of two DBC wafers which sandwich one or more semiconductor die. The die electrodes and terminals extend through one insulation covered end of the wafer sandwich and the outer sides of the sandwiches are the outer copper plates of the DBC wafers which are in good thermal communication with the semiconductor die but are electrically insulated therefrom. The plural packages may be connected in parallel by lead frames on the terminals and the packages are stacked with a space between them to expose both sides of all packages to a cooling medium, either the fingers of a conductive comb or a fluid heat exchange medium.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: March 25, 2014
    Assignee: International Rectifier Corporation
    Inventor: Henning M. Hauenstein
  • Patent number: 8673700
    Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: March 18, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy
  • Publication number: 20140061888
    Abstract: The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng LIN, Chin-Chuan CHANG, Jui-Pin HUNG