Abstract: One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices.

Abstract: A power block includes an insulating substrate, a conductive pattern formed on the insulating substrate, a power semiconductor chip bonded onto the conductive pattern by lead-free solder, a plurality of electrodes electrically connected to the power semiconductor chip and extending upwardly away from the insulating substrate, and a transfer molding resin covering the conductive pattern, the lead-free solder, the power semiconductor chip, and the plurality of electrodes, wherein surfaces of the plurality of electrodes are exposed at an outer surface of the transfer molding resin and lie in the same plane as the outer surface, the outer surface being located directly above the conductive pattern.

Abstract: A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer.

Abstract: A method for manufacturing a semiconductor device includes: a first etching step of etching a TEOS layer from a glass substrate to partially expose a SiN layer; a second etching step, conducted separately and independently from the first etching step, of wet-etching the exposed SiN layer to partially expose the glass substrate; and a bonding step of bonding a driver portion to the exposed glass substrate.

Abstract: A semiconductor mounting substrate according to the present invention comprises: a substrate; a semiconductor device, mounted on this substrate; solder bumps, which connect the semiconductor device and the substrate; a first resin, filled in a space between the semiconductor device and the substrate; and electronic components, mounted on a face side of the semiconductor device where the semiconductor device is mounted, wherein bond strength reinforcing resin section is provided at least between a side face in the vicinity of a corner part of the semiconductor device and a substrate surface of the substrate in a position corresponding to the corner part.

Abstract: A method for manufacture of a nanophotonic device can include the step of operatively coupling a planar light source and a photodetector with an optical waveguide. The planar light source, photodetector and optical waveguide can then be monolithically integrated in direct contact with a sapphire substrate, along with an electronic component that is also in direct contact with the sapphire substrate.

Abstract: A chip-type semiconductor ceramic electronic component including a ceramic body made of a semiconductor ceramic, first external electrodes formed on opposite end surfaces of the ceramic body, and second external electrodes extending to cover surfaces of the first external electrodes and part of side surfaces of the ceramic body. A curvature radius of a corner portion of the ceramic body is R (?m), a maximum thickness of a layer of the first external electrode layer, which is in contact with the ceramic body, measured from the end surface of the ceramic body is y (?m), and a minimum thickness of a layer of the second external electrode, which is in contact with the side surface of the ceramic body, measured from an apex of the corner portion of the ceramic body is x (?m), and 20?R?50, ?0.4 x+0.6?y?0.4 is satisfied when 0.5?x?1.1, and ?0.0076 x+0.16836?y?0.4 is satisfied when 1.1?x?9.0.

Abstract: A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, which forms a second external contact element. The first and the second carriers are arranged in such a way that the first and the second extension point in different directions.

Abstract: The present invention provides an aluminum nitride substrate and an aluminum nitride circuit board having excellent insulation characteristics and heat dissipation properties and having high strength, a semiconductor apparatus, and a method for manufacturing an aluminum nitride substrate.

Abstract: A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer.

Abstract: The outer peripheral portion of a substrate is provided with a first peripheral edge and a second peripheral edge. The first peripheral edge is provided on the edge portion of a first upper surface of the substrate on which a light-emitting diode element is mounted. The second peripheral edge is formed either on an extension of an imaginary line connecting an edge of the light-emitting facet of the light-emitting diode element and the first peripheral edge or inwardly of the extension. The second peripheral edge is located at a position where the first peripheral edge blocks direct light from the light-emitting diode element. This configuration prevents the second upper surface of the substrate provided between the first peripheral edge and the second peripheral edge from becoming deteriorated due to the direct light.

Abstract: A nanophotonic device. The device includes a substrate, at least one light emitting structure and at least one electronic component. The at least one light emitting structure is capable of transmitting light and is monolithically integrated on the substrate. The at least one electronic component is monolithically integrated on the substrate. A method for fabricating nanophotonic devices is also described.

Abstract: A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip.

Abstract: A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.

Abstract: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Abstract: A semiconductor module includes a multilayer substrate. The multilayer substrate includes a first metal layer and a first ceramic layer over the first metal layer. An edge of the first ceramic layer extends beyond an edge of the first metal layer. The multilayer substrate includes a second metal layer over the first ceramic layer and a second ceramic layer over the second metal layer. An edge of the second ceramic layer extends beyond an edge of the second metal layer. The multilayer substrate includes a third metal layer over the second ceramic layer.

Abstract: A method for producing a power semiconductor module including forming a contact between a contact region and a contact element as an ultrasonic welding contact via a sonotrode. The ultrasonic welding operation also being used for joining the contact regions with the contact ends and consequently for joining the contacts and the foot regions.

Abstract: Side-mountable semiconductor light emitting device packages include an electrically insulating substrate having a front face and a back face and a side face extending therebetween. The side face is configured for mounting on an underlying surface. An electrically conductive contact is provided proximate an edge of the substrate on the back face of the substrate and/or on a recessed region on the side face of the substrate. The contact is positioned to be positioned proximate an electrical connection region of the underlying surface when the semiconductor light emitting device package is side mounted on the underlying surface. A conductive trace extends along the front face of the substrate and is electrically connected to the contact. A semiconductor light emitting device is mounted on the front face of the substrate and electrically connected to the conductive trace.

Abstract: A through electrode is formed prior to fabricating a semiconductor device by using a standard manufacturing method. Aside face of the through electrode is insulated from a semiconductor substrate by an insulating film, while the top face thereof is covered with a protective insulating film. These insulating films covering the through electrode protect a conductor of the through electrode and prevent emission of a contaminant from the conductor. Standard manufacturing conditions can be applied without change.

Abstract: A method for producing a capping wafer for a sensor having at least one cap includes: production of a contacting via extending through the wafer, and, temporally subsequent thereto, filling of the contacting via with an electrically conductive material.

Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.

Abstract: A method for fabricating a semiconductor component with through interconnects can include the steps of providing a semiconductor substrate with substrate contacts, and forming openings from a backside of the substrate aligned with the substrate contacts. The method can also include the steps of providing an interposer substrate (or alternately a second semiconductor substrate), forming projections on the interposer substrate (or on the second semiconductor substrate), and forming conductive vias in the projections. The method can also include the steps of placing the projections in physical contact with the openings, and placing the conductive vias in electrical contact with the substrate contacts. The method can also include the steps of bonding the conductive vias to the substrate contacts, and forming terminal contacts on the interposer substrate (or alternately on one of the semiconductor substrates) in electrical communication with the conductive vias.

Abstract: A Cu—Mo substrate 10 according to the present invention includes: a Cu base 1 containing Cu as a main component; an Mo base having opposing first and second principal faces 2a, 2b and containing Mo as a main component, the second principal face 2b of the Mo base 2 being positioned on at least a portion of a principal face 1a of the Cu base 1; and a first Sn—Cu-type alloy layer 3 covering the first principal face 2a and side faces 2c and 2d of the Mo base 2, the first Sn—Cu-type alloy layer 3 containing no less than 1 mass % and no more than 13 mass % of Sn.

Abstract: A network electronic component comprises a network-electronic-component substrate, a thin-film passive element provided on the substrate, and a plurality of external connection electrodes provided on the substrate in connection with the thin-film passive element.

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: The invention relates to a metal-ceramic substrate for electric circuits or modules, said substrate including a ceramic layer which is provided with at least one metallic layer of a first type applied to a surface of said ceramic layer in a plane manner. An insulating layer made up of a glass-containing material is applied to at least one partial region of a surface of the metallic layer of the first type, said surface opposing the ceramic layer, and a metallic layer of a second type is applied to the insulating layer, the insulating layer and the metallic layer of a second type respectively being thinner then the ceramic layer and the metallic layer of the first type.

Abstract: A member for a semiconductor device of low price, capable of forming a high quality plating layer on a surface, having heat conductivity at high temperature (100° C.) of more than or equal to 180 W/m·K and toughness that will not cause breaking due to screwing, and will not cause solder breaking due to heat stress when it is bonded to other member with solder, and a production method thereof are provided. A member for a semiconductor device (1) having a coefficient of thermal expansion ranging from 6.5×10?6/K to 15×10?6/K inclusive, and heat conductivity at 100° C.

Abstract: A collective substrate has through-holes. The through-holes each have an interior surface including taper surfaces which are tapered as having an opening size progressively decreasing from a main surface and an external connection surface toward a minimum size hole portion. A semiconductor element mount includes an insulative member cut out of the collective substrate. An imaging device includes an imaging element mounted in a region surrounded by a frame which is bonded to the main surface of the insulative member and closed by a cover. A light emitting diode component includes a light emitting element mounted on the main surface of the insulative member with the minimum size hole portion of the through-hole being filled with an electrically conductive material, the light emitting element being sealed with a fluorescent material and/or a protective resin.

Abstract: A technology providing an improvement in the durability in the condition of changing the temperature, while ensuring characteristics such as the applicability to applications utilizing larger electric current, lower resistance and the like can be achieved. A semiconductor device 100 includes a ceramic multiple-layered interconnect substrate 120, a silicon chip 110 that is flip-bonded to a chip-carrying region of the ceramic multiple-layered interconnect substrate 120, and an external connecting bumps 161 and an external connecting bumps 163, which are provided in the side that the silicon chip 110 of the ceramic multiple-layered interconnect substrate 120 is carried. The silicon chip 110 includes a front surface electrode and a back surface electrode.

Abstract: A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.

Abstract: A semiconductor module includes a multilayer substrate. The multilayer substrate includes a first metal layer and a first ceramic layer over the first metal layer. An edge of the first ceramic layer extends beyond an edge of the first metal layer. The multilayer substrate includes a second metal layer over the first ceramic layer and a second ceramic layer over the second metal layer. An edge of the second ceramic layer extends beyond an edge of the second metal layer. The multilayer substrate includes a third metal layer over the second ceramic layer.

Abstract: A high frequency ceramic package includes: a first conductive pattern placed on the top surface of a ceramic RF substrate; a second conductive pattern placed on the bottom surface of the ceramic RF substrate; a through hole for passing through the top surface and bottom surface of the ceramic RF substrate; a through hole metal layer which is filled up in the through hole and which connects the first conductive pattern and the second conductive pattern; a ceramic seal ring placed on the ceramic RF substrate; an insulating adhesive bond placed on the ceramic seal ring; and a ceramic cap placed on the insulating adhesive bond, wherein the second conductive pattern is used as an external terminal, and between the ceramic cap and the top surfaces of the ceramic seal ring is sealed with the insulating adhesive bond and it is simple for structure and excellent in high frequency characteristics.

Abstract: Projecting elongate stub walls are provided on the planar surfaces of a substrate at positions where bonding of the substrate to a clamping lid or base is to be carried out. On firing of the substrate, the surfaces thereof are mechanically processed but since the stub walls protrude from the substrate, the grinding and polishing tools make contact with the surfaces of these stub walls, rather than with the entire substrate surface. As a result, the area of the substrate to be processed is minimised and problems with dishing and erosion are alleviated. This allows the clamping lid, or frame to be bonded, using conventional conductive adhesive processes, avoiding the cracking and stress problems associated with non-uniformity of the surface of the ceramic substrates.

Abstract: A sensor package includes an image sensing chip having a front surface, a plurality of bumps, a glass cover plate, and a connector. The plurality of bumps are formed on the front surface, and are electrically connected to the image sensing chip. The glass cover plate has a bottom surface facing the front surface, and the glass cover plate has a plurality of transparent conductive wires formed on the bottom surface. A terminal of each of the transparent conductive wires is electrically connected to a respective bump, and another terminal of each of the transparent conductive wires extends out of an orthogonal projection area of the image sensing chip on the bottom surface. The connector is electrically connected to the another terminal of each of the transparent conductive wires.

Abstract: Disclosed is a power module having improved joint reliability. Specifically disclosed is a power module including a power module substrate wherein a circuit layer is brazed on the front surface of a ceramic substrate, a metal layer is brazed on the rear surface of the ceramic substrate and a semiconductor chip is soldered to the circuit layer. The metal layer is composed of an Al alloy having an average purity of not less than 98.0 wt. % but not more than 99.9 wt. % as a whole. In this metal layer, the Fe concentration in the side of a surface brazed with the ceramic substrate is set at less than 0.1 wt. %, and the Fe concentration in the side of a surface opposite to the brazed surface is set at not less than 0.1 wt. %.

Abstract: A silicon-based wafer such as a TSV interposer wafer having a first and second surfaces wherein a glass carrier is mounted on the second surface by a UV tape is held by a vacuum holder applied on the first surface and the glass carrier is removed from the silicon-based wafer by irradiating the UV tape with a UV light through the glass carrier. The silicon-based wafer is then flipped and placed onto a vacuum plate and secured to the vacuum plate by applying vacuum to the vacuum plate. The vacuum holder is then released from the silicon-based wafer leaving the silicon-based wafer secured to the vacuum plate for subsequent processing steps.

Abstract: A chip package includes a coreless package substrate and a chip. The coreless package substrate includes an interconnection structure and a ceramic stiffener. The interconnection structure has a first inner circuit, a carrying surface and a corresponding contact surface. The first inner circuit has multiple contact pads disposed on the contact surface. The ceramic stiffener is disposed on the carrying surface and has a first opening. In addition, the chip is disposed on the carrying surface and within the first opening and electrically connected to at least one of the contact pads.

Abstract: A ceramic substrate (100) includes a top surface, a plurality of identification marks (104), a protective compound (110), a bottom surface, and a plurality of grooves (106). The top surface includes a first area and a second area. The first area is defined at one or more edges portions of the top surface. The second area is defined inside the first area. The identification marks are arranged on the first area. The protective compound is covered on the second area. The grooves are defined at the bottom surface, and corresponding to the identification marks. A related method for breaking a ceramic substrate includes: (a) pasting one or more tapes on the first area; (b) covering protective compound on the second area; (c) removing the tapes; (d) cutting the protective compound according to the identification marks; and (e) breaking the ceramic substrate into individual circuit unit pieces along the grooves.

Abstract: Disclosed is a semiconductor package and method for package a semiconductor that has high reliability. A semiconductor package according to the present invention comprises a first substrate on which a circuit pattern and an electrode pad are formed; a second substrate which is adhered to the first substrate and on which a hole is formed; and a solder ball adhered to the electrode pad through the hole formed on the second substrate. Then, the second substrate is used as a solder resist. Accordingly, since the first substrate and the second substrate are formed of same material, the BGA package can be prevented from being cracked and being nonuniform when fired.

Abstract: An apparatus including a first electrode; a second electrode; a first and second ceramic material disposed between the first electrode and the second electrode, the second ceramic material having a greater electrical conductivity than the first ceramic material. A method including forming a first ceramic material film and a different second ceramic material film on a first electrode; and forming a second electrode on the second ceramic material film to form a capacitor structure having the first ceramic material film and the second ceramic material film disposed between the first electrode and the second electrode, wherein the first ceramic material has a conductivity selected to dampen undesired oscillations in electrical device operation to which the capacitor structure may be exposed. An apparatus including a first electrode; a second electrode; and a composite dielectric including a plurality of dielectric films including a different Curie temperature.

Abstract: A low-temperature co-fired ceramics (LTCC) substrate includes a plurality of substrate units and at least one cutting pattern. The cutting pattern is disposed between neighboring two of the substrate units. A semiconductor package including the LTCC substrate is also disclosed.

Abstract: The present invention relates to a substrate structure comprising at least two substrate layers extending in substantially parallel planes, which substrate layers are (Z-)interconnected in a direction substantially perpendicular to said planes. It comprises at least one adhesive film layer for interconnecting said at least two substrate layers, said adhesive film layer(s) comprising non-conductive portions and conductive portions. The position(s) of conductive portions is controllable such as to admit positioning of conductive portions at locations in the substrate layers where electrical conductivity is needed in a direction substantially perpendicular to the planar extension of, and between, two interconnected substrate layers.

Abstract: A wiring glass substrate includes a glass substrate formed of glass and having a plurality of holes formed at predetermined positions, bumps so formed as to be connected to a conductive material filling the holes and wirings formed on a surface opposite to a surface having the bumps formed thereon and electrically connecting a plurality of connection terminals arranged in intervals different from intervals of the holes to the conductive material. The shape of the conductive material is porous and porous electrodes are bonded to the inner wall surfaces of the holes by an anchor effect to increase the strength of the glass substrate.

Abstract: A multi-layer structure including a base insulating layer and a thin metal film layer (seed layer) is prepared. A plating resist layer is formed to have a prescribed pattern on the upper surface of the thin metal film layer. A metal plating layer is formed on the thin metal film layer exposed by electroplating. Then, the plating resist layer is removed, and the thin metal film layer in the region having the plating resist layer is removed. In this way, a conductive pattern including the thin metal film layer and the metal plating layer is formed. The upper surface of the base insulating layer in the region without the conductive pattern is subjected to roughening treatment. A cover insulating layer is formed on the upper surfaces of the base insulating layer and the conductive pattern. In this way, a printed circuit board is completed.

Abstract: A method of making an integrated circuit package includes forming a through hole in an integrated circuit and assembling a die containing the integrated circuit on a carrier so that the die is mechanically and electrically connected to the carrier. Thereafter, an underfill material is dispensed between the die and the carrier via the through hole.

Abstract: An integrated circuit package system comprising forming a first device unit, having a first external interconnect, and a second device unit, having a second external interconnect, in an array configuration; mounting an integrated circuit die over the first device unit; connecting the integrated circuit die and the first external interconnect; and encapsulating the integrated circuit die, the first device unit, and the second device unit with both the first external interconnect and the second external interconnect partially exposed.

Abstract: Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A trench is formed by etching the semiconductor exposing an inter-layered dielectric (ILD) layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the trench is removed, and the ILD layer is subsequently removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an L-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

Abstract: Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

Abstract: In a ceramic circuit board 1 prepared by integrally joining a circuit layer 4 composed of a clad member including a circuit plate 2 made of an Al plate and an Al—Si brazing material layer 3 to a ceramic substrate 6, a surface of the clad member adjacent to the Al—Si brazing material layer 3 is joined to the ceramic substrate 6 with an Al alloy film 5 therebetween, the Al alloy film 5 having a thickness of less than 1 ?m and being provided on the surface of the ceramic substrate 6. According to this structure, a ceramic circuit board in which the generation of voids in the joint interface can be effectively suppressed, the joint strength of the metal member serving as the circuit layer can be increased, and the heat resistance cycle characteristics can be drastically improved, and a method for producing the same can be provided.

Abstract: The present invention discloses an anodically bonded vacuum cell structure with a glass substrate including a cavity, and a substrate deposited on the glass substrate, thereby enclosing the cavity to form a bonding interface. The bonding interface having silicon such that the substrate includes a layer of silicon or a secondary substrate with silicon layer bonded onto the secondary substrate.