Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

Abstract: A semiconductor device includes a semiconductor substrate and at least one integrated circuit formed on a frontside of the semiconductor substrate. A shielding layer is formed on a backside of the semiconductor substrate. The shielding layer includes one or more elements having a high thermal neutron absorption cross section.

Abstract: An energy distribution of soft error-inducing radiation likely to be encountered by an electronic circuit during operation is determined. A tuned radiation source having a source energy distribution similar to the determined energy distribution is prepared. The electronic circuit is tested using the tuned radiation source.

Abstract: An embedded-electronic-device package includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer, a shielding-metal layer and conductive vias. The core layer includes a first surface, a second surface opposite to the second surface and a cavity penetrating the core layer. The electronic device is disposed in the cavity including an inner surface. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers part of the electronic device. The second dielectric layer disposed on the second surface is filled in rest of the cavity, covers rest of the electronic device. The first and second dielectric layers cover the electronic device. The shielding-metal layer covers the inner surface. The conductive vias are respectively disposed in the first and second dielectric layers and extended respectively from outer surfaces of the first and second dielectric layers to the shielding-metal layer.

Abstract: A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Abstract: A semiconductor device includes a semiconductor substrate and at least one integrated circuit formed on a frontside of the semiconductor substrate. A shielding layer is formed on a backside of the semiconductor substrate. The shielding layer includes one or more elements having a high thermal neutron absorption cross section.

Abstract: A semiconductor chip package includes a substrate unit, a chip, metal members, a molding compound and a shielding layer. The chip is assembled on and electrically connected with the substrate unit. The substrate unit includes conductive seat portions surrounding the chip, and defines through holes respectively coated by conducting films to ground the corresponding seat portions. The metal members are assembled on the seat portions, surround the chip, and are grounded through the conducting films. The molding compound encapsulates the chip and the metal members, with part of each metal member exposed out of the molding compound. The shielding layer covers the molding compound and the parts of each metal member exposed out of the molding compound to shield the chip from electromagnetic radiation.

Abstract: A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Abstract: An energy distribution of soft error-inducing radiation likely to be encountered by an electronic circuit during operation is determined. A tuned radiation source having a source energy distribution similar to the determined energy distribution is prepared. The electronic circuit is tested using the tuned radiation source.

Abstract: A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.

Abstract: A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.

Abstract: A method for detecting soft errors in an integrated circuit (IC) due to transient-particle emission, the IC comprising at least one chip and a substrate includes mixing an epoxy with a radioactive source to form a hot underfill (HUF); underfilling the chip with the HUF; sealing the underfilled chip; measuring a radioactivity of the HUF at an edge of the chip; measuring the radioactivity of the HUF on a test coupon; testing the IC for soft errors by determining a current radioactivity of the HUF at the time of testing based on the measured radioactivity; and after the expiration of a radioactive decay period of the radioactive source, using the IC in a computing device by a user.

Abstract: An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. A UBM layer is disposed between the solder bump and the semiconductor portion and includes the UBM pad and a UBM field. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion. The UBM field is separated from each UBM pad by a gap extending from the UBM pad to the UBM field so as to electrically isolate the UBM field from the UBM pad.

Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.

Abstract: A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Abstract: A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip.

Abstract: A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.

Abstract: A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

Abstract: An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel dielectric layer furthest from the substrate, each interlevel dielectric layer of the set of interlevel dielectric layers including electrically conductive wires, top surfaces of the wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive terminal pad contacting a wire pad of the uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of the terminal pad; and a copper block on the plating base layer.

Abstract: An electronic package-on-package system with integrated shielding. The package-on-package system includes a first package having a first die and a second package having a second die and a substrate. The system also includes a conductive shield having a first portion and a second portion. The first portion is disposed between the first die and the second die and the second portion is disposed between the substrate and the first portion. The first portion is coupled to the second portion for shielding the first die from the second die.

Abstract: Aimed at reducing the area of a protective circuit in a semiconductor device provided therewith, a semiconductor device of the present invention has a first-conductivity-type well, a plurality of first diffusion layers formed in the well, a plurality of second diffusion layers formed in the well, and a diffusion resistance layer formed in the well, wherein the first diffusion layers have a second conductivity type, and are connected in parallel with each other to an input/output terminal of the semiconductor device; the second diffusion layers are arranged alternately with a plurality of first diffusion layers, and are connected to a power source or to the ground; the diffusion resistance layer has a second conductivity type, and is located in adjacent to any of the plurality of second diffusion layers; the diffusion resistance layer is connected to the input/output terminal of the semiconductor device, while being arranged in parallel with the first diffusion layers, and connects the internal circuit and the

Abstract: A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.

Abstract: An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion.

Abstract: Systems and methods are disclosed herein for determining the placement of a standard cell, representing a semiconductor component in a design stage, on an integrated circuit die. One embodiment of a method, among others, comprises analyzing regions of a semiconductor die with respect to the susceptibility of the region to be exposed to radiation. This method further comprises placing the standard cell in one of the analyzed regions of the semiconductor die, the standard cell being placed based on the sensitivity of the standard cell to radiation. The method may also comprise running an algorithm, e.g. using a component placement engine, for determining the placement of semiconductor components on an integrated circuit die.

Abstract: A method for reducing single event upsets in an integrated circuit includes the step of providing a plurality of levels within the integrated circuit, wherein the plurality of levels within the integrated circuit are in a stacked arrangement. The method also includes the step of providing a plurality of metal fill patterns within each of the plurality of levels within the integrated circuit. The method further includes the step of placing the plurality of metal fill patterns within at least one of the plurality of levels in a pattern such that a line of sight towards an active silicon layer does not exist within the stacked arrangement of the plurality of levels, thereby increasingly absorbing ionizing radiation particles, and thereby reducing single event upsets in the integrated circuit.

Abstract: A substrate for a semiconductor package includes a dielectric substrate, a circuit pattern formed on a first surface of the dielectric substrate, and an electromagnetic band gap (EGB) pattern. The EGB pattern includes multiple unit structures formed on a second surface of the dielectric substrate, where each unit structure includes a flat conductor electrically connected to the circuit pattern through a ground connection, and multiple spiral-patterned conductors electrically connected to the flat conductor. The second surface is formed on an opposite side of the dielectric substrate from the first surface. Each flat conductor is electrically connected to a flat conductor of another one of the unit structures. At least one of the spiral-patterned conductors in each one of the unit structures is electrically connected to another one of the spiral-patterned conductors.

Abstract: An ultra wideband hermetically sealed surface mount package for a microwave monolithic integrated circuit (MMIC) is provided including: an integrated circuit; a package body being mounted with the integrated circuit and comprising a plurality of first dielectrics formed in a multilayer, a first line unit mounted to a circuit substrate and is electrically connected with an external circuit, a second line unit upwardly extended from the first line unit and is electrically connected with the first line unit, a third line unit extended to the right angle from the second line unit and is electrically connected with the second line unit, and a bonding unit that electrically connects the third line unit and the mounted integrated circuit; and a package cover being formed on the package body to seal the integrated circuit and comprising a plurality of second dielectrics formed in a multilayer.

Abstract: A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip.

Abstract: An integrated circuit package system includes: a substrate; a first device attached to the substrate; a shield attached to the substrate and surrounding the first device; apertures formed within the shield; the shield configured to block electromagnetic energy that passes through the apertures; and an encapsulation material deposited through the apertures.

Abstract: A semiconductor device has a substrate comprising at least one dielectric layer and at least one metal layer on a first surface of the substrate. A die is attached to the first surface of the substrate. A mold compound is used to encapsulate the die and partially encapsulate the first surface of the substrate. The mold compound has a protrusion proximate to the at least one metal layer. A conductive material covers the mold compound, including the protrusion, and contacts the at least one metal layer.

Abstract: Embodiments of the present disclosure provide an apparatus including a semiconductor die having a plurality of integrated circuit devices, a pad structure electrically coupled to at least one integrated circuit device of the plurality of integrated circuit devices via an interconnect layer, an electrically insulative layer disposed on the interconnect layer, a first shielding structure disposed in the electrically insulative layer and electrically coupled to the pad structure, an under-ball metallization (UBM) structure electrically coupled to the first shielding structure, and a solder bump electrically coupled to the UBM structure, the solder bump comprising a solder bump material capable of emitting alpha particles, wherein the first shielding structure is positioned between the solder bump and the plurality of integrated circuit devices to shield the plurality of integrated circuit devices from the alpha particles. Other embodiments may be described and/or claimed.

Abstract: A method and system for fabricating an electromagnetic radiation shield for an electronics package is disclosed. The electronics package includes a substrate, at least one ground contact feature, and a protective layer. The electronics package is physically coupled to at least one additional electronics package through at least the substrate. The method and system include exposing a portion of the ground contact feature(s) by removing a portion of the electronics package above the ground contact feature(s). The exposing step forms at least one trench above the ground contact feature(s). The method and system also include depositing an electromagnetic radiation shield that substantially covers the electronics package, fills the trench(es), and is electrically connected to the ground contact feature(s).

Abstract: A method and device comprising an easily reworkable alpha particle barrier is provided. The easily reworkable alpha particle barrier is applied in the space between the surface of the chip and the surface of the substrate, and reduces soft error rate (SER). Further, the easily reworkable alpha particle barrier material is chosen from the group of an organic material, a hydrocarbon, more specifically a polyalphaolefin (PAO) oil, and a polymer or filled polymer; wherein the polyalphaolefin oil has a viscosity below 1000 cSt (at 100° C.). The easily reworkable alpha particle barrier material can be used with multichip modules (MCM's) allowing easy device rework of one or more dies without affecting other dies on the same substrate.

Abstract: A structure for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

Abstract: A high reliability radiation shielding integrated circuit apparatus comprising a plurality of package layers; a radiation shielding lid or base coupled to the plurality of package layers; wherein the circuit die are shielded from receiving an amount of radiation greater than the total dose of tolerance of the circuit die. In one embodiment, an integrated circuit apparatus for use in high reliability applications is disclosed. The integrated circuit apparatus is designed to be highly reliable and protect integrated circuit die from failing or becoming unreliable due to radiation, mechanical forces, thermal exposure, or chemical contaminates.

Abstract: A package structure with a plurality of chips stacked on each other includes a substrate, a first chip and second chip. The substrate has a dielectric layer, a metal layer having a conducting trace area and a shielding area formed on the dielectric layer, and a solder mask formed on the conducting trace area. The first chip and the second chip are electrically connected to the conducting trace area and arranged on the solder mask respectively. The first chip has a package body connected with one surface of the metal layer for arranging the first chip between the solder mask and the shielding area of the metal layer. The second chip has a package body connected with the other surface of the metal layer for arranging the second chip between the solder mask and the shielding area of the metal layer.

Abstract: A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

Abstract: A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Abstract: An image sensor includes a substrate with an epitaxial layer deposited thereon, a plurality of photodiodes buried in the epitaxial layer, and a plurality of field oxide films interposed between the photodiodes for insulating the photodiodes. Each of the field oxide films includes a trench formed on the epitaxial layer, a first oxide layer deposited on an inside of the trench, a reflective layer deposited on the first oxide film for reflecting incident light to a side of the photodiode, and a second oxide layer formed on the reflective layer.

Abstract: A semiconductor device includes a silicon substrate having a film thickness smaller than a maximum range of a particle generated by a nuclear reaction between a fast neutron and a silicon atom, and a semiconductor element formed on a surface of the silicon substrate.

Abstract: Microelectronic apparatus having protection against high frequency crosstalk radiation, comprising: a planar insulating substrate; an active semiconductor electronic device located over a first region of the insulating substrate; and a doped semiconductor located in a second region of the insulating substrate substantially surrounding the first region. Apparatus further comprising a dissipative conductor overlaying and adjacent to the doped semiconductor. Apparatus additionally comprising metallic test probe contacts making electrical connections with the active semiconductor electronic device. Application of the apparatus to dissipate crosstalk radiation having a center frequency within a range between about 1 gigahertz and about 1,000 gigahertz. Methods for making the apparatus.

Abstract: A radiation shielded and packaged integrated circuit semiconductor device includes a lid secured to a base to enclose an integrated circuit die within, wherein the lid and the base are each constructed from a high Z material to prevent radiation from penetrating therethrough. Another embodiment includes a die attach slug constructed from a high Z material disposed between the integrated circuit die and the base, in combination with a high Z material lid to substantially block incident radiation.