Protection Against Radiation, E.g., Light, Electromagnetic Waves (epo) Patents (Class 257/E23.114)
  • Patent number: 11532868
    Abstract: An antenna apparatus comprises a semiconductor die in a molding compound layer, a first through via is between a sidewall of the semiconductor die and a sidewall of the molding compound layer and an antenna structure over the molding compound layer, wherein a first portion of the antenna structure is directly over a top surface of the semiconductor die and a second portion of the antenna structure is directly over a top surface of the first through via.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lai Wei Chih, Monsen Liu, En-Hsiang Yeh, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 11512905
    Abstract: A heatsink comprising a heat exchange device having a plurality of heat exchange elements each having a surface boundary with respect to a heat transfer fluid, having successive elements or regions having varying size scales. According to one embodiment, an accumulation of dust or particles on a surface of the heatsink is reduced by a removal mechanism. The mechanism can be thermal pyrolysis, vibration, blowing, etc. In the case of vibration, adverse effects on the system to be cooled may be minimized by an active or passive vibration suppression system.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: November 29, 2022
    Assignee: Fractal Heatsink Technologies LLC
    Inventor: Alexander Poltorak
  • Patent number: 11508646
    Abstract: A semiconductor device comprises; a lead frame having leads and a die pad; a printed circuit board including an electrode for the connection of each of the leads and the die pad, a wiring pattern, and an opening exposing a part of a surface of the die pad; the semiconductor element for processing a high frequency signal, mounted on a surface of a metal block bonded to the surface of the die pad exposed through the opening, and connected to the wiring pattern with a metal wire; electronic components connected to the wiring pattern and mounted on a surface of the printed circuit board; and a sealing resin to seal the printed circuit board, the semiconductor element, the electronic components, and the metal wire so as to expose rear surfaces of the leads and the die pad.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 22, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Miyawaki
  • Patent number: 11495513
    Abstract: A component carrier with a stack that has at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a semiconductor component embedded in the stack, and a highly-conductive block embedded in the stack and being thermally and/or electrically coupled with the semiconductor component is illustrated and described.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: November 8, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Johannes Stahr, Andreas Zluc, Mike Morianz, Heinz Moitzi
  • Patent number: 11490526
    Abstract: A method of forming a structure upon a substrate is disclosed. The method comprises: providing a substrate upon a surface of which a plurality of electrically conductive pads are disposed; depositing fluid containing a dispersion of electrically polarizable nanoparticles onto the substrate such that at least a portion of a first one of the plurality of pads is in contact with the fluid; applying an alternating electric field to the fluid using a first electrode and a second electrode, the first electrode being positioned so as to provide an effective first electrode end position from which the electric field is applied, coincident with the deposited fluid, and spaced apart from the first pad by a distance, and the second electrode being in contact with the first pad, such that a plurality of the nanoparticles are assembled to form a first elongate structure extending along at least part of the distance between the effective first electrode end position and the portion of the first pad.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: November 1, 2022
    Assignee: XTPL S.A.
    Inventors: Piotr Kowalczewski, Aneta Wiatrowska, Michal Dusza, Filip Granek
  • Patent number: 11474168
    Abstract: A magnetic sensor device having a spin-valve-type magnetoresistive effect element and capable of stably applying a bias magnetic field on the free layer of the magnetoresistive effect element includes a spin-valve-type magnetoresistive effect element, a substrate on which the magnetoresistive effect element is positioned, a power source that supplies a substantially constant electric current applied on the magnetoresistive effect element, and a magnetic field generator that is connected to the electric current path of the electric current applied on the magnetoresistive effect element in series. The magnetic field generator is provided to be capable of applying a bias magnetic field on at least a portion of the magnetoresistive effect element. The magnetic field generator is close to a portion of the magnetoresistive effect element and is positioned at a different level from the substrate.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: October 18, 2022
    Assignee: TDK Corporation
    Inventors: Naoki Ohta, Yongfu Cai
  • Patent number: 11476565
    Abstract: A patch antenna includes a flat-plate radiating element; and a metal wall provided outside a peripheral edge of the radiating element, such that a wall surface of the metal wall intersects a line connecting a center of the radiating element and a feeding point. An antenna device for a vehicle includes: the patch antenna; a housing installed in a predetermined orientation at a predetermined position of the vehicle; and a support supporting the patch antenna such that the patch antenna is used for vertically polarized waves when the housing is installed in the predetermined orientation at the predetermined position.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 18, 2022
    Assignee: YOKOWO CO., LTD.
    Inventor: Takeshi Sampo
  • Patent number: 11462485
    Abstract: The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: October 4, 2022
    Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITED
    Inventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Ying-Chuan Li, Ping-Hua Chu
  • Patent number: 11456340
    Abstract: Disclosed are an electroluminescent display panel and a brightness compensation method therefor. The electroluminescent display panel is provided with photoelectric detectors corresponding to at least a portion of light-emitting structures. The photoelectric detector is used to convert, under control of a sample control line, light emitted when the corresponding light-emitting structure is turned on into an electric signal, and to output the same to a detection output line. The display panel employs a photoelectric detector to detect a change in display brightness of a corresponding light-emitting structure, such that voltage compensation can be performed on the light-emitting structure according to the detected brightness change, thereby ensuring good display performance of the entire display panel.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 27, 2022
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventor: Guoqiang Tang
  • Patent number: 11445612
    Abstract: A component carrier including: i) a layer stack with at least one electrically insulating layer structure and at least one electrically conductive layer structure, ii) a cavity formed in the layer stack, iii) a dielectric element at least partially placed in the cavity, wherein the dielectric element and the layer stack are electromagnetically couple-able, and iv) an electrically insulating connection material between the dielectric element and the layer stack.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: September 13, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Patrick Lenhardt, Sebastian Wolfgang Sattler
  • Patent number: 11394319
    Abstract: An apparatus and a method of fabricating an apparatus for piercing an object, the apparatus comprises: a substrate; one or more needles; one or more anchors and one or more piezoelectric actuators. The method comprises the steps of deposit sacrificial layer over the substrate; deposit conducting layer over the sacrificial layer; deposit piezoelectric layer over the conducting layer; etch a geometry of the one or more piezoelectric actuators using a first mask created by lithography process; deposit the one or more needle and one or more anchors using a second mask created by lithography process and a lift-off process; etch the sacrificial layer under the needle and the one or more piezoelectric actuators, wherein the anchors are configured to connect the substrate to the piezoelectric actuators and the one or more piezoelectric actuators are configured to expand, contract or bend, and form holding arms that are configured to move the one or more needles.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: July 19, 2022
    Inventor: David Hirshberg
  • Patent number: 11348894
    Abstract: Provided is a high-frequency module capable of enhancing its shielding performance by reducing a placement interval of bonding wires at a desired position using a plurality of bonding wires different in arc height when a shield member is formed using the bonding wires. A high-frequency module includes a multilayer wiring board, components mounted on an upper surface of the multilayer wiring board, a shield member disposed along the component, a sealing resin layer, and a shield film. The shield member is formed of a plurality of bonding wires different in arc height. When the bonding wires are disposed by allowing a bonding wire having a high arc height to sequentially straddle a bonding wire having a low arc height in a nested manner, a placement interval of the bonding wires at a desired position can be reduced and shielding performance can be enhanced.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: May 31, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Motohiko Kusunoki
  • Patent number: 11328953
    Abstract: The present disclosure relates to a wiring circuit, and a method for producing the wiring circuit, that includes graphite wiring having a specified thickness, a high electrical conductivity, and a high carrier mobility. The wiring circuit may include graphite wiring comprised of graphite where the graphite wiring has a thickness of 3 nm or more and less than 300 nm. The graphite may have an electrical conductivity along a graphite film plane direction of 18000 S/cm or more, and the graphite may have a carrier mobility along the graphite film plane direction of 9500 cm2/Vsec or more. The method for producing a wiring circuit may include steps of: (1) bonding a graphite film with a substrate; (2) plasma etching the graphite film to form a graphite thin film; and (3) etching the graphite thin film to form a wiring circuit.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 10, 2022
    Assignee: KANEKA CORPORATION
    Inventors: Mutsuaki Murakami, Yuki Kawashima
  • Patent number: 11324112
    Abstract: An antenna device comprises: a printed circuit board formed with both sides in a plate shape including a first surface and a second surface and including at least one conductive layer between the first surface and the second surface; an array of conductive plates formed parallel to the first surface on or in the printed circuit board; a wireless communication circuit electrically connected to the array of conductive plates, coupled to the first surface, and capable of transmitting or receiving frequencies between 3 GHz and 300 GHz; and a conductive shielding structure mounted on the first surface of the printed circuit board and electrically connected to the at least one conductive layer when covering the wireless communication circuit, wherein the conductive shielding structure may include: a third surface facing the first surface when seen from the top of the first surface; and an electromagnetic bandgap (EBG) structure formed on the third surface.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: May 3, 2022
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Junho Lee, Antonio Ciccomancini Scogna
  • Patent number: 11302617
    Abstract: An electronic package comprising a first substrate that includes a first plurality of substrate vias and one or more cavities, a second substrate that includes a second plurality of substrate vias and one or more cavities, and a standoff substrate(s). The standoff substrate(s)positioned between the first and second substrate, the standoff substrate(s) is affixed to each of the first and second substrate, standoff substrate(s) forms a clearance between the first and second substrate, the standoff substrate(s) comprises an intervening plurality of substrate vias passing through the entire thickness of the standoff substrate(s), and a portion of the second plurality of substrate vias are configured to be or capable of being electrically connected to a portion of the first plurality of substrate vias by way of a portion of the intervening plurality of substrate vias.
    Type: Grant
    Filed: December 22, 2019
    Date of Patent: April 12, 2022
    Assignee: BroadPak Corporation
    Inventor: Farhang Yazdani
  • Patent number: 11222852
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing an electronic component on a lower side of a first carrier and forming an encapsulant on an upper side of the first carrier. A first conductor is disposed on the encapsulant and configured for generating radiation energy by an alternating voltage, an alternating current or radiation variation. As such, the electronic package has a reduced thickness and improved antenna efficiency.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: January 11, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Chia-Yang Chen
  • Patent number: 11219143
    Abstract: The present disclosure provides a control unit of display device and a display device. The control unit of display device includes: a back plate a plurality of circuit structures, the plurality of circuit structures being arranged on the back plate; a plurality of electric field shielding structures, each of the electric field shielding structures being arranged between the circuit structures and configured to shield an electric field between the circuit structures, wherein each of the electric field shielding structures includes a plurality of shielding strips, the plurality of shielding strips are spaced apart from each other and projections of the shielding strips on a corresponding side of the circuit structure are continuous and uninterrupted.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 4, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yongda Ma, Pan Li, Yong Qiao
  • Patent number: 11160163
    Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 26, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Snehamay Sinha, Tapobrata Bandyopadhyay, Makarand Ramkrishna Kulkarni
  • Patent number: 10999956
    Abstract: A module includes a wiring substrate; a component; a metal pin attached to a land electrode formed at one main surface and has a first extending portion extends from the one main surface, a second extending portion that is bent and extends from one end of the first extending portion on an opposite side from the one end surface, and a third extending portion that is bent and extends from one end of the second extending portion on an opposite side from the first extending portion to approach the one main surface; a sealing resin layer that covers the one main surface, the component, and the metal pin; and a shield layer that covers a side surface of the wiring substrate, a surface of the sealing resin layer, and the upper surface and the side outer surface of the metal pin.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 4, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yoshihito Otsubo
  • Patent number: 10957612
    Abstract: A power semiconductor module arrangement includes a substrate including a dielectric insulation layer, a first metallization layer arranged on a first side of the dielectric insulation layer, and a second metallization layer arranged on a second side of the dielectric insulation layer, the dielectric insulation layer being disposed between the first and second metallization layers. The arrangement further includes at least one first connection element mounted on the substrate, a housing having sidewalls, and at least one second connection element. Each second connection element includes a first part extending vertically through a sidewall of the housing, a second part coupled to a first end of the first part and protruding from the sidewall in a vertical direction, and a third part coupled to a second end of the first part opposite the first end. Each third part is detachably coupled to one of the at least one first connection element.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Regina Nottelmann, Mark Schnietz
  • Patent number: 10903560
    Abstract: A module unit includes a carrier substrate, an antenna substrate as well as sealants. The carrier substrate includes a chip arranged on a first main surface as well as a spacer arranged on the first main surface. The antenna substrate includes at least one antenna structure. The sealants hermetically seal off the antenna substrate and the carrier substrate in an edge area and connect same to each other. The antenna substrate is connected to the carrier substrate via the spacer, so that a cavity is formed between the chip and the antenna substrate.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 26, 2021
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Thomas Loeher, Ivan Ndip, Klaus-Dieter Lang
  • Patent number: 10651583
    Abstract: A socket assembly includes a socket connector including a socket substrate having an upper surface and a lower surface, upper socket contacts on the upper surface configured to be terminated to an electronic package and lower socket contacts configured to be terminated to a host circuit board. The socket connector includes first and second power contacts. The first power contact is configured to be terminated to the electronic package. The socket assembly includes a power connector terminated to the socket substrate having a power connector terminal electrically connected to the second power contact. The socket substrate is configured to electrically connect the power connector to the electronic package through the first power contact and the second power contact.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: May 12, 2020
    Assignee: TE CONNECTIVITY CORPORATION
    Inventors: Jeffery Walter Mason, Michael David Herring, Christopher William Blackburn
  • Patent number: 10607976
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
  • Patent number: 10601254
    Abstract: An electromagnetic-coupling module including a radio IC chip and a feeder circuit board on which the radio IC chip is mounted and a feeder circuit including a resonant circuit having a predetermined resonant frequency is attached to an article. The article has a radiation element that radiates a transmission signal supplied from the feeder circuit of the electromagnetic-coupling module via electromagnetic coupling and that supplies a received reception signal to the feeder circuit via the electromagnetic coupling.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: March 24, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Noboru Kato, Ikuhei Kimura, Kimikazu Iwasaki, Satoshi Ishino
  • Patent number: 10446530
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
  • Patent number: 10347616
    Abstract: A chip package includes a sensing chip, a computing chip, and a protective layer annularly surrounding the sensing chip and the computing chip. The sensing chip has a first conductive pad, a sensing element, a first surface and a second surface opposite to each other. And the sensing element is disposed on the first surface. The computing chip has a second conductive pad and a computing element. The protective layer is formed by lamination and at least exposes the sensing element. The chip package further includes a conductive layer underneath the second surface of the sensing chip and extending to be in contact with the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 9, 2019
    Assignee: XINTEC INC.
    Inventors: Hsin Kuan, Chin-Ching Huang, Chia-Ming Cheng
  • Patent number: 10338131
    Abstract: A system has a chip mounting board and a docking board. The chip mounting board can be loaded with test samples in a low voltage environment and can then be transported to a high voltage environment. The chip mounting board can be connected to the docking board and allows high voltage testing of multiple samples in parallel. The chip mounting board can then be disconnected from the docking board and transported back to a low voltage environment to unload the tested samples.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joseph Milton Yehle, Xu Gao, L Reneā€² Graves
  • Patent number: 10304623
    Abstract: Some features pertain to a package substrate that includes at least one dielectric layer, an inductor in the at least one dielectric layer, a first terminal coupled to the inductor, a second terminal coupled to the inductor, and a third terminal coupled to the inductor. The first terminal is configured to be a first port for the inductor. The second terminal is configured to be a second port for the inductor. The third terminal is a dummy terminal. In some implementations, the package substrate includes a solder resist layer over the dielectric layer, where the solder resist layer covers the third terminal. In some implementations, the package substrate includes a solder interconnect over the third terminal, such that the solder resist layer is between the third terminal and the solder interconnect. In some implementations, the package substrate is coupled to a die comprising a plurality of switches.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: May 28, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Young Kyu Song, John Jong Hoon Lee, Sangjo Choi
  • Patent number: 10201096
    Abstract: An electrical connector used for connecting an chip module to a printed circuit board includes an insulating housing, a number of terminals and a cover. The insulating housing includes a body portion. The terminals are insert molded in the body portion. The body portion includes an upper face and a lower face. Each of the terminals includes a first soldering portion extending upwardly beyond the upper face and a second soldering portion extending downwardly beyond the lower face. The cover covers the insulating housing. The electrical connector has a simple structure and a simple manufacturing process.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: February 5, 2019
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventor: Shuo-Hsiu Hsu
  • Patent number: 10199333
    Abstract: A delamination-resistant semiconductor device includes a conductive layer, a semiconductor layer, and a spacer. The conductive layer has a first side opposite a second side. The semiconductor layer is on the first side and defines an aperture therethrough spanned by the conductive layer. The spacer is on the second side and has a top surface, proximate the conductive layer, that defines a blind hole spanned by the conductive layer. A method for preventing delamination of a multilayer structure, includes a step of disposing a first layer on a substrate such that the first layer spans an aperture of the substrate. The method also includes a step of disposing a second layer on the first layer. The second layer has a blind hole adjacent to the first layer such that the first layer spans the blind hole.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 5, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventors: Ying-Chih Kuo, Ying Chung
  • Patent number: 9947623
    Abstract: A semiconductor device. For example and without limitation, various aspects of the present disclosure provide a semiconductor device that comprises a semiconductor die comprising an inactive die side and an active die side opposite the inactive die side, a through hole in the semiconductor die that extends between the inactive die side and the active die side where the through hole comprises an inner wall, an insulating layer coupled to the inner wall of the through hole, a through electrode inside of the insulating layer, a dielectric layer coupled to the inactive die side, and a conductive pad coupled to the through electrode.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: April 17, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Won Chul Do, Yong Jae Ko
  • Patent number: 9887454
    Abstract: An antenna-integrated wireless module is provided which does not need a metal case, and which can realize size reduction. A shield layer is formed on an upper surface of a resin sealing layer, which is disposed on one principal surface of a substrate and which covers a wireless region and an antenna region, such that the shield layer does not cover a portion of the resin sealing layer, the portion being positioned directly above the antenna region. Hence the shield layer formed on the upper surface of the resin sealing layer on the side covering the wireless region can serve to suppress electromagnetic waves radiated from a wireless functional section, which is disposed in a region overlapping the wireless region when looking at the module in a plan view, and which includes an RF circuit disposed at least on the one principal surface of the substrate or inside the substrate.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: February 6, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yuichi Ito, Taro Hirai, Katsuhiko Fujikawa
  • Patent number: 9848500
    Abstract: The present invention relates to the field of integrating electronic systems that operate at mm-wave and THz frequencies. A monolithic multichip package, a carrier structure for such a package as well as manufacturing methods for manufacturing such a package and such a carrier structure are proposed to obtain a package that fully shields different functions of the mm-wave/THz system. The package is poured into place by polymerizing photo sensitive monomers. It gradually grows around and above the MMICs (Monolithically Microwave Integrated Circuit) making connection to the MMICs but recessing the high frequency areas of the chip. The proposed approach leads to functional blocks that are electromagnetically completely shielded. These units can be combined and cascaded according to system needs.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: December 19, 2017
    Assignee: SONY CORPORATION
    Inventors: Thomas Merkle, Stefan Koch, Joo-Young Choi
  • Patent number: 9743465
    Abstract: A microwave module lid is disclosed. The microwave module lid can include an inner side operable to define, at least in part, a cavity configured to have a radio frequency (RF) emitting component disposed therein. The microwave module lid can also include two or more dielectric layers proximate one another. Each layer can have a thickness, a dielectric constant, and a dielectric loss characteristic. In addition, the microwave module lid can include a metal backing layer proximate one of the dielectric layers to contain RF energy within the lid. The thicknesses, the dielectric constants, and/or the dielectric loss characteristics of the dielectric layers can be configured to minimize RF resonance in the cavity.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: August 22, 2017
    Assignee: Raytheon Company
    Inventor: James Mcspadden
  • Patent number: 9705202
    Abstract: A millimeter-wave dielectric transmission device. The millimeter-wave dielectric transmission device includes a semiconductor chip provided on one interposer substrate and capable of millimeter-wave dielectric transmission, an antenna structure connected to the semiconductor chip, two semiconductor packages including a molded resin configured to cover the semiconductor chip and the antenna structure, and a dielectric transmission path provided between the two semiconductor packages to transmit a millimeter wave signal. The semiconductor packages are mounted such that the antenna structures thereof are arranged with the dielectric transmission path interposed therebetween.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: July 11, 2017
    Assignee: SONY CORPORATION
    Inventors: Hirofumi Kawamura, Yasuhiro Okada
  • Patent number: 9666659
    Abstract: An external storage device including an interconnect substrate having a contact type external terminal, at least one semiconductor chip disposed over a first surface of the interconnect substrate, and a sealing resin layer which seals the at least one semiconductor chip and does not cover the external terminal. The at least one semiconductor chip includes a storage device, an inductor being connected to the storage device, a driver circuit configured to control the inductor and an interconnect layer. The interconnect layer is formed at a first surface of the semiconductor chip and includes the inductor. The first surface of the semiconductor chip is other than facing the first surface of the interconnect substrate, and the inductor and the driver circuit are connected to each other through the interconnect layer.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 30, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Kenta Ogawa
  • Patent number: 9397032
    Abstract: A guard ring structure is provided, including a semiconductor substrate with a circuit region encircled by a first ring and a second ring. In one embodiment, the semiconductor substrate has a first dopant type, and the first and second ring respectively includes a plurality of separated first doping regions formed in a top portion of the semiconductor substrate, having a second dopant type opposite to the first conductivity type, and an interconnect element formed over the semiconductor substrate, covering the first doping regions.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: July 19, 2016
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Chiyuan Lu, Chien-Chih Lin, Cheng-Chou Hung, Yu-Hua Huang
  • Patent number: 9398694
    Abstract: The present invention relates to the field of integrating electronic systems that operate at mm-wave and THz frequencies. A monolithic multichip package, a carrier structure for such a package as well as manufacturing methods for manufacturing such a package and such a carrier structure are proposed to obtain a package that fully shields different functions of the mm-wave/THz system. The package is poured into place by polymerizing photo sensitive monomers. It gradually grows around and above the MMICs (Monolithically Microwave Integrated Circuit) making connection to the MMICs but recessing the high frequency areas of the chip. The proposed approach leads to functional blocks that are electromagnetically completely shielded. These units can be combined and cascaded according to system needs.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: July 19, 2016
    Assignee: Sony Corporation
    Inventors: Thomas Merkle, Stefan Koch, Joo-Young Choi
  • Patent number: 9392695
    Abstract: There is provided an electronic component module capable of increasing the degree of integration by mounting electronic components on both surfaces of a substrate. The electronic component module according to an exemplary embodiment of the present disclosure includes a first substrate having one surface on which at least one electronic component is mounted; and a second substrate bonded to one surface of the first substrate and including at least one component accommodating part in which the at least one electronic component is accommodated, wherein the second substrate includes a core layer, and metal wiring layers formed on both surfaces of the core layer and having a plurality of electrode pads.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: July 12, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Min Gi Cho
  • Patent number: 9362984
    Abstract: In a multi-core semiconductor device, a data bus between CPUs or the like consumes a larger amount of power. By provision of a plurality of CPUs which transmit data by a backscattering method of a wireless signal, a router circuit which mediates data transmission and reception between the CPUs or the like, and a thread control circuit which has a thread scheduling function, a semiconductor device which consumes less power and has high arithmetic performance can be provided at low cost.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: June 7, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 9324491
    Abstract: An inductor device includes a layer-laminated member with laminated base-material layers and a coil with a winding axis coincident with a direction of layer lamination, a smaller-thickness portion near one end portion thereof in the direction of layer lamination, and a greater-thickness portion with more base-material layers than that in the smaller-thickness portion. The coil is located in the greater-thickness portion. The coil is connected, at its one end positioned near one end portion of the layer-laminated member, to a conductor pattern in the smaller-thickness portion. The coil is connected, at its other end positioned near the other end portion of the layer-laminated member, to a conductor pattern in a base-material layer located near the other end portion of the layer-laminated member. The conductor patterns are located at respective different positions in the direction of layer lamination.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: April 26, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kuniaki Yosui
  • Patent number: 8987889
    Abstract: An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: March 24, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Patrick Lawrence Welch, Yifan Guo
  • Patent number: 8987871
    Abstract: A cap for a microelectromechanical system device includes a first layer of, e.g., Bismaleimide Triazine (BT) resin material in which a through-aperture is formed, laminated to a second layer of BT resin material that closes the aperture in the first layer, forming a cavity. The first and second layers are laminated with a thermosetting adhesive that is sufficiently thick to encapsulate particles that may remain from a routing operation for forming the apertures. The interior of the cavity, including exposed portions of the adhesive, and the exposed face of the first layer are coated with an electrically conductive paint. The cap is adhered to a substrate over the MEMS device using an electrically conductive adhesive, which couples the conductive paint layer to a ground plane of the substrate. The layer of conductive paint serves as a shield to prevent or reduce electromagnetic interference acting on the MEMS device.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: March 24, 2015
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Jerome Teysseyre, Glenn de los Reyes, Wee Chin Judy Lim
  • Patent number: 8987921
    Abstract: A method for producing a component with at least one micro-structured or nano-structured element includes applying at least one micro-structured or nano-structured element to a carrier. The element has at least one area configure to make contact and the element is applied to the carrier such that the at least one area adjoins the carrier. The element is enveloped in an enveloping compound and the element-enveloping compound composite is detached from the carrier. A first layer comprising electrically conductive areas is applied to the side of the element-enveloping compound composite that previously adjoined the carrier. At least one passage is introduced into the enveloping compound. A conductor layer is applied to the surface of the passage and at least to a section of the layer comprising the first electrically conductive areas to generate a through contact, which enables space-saving contacting. A component is formed from the method.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 24, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Ulrike Scholz, Ralf Reichenbach
  • Patent number: 8963285
    Abstract: A semiconductor device includes a semiconductor substrate having a first main surface in which a recess is formed. Further, the semiconductor device includes an electrical interconnect structure which is arranged at a bottom of the recess. A semiconductor chip is located in the recess. The semiconductor chip includes a plurality of chip electrodes facing the electrical interconnect structure. Further, a plurality of electrically conducting elements is arranged in the electrical interconnect structure and electrically connected to the plurality of chip electrodes.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Winfried Bakalski, Anton Steltenpohl
  • Patent number: 8952503
    Abstract: Apparatus and methods for an electronic package incorporating shielding against emissions of electromagnetic interference (EMI). According to an integrated circuit structure, a substrate is on a printed circuit board. An integrated circuit chip is on the substrate. The integrated circuit chip is electrically connected to the substrate. An electromagnetic interference (EMI) shielding unit is on the integrated circuit chip and the substrate. The EMI shielding unit comprises a lid covering the integrated circuit chip and portions of the substrate outside the integrated circuit chip. A fill material can be deposited within a cavity formed between the lid and the substrate. The fill material comprises an EMI absorbing material. A periphery of the lid comprises a side skirt, the side skirt circumscribing the integrated circuit chip and the substrate. EMI absorbing material is on the printed circuit board, and a portion of the side skirt is embedded in the EMI absorbing material.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: William L. Brodsky, Timothy W. Budell, Samuel R. Connor, Mark Curtis Hayes Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 8946749
    Abstract: A semiconductor light emitting device includes a substrate having a wiring pattern formed thereon, and a semiconductor light emitting element mounted on one main surface of the substrate and electrically connected to the wiring pattern. The substrate has, on the one main surface, a serrated structure reflecting at least part of light emitted from said semiconductor light emitting element to the substrate, to a direction perpendicular to the one main surface.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: February 3, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsuji Iguchi
  • Patent number: 8933544
    Abstract: An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: January 13, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Yin Qian, Tiejun Dai, Howard E. Rhodes, Hongli Yang
  • Patent number: 8928129
    Abstract: A semiconductor device includes a substrate, a semiconductor chip, a first molding member and a metal layer. The substrate includes a first ground pad formed therein, the first ground pad having a first exposed surface exposed at a first surface of the substrate. The semiconductor chip is formed on the first surface of the substrate. The first molding member is formed on the first surface of the substrate and covers the semiconductor chip while not covering the first exposed surface. The metal layer covers the first molding member and extends to lateral surfaces of the substrate while contacting the first exposed surface.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: In-Sang Song
  • Patent number: 8916420
    Abstract: An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: December 23, 2014
    Inventors: Baw-Ching Perng, Chun-Lung Huang