Protection Against Radiation, E.g., Light, Electromagnetic Waves (epo) Patents (Class 257/E23.114)
  • Patent number: 10957612
    Abstract: A power semiconductor module arrangement includes a substrate including a dielectric insulation layer, a first metallization layer arranged on a first side of the dielectric insulation layer, and a second metallization layer arranged on a second side of the dielectric insulation layer, the dielectric insulation layer being disposed between the first and second metallization layers. The arrangement further includes at least one first connection element mounted on the substrate, a housing having sidewalls, and at least one second connection element. Each second connection element includes a first part extending vertically through a sidewall of the housing, a second part coupled to a first end of the first part and protruding from the sidewall in a vertical direction, and a third part coupled to a second end of the first part opposite the first end. Each third part is detachably coupled to one of the at least one first connection element.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Regina Nottelmann, Mark Schnietz
  • Patent number: 10903560
    Abstract: A module unit includes a carrier substrate, an antenna substrate as well as sealants. The carrier substrate includes a chip arranged on a first main surface as well as a spacer arranged on the first main surface. The antenna substrate includes at least one antenna structure. The sealants hermetically seal off the antenna substrate and the carrier substrate in an edge area and connect same to each other. The antenna substrate is connected to the carrier substrate via the spacer, so that a cavity is formed between the chip and the antenna substrate.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 26, 2021
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Thomas Loeher, Ivan Ndip, Klaus-Dieter Lang
  • Patent number: 10651583
    Abstract: A socket assembly includes a socket connector including a socket substrate having an upper surface and a lower surface, upper socket contacts on the upper surface configured to be terminated to an electronic package and lower socket contacts configured to be terminated to a host circuit board. The socket connector includes first and second power contacts. The first power contact is configured to be terminated to the electronic package. The socket assembly includes a power connector terminated to the socket substrate having a power connector terminal electrically connected to the second power contact. The socket substrate is configured to electrically connect the power connector to the electronic package through the first power contact and the second power contact.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: May 12, 2020
    Assignee: TE CONNECTIVITY CORPORATION
    Inventors: Jeffery Walter Mason, Michael David Herring, Christopher William Blackburn
  • Patent number: 10607976
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
  • Patent number: 10601254
    Abstract: An electromagnetic-coupling module including a radio IC chip and a feeder circuit board on which the radio IC chip is mounted and a feeder circuit including a resonant circuit having a predetermined resonant frequency is attached to an article. The article has a radiation element that radiates a transmission signal supplied from the feeder circuit of the electromagnetic-coupling module via electromagnetic coupling and that supplies a received reception signal to the feeder circuit via the electromagnetic coupling.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: March 24, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Noboru Kato, Ikuhei Kimura, Kimikazu Iwasaki, Satoshi Ishino
  • Patent number: 10446530
    Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
  • Patent number: 10347616
    Abstract: A chip package includes a sensing chip, a computing chip, and a protective layer annularly surrounding the sensing chip and the computing chip. The sensing chip has a first conductive pad, a sensing element, a first surface and a second surface opposite to each other. And the sensing element is disposed on the first surface. The computing chip has a second conductive pad and a computing element. The protective layer is formed by lamination and at least exposes the sensing element. The chip package further includes a conductive layer underneath the second surface of the sensing chip and extending to be in contact with the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 9, 2019
    Assignee: XINTEC INC.
    Inventors: Hsin Kuan, Chin-Ching Huang, Chia-Ming Cheng
  • Patent number: 10338131
    Abstract: A system has a chip mounting board and a docking board. The chip mounting board can be loaded with test samples in a low voltage environment and can then be transported to a high voltage environment. The chip mounting board can be connected to the docking board and allows high voltage testing of multiple samples in parallel. The chip mounting board can then be disconnected from the docking board and transported back to a low voltage environment to unload the tested samples.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joseph Milton Yehle, Xu Gao, L Reneā€² Graves
  • Patent number: 10304623
    Abstract: Some features pertain to a package substrate that includes at least one dielectric layer, an inductor in the at least one dielectric layer, a first terminal coupled to the inductor, a second terminal coupled to the inductor, and a third terminal coupled to the inductor. The first terminal is configured to be a first port for the inductor. The second terminal is configured to be a second port for the inductor. The third terminal is a dummy terminal. In some implementations, the package substrate includes a solder resist layer over the dielectric layer, where the solder resist layer covers the third terminal. In some implementations, the package substrate includes a solder interconnect over the third terminal, such that the solder resist layer is between the third terminal and the solder interconnect. In some implementations, the package substrate is coupled to a die comprising a plurality of switches.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: May 28, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Young Kyu Song, John Jong Hoon Lee, Sangjo Choi
  • Patent number: 10201096
    Abstract: An electrical connector used for connecting an chip module to a printed circuit board includes an insulating housing, a number of terminals and a cover. The insulating housing includes a body portion. The terminals are insert molded in the body portion. The body portion includes an upper face and a lower face. Each of the terminals includes a first soldering portion extending upwardly beyond the upper face and a second soldering portion extending downwardly beyond the lower face. The cover covers the insulating housing. The electrical connector has a simple structure and a simple manufacturing process.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: February 5, 2019
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventor: Shuo-Hsiu Hsu
  • Patent number: 10199333
    Abstract: A delamination-resistant semiconductor device includes a conductive layer, a semiconductor layer, and a spacer. The conductive layer has a first side opposite a second side. The semiconductor layer is on the first side and defines an aperture therethrough spanned by the conductive layer. The spacer is on the second side and has a top surface, proximate the conductive layer, that defines a blind hole spanned by the conductive layer. A method for preventing delamination of a multilayer structure, includes a step of disposing a first layer on a substrate such that the first layer spans an aperture of the substrate. The method also includes a step of disposing a second layer on the first layer. The second layer has a blind hole adjacent to the first layer such that the first layer spans the blind hole.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 5, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventors: Ying-Chih Kuo, Ying Chung
  • Patent number: 9947623
    Abstract: A semiconductor device. For example and without limitation, various aspects of the present disclosure provide a semiconductor device that comprises a semiconductor die comprising an inactive die side and an active die side opposite the inactive die side, a through hole in the semiconductor die that extends between the inactive die side and the active die side where the through hole comprises an inner wall, an insulating layer coupled to the inner wall of the through hole, a through electrode inside of the insulating layer, a dielectric layer coupled to the inactive die side, and a conductive pad coupled to the through electrode.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: April 17, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Won Chul Do, Yong Jae Ko
  • Patent number: 9887454
    Abstract: An antenna-integrated wireless module is provided which does not need a metal case, and which can realize size reduction. A shield layer is formed on an upper surface of a resin sealing layer, which is disposed on one principal surface of a substrate and which covers a wireless region and an antenna region, such that the shield layer does not cover a portion of the resin sealing layer, the portion being positioned directly above the antenna region. Hence the shield layer formed on the upper surface of the resin sealing layer on the side covering the wireless region can serve to suppress electromagnetic waves radiated from a wireless functional section, which is disposed in a region overlapping the wireless region when looking at the module in a plan view, and which includes an RF circuit disposed at least on the one principal surface of the substrate or inside the substrate.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: February 6, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yuichi Ito, Taro Hirai, Katsuhiko Fujikawa
  • Patent number: 9848500
    Abstract: The present invention relates to the field of integrating electronic systems that operate at mm-wave and THz frequencies. A monolithic multichip package, a carrier structure for such a package as well as manufacturing methods for manufacturing such a package and such a carrier structure are proposed to obtain a package that fully shields different functions of the mm-wave/THz system. The package is poured into place by polymerizing photo sensitive monomers. It gradually grows around and above the MMICs (Monolithically Microwave Integrated Circuit) making connection to the MMICs but recessing the high frequency areas of the chip. The proposed approach leads to functional blocks that are electromagnetically completely shielded. These units can be combined and cascaded according to system needs.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: December 19, 2017
    Assignee: SONY CORPORATION
    Inventors: Thomas Merkle, Stefan Koch, Joo-Young Choi
  • Patent number: 9743465
    Abstract: A microwave module lid is disclosed. The microwave module lid can include an inner side operable to define, at least in part, a cavity configured to have a radio frequency (RF) emitting component disposed therein. The microwave module lid can also include two or more dielectric layers proximate one another. Each layer can have a thickness, a dielectric constant, and a dielectric loss characteristic. In addition, the microwave module lid can include a metal backing layer proximate one of the dielectric layers to contain RF energy within the lid. The thicknesses, the dielectric constants, and/or the dielectric loss characteristics of the dielectric layers can be configured to minimize RF resonance in the cavity.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: August 22, 2017
    Assignee: Raytheon Company
    Inventor: James Mcspadden
  • Patent number: 9705202
    Abstract: A millimeter-wave dielectric transmission device. The millimeter-wave dielectric transmission device includes a semiconductor chip provided on one interposer substrate and capable of millimeter-wave dielectric transmission, an antenna structure connected to the semiconductor chip, two semiconductor packages including a molded resin configured to cover the semiconductor chip and the antenna structure, and a dielectric transmission path provided between the two semiconductor packages to transmit a millimeter wave signal. The semiconductor packages are mounted such that the antenna structures thereof are arranged with the dielectric transmission path interposed therebetween.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: July 11, 2017
    Assignee: SONY CORPORATION
    Inventors: Hirofumi Kawamura, Yasuhiro Okada
  • Patent number: 9666659
    Abstract: An external storage device including an interconnect substrate having a contact type external terminal, at least one semiconductor chip disposed over a first surface of the interconnect substrate, and a sealing resin layer which seals the at least one semiconductor chip and does not cover the external terminal. The at least one semiconductor chip includes a storage device, an inductor being connected to the storage device, a driver circuit configured to control the inductor and an interconnect layer. The interconnect layer is formed at a first surface of the semiconductor chip and includes the inductor. The first surface of the semiconductor chip is other than facing the first surface of the interconnect substrate, and the inductor and the driver circuit are connected to each other through the interconnect layer.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 30, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Kenta Ogawa
  • Patent number: 9397032
    Abstract: A guard ring structure is provided, including a semiconductor substrate with a circuit region encircled by a first ring and a second ring. In one embodiment, the semiconductor substrate has a first dopant type, and the first and second ring respectively includes a plurality of separated first doping regions formed in a top portion of the semiconductor substrate, having a second dopant type opposite to the first conductivity type, and an interconnect element formed over the semiconductor substrate, covering the first doping regions.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: July 19, 2016
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Chiyuan Lu, Chien-Chih Lin, Cheng-Chou Hung, Yu-Hua Huang
  • Patent number: 9398694
    Abstract: The present invention relates to the field of integrating electronic systems that operate at mm-wave and THz frequencies. A monolithic multichip package, a carrier structure for such a package as well as manufacturing methods for manufacturing such a package and such a carrier structure are proposed to obtain a package that fully shields different functions of the mm-wave/THz system. The package is poured into place by polymerizing photo sensitive monomers. It gradually grows around and above the MMICs (Monolithically Microwave Integrated Circuit) making connection to the MMICs but recessing the high frequency areas of the chip. The proposed approach leads to functional blocks that are electromagnetically completely shielded. These units can be combined and cascaded according to system needs.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: July 19, 2016
    Assignee: Sony Corporation
    Inventors: Thomas Merkle, Stefan Koch, Joo-Young Choi
  • Patent number: 9392695
    Abstract: There is provided an electronic component module capable of increasing the degree of integration by mounting electronic components on both surfaces of a substrate. The electronic component module according to an exemplary embodiment of the present disclosure includes a first substrate having one surface on which at least one electronic component is mounted; and a second substrate bonded to one surface of the first substrate and including at least one component accommodating part in which the at least one electronic component is accommodated, wherein the second substrate includes a core layer, and metal wiring layers formed on both surfaces of the core layer and having a plurality of electrode pads.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: July 12, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Min Gi Cho
  • Patent number: 9362984
    Abstract: In a multi-core semiconductor device, a data bus between CPUs or the like consumes a larger amount of power. By provision of a plurality of CPUs which transmit data by a backscattering method of a wireless signal, a router circuit which mediates data transmission and reception between the CPUs or the like, and a thread control circuit which has a thread scheduling function, a semiconductor device which consumes less power and has high arithmetic performance can be provided at low cost.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: June 7, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 9324491
    Abstract: An inductor device includes a layer-laminated member with laminated base-material layers and a coil with a winding axis coincident with a direction of layer lamination, a smaller-thickness portion near one end portion thereof in the direction of layer lamination, and a greater-thickness portion with more base-material layers than that in the smaller-thickness portion. The coil is located in the greater-thickness portion. The coil is connected, at its one end positioned near one end portion of the layer-laminated member, to a conductor pattern in the smaller-thickness portion. The coil is connected, at its other end positioned near the other end portion of the layer-laminated member, to a conductor pattern in a base-material layer located near the other end portion of the layer-laminated member. The conductor patterns are located at respective different positions in the direction of layer lamination.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: April 26, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kuniaki Yosui
  • Patent number: 8987871
    Abstract: A cap for a microelectromechanical system device includes a first layer of, e.g., Bismaleimide Triazine (BT) resin material in which a through-aperture is formed, laminated to a second layer of BT resin material that closes the aperture in the first layer, forming a cavity. The first and second layers are laminated with a thermosetting adhesive that is sufficiently thick to encapsulate particles that may remain from a routing operation for forming the apertures. The interior of the cavity, including exposed portions of the adhesive, and the exposed face of the first layer are coated with an electrically conductive paint. The cap is adhered to a substrate over the MEMS device using an electrically conductive adhesive, which couples the conductive paint layer to a ground plane of the substrate. The layer of conductive paint serves as a shield to prevent or reduce electromagnetic interference acting on the MEMS device.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: March 24, 2015
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Jerome Teysseyre, Glenn de los Reyes, Wee Chin Judy Lim
  • Patent number: 8987889
    Abstract: An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: March 24, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Patrick Lawrence Welch, Yifan Guo
  • Patent number: 8987921
    Abstract: A method for producing a component with at least one micro-structured or nano-structured element includes applying at least one micro-structured or nano-structured element to a carrier. The element has at least one area configure to make contact and the element is applied to the carrier such that the at least one area adjoins the carrier. The element is enveloped in an enveloping compound and the element-enveloping compound composite is detached from the carrier. A first layer comprising electrically conductive areas is applied to the side of the element-enveloping compound composite that previously adjoined the carrier. At least one passage is introduced into the enveloping compound. A conductor layer is applied to the surface of the passage and at least to a section of the layer comprising the first electrically conductive areas to generate a through contact, which enables space-saving contacting. A component is formed from the method.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 24, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Ulrike Scholz, Ralf Reichenbach
  • Patent number: 8963285
    Abstract: A semiconductor device includes a semiconductor substrate having a first main surface in which a recess is formed. Further, the semiconductor device includes an electrical interconnect structure which is arranged at a bottom of the recess. A semiconductor chip is located in the recess. The semiconductor chip includes a plurality of chip electrodes facing the electrical interconnect structure. Further, a plurality of electrically conducting elements is arranged in the electrical interconnect structure and electrically connected to the plurality of chip electrodes.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Winfried Bakalski, Anton Steltenpohl
  • Patent number: 8952503
    Abstract: Apparatus and methods for an electronic package incorporating shielding against emissions of electromagnetic interference (EMI). According to an integrated circuit structure, a substrate is on a printed circuit board. An integrated circuit chip is on the substrate. The integrated circuit chip is electrically connected to the substrate. An electromagnetic interference (EMI) shielding unit is on the integrated circuit chip and the substrate. The EMI shielding unit comprises a lid covering the integrated circuit chip and portions of the substrate outside the integrated circuit chip. A fill material can be deposited within a cavity formed between the lid and the substrate. The fill material comprises an EMI absorbing material. A periphery of the lid comprises a side skirt, the side skirt circumscribing the integrated circuit chip and the substrate. EMI absorbing material is on the printed circuit board, and a portion of the side skirt is embedded in the EMI absorbing material.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: William L. Brodsky, Timothy W. Budell, Samuel R. Connor, Mark Curtis Hayes Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 8946749
    Abstract: A semiconductor light emitting device includes a substrate having a wiring pattern formed thereon, and a semiconductor light emitting element mounted on one main surface of the substrate and electrically connected to the wiring pattern. The substrate has, on the one main surface, a serrated structure reflecting at least part of light emitted from said semiconductor light emitting element to the substrate, to a direction perpendicular to the one main surface.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: February 3, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsuji Iguchi
  • Patent number: 8933544
    Abstract: An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: January 13, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Yin Qian, Tiejun Dai, Howard E. Rhodes, Hongli Yang
  • Patent number: 8928129
    Abstract: A semiconductor device includes a substrate, a semiconductor chip, a first molding member and a metal layer. The substrate includes a first ground pad formed therein, the first ground pad having a first exposed surface exposed at a first surface of the substrate. The semiconductor chip is formed on the first surface of the substrate. The first molding member is formed on the first surface of the substrate and covers the semiconductor chip while not covering the first exposed surface. The metal layer covers the first molding member and extends to lateral surfaces of the substrate while contacting the first exposed surface.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: In-Sang Song
  • Patent number: 8916420
    Abstract: An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: December 23, 2014
    Inventors: Baw-Ching Perng, Chun-Lung Huang
  • Patent number: 8906741
    Abstract: A method for making an electronic package structure is provided which comprises: providing a substrate; providing an inductor module; assembling the inductor module and the substrate so that they define a space; injecting package glue into the space defined by the inductor module and the substrate so as to form a package layer.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: December 9, 2014
    Assignee: Cyntec Co., Ltd.
    Inventors: Bau-Ru Lu, Kai-Peng Chiang, Da-Jung Chen, Tsung-Chan Wu
  • Patent number: 8901718
    Abstract: There are provided a semiconductor package and a manufacturing method thereof, capable of increasing integration by mounting electronic devices on both surfaces of a substrate. The semiconductor package includes a first substrate having mounting electrodes on both surfaces thereof; a plurality of electronic devices mounted on both surfaces of the first substrate; and a second substrate exposed in cavities and bonded to a bottom surface of the first substrate so as to accommodate the electronic devices mounted on the bottom surface of the first substrate in the cavities.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: December 2, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Min Gi Cho
  • Patent number: 8895357
    Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: November 25, 2014
    Assignee: NXP B.V.
    Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Caroline Catharina Maria Beelen-Hendrikx
  • Patent number: 8872340
    Abstract: A substrate for a semiconductor package includes: a first dielectric having a first surface and a second surface which faces away from the first surface and possesses waveform shaped portions, and formed with first holes penetrating the first and second surfaces; and circuit traces formed over the second surface of the first dielectric and having waveform shaped portions disposed over the waveform shaped portions of the second surface of the first dielectric. The waveform shaped portions of the second surface of the first dielectric and the waveform shaped portions of the circuit traces form a stress-resistant structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Hoon Kim
  • Patent number: 8872313
    Abstract: A package apparatus is for packaging a power semiconductor device that includes a substrate formed, a mold part molded on the substrate, and electrode terminals extended from the mold part to a side opposite from the substrate by a predetermined length; includes: a holding unit that has insertion slots and is to holding the power semiconductor device, the insertion slots each being an opening into which the power semiconductor device is insertable in a direction perpendicular to extending direction of the electrode, edges of the opening being formed to make contact with the mold part and the substrate; and a container box that contains the holding unit. The insertion slots are provided to the holding unit so that an interval between the insertion slots in an extending direction of the electrode terminals of the power semiconductor device inserted is greater than the extending length of the electrode terminals.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: October 28, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takayuki Ushio, Yoshihisa Oguri, Akira Goto, Jyunya Kanazawa
  • Patent number: 8860079
    Abstract: Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A permanent carrier is provided and the at least one die is attached to the permanent carrier. The first surface of the at least one die is facing the permanent carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The first surface of the cap contacts the permanent carrier and the second surface of the cap is disposed at a different plane than the second surface of the die.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: October 14, 2014
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Catherine Bee Liang Ng, Kriangsak Sae Le, Chuen Khiang Wang, Nathapong Suthiwongsunthorn
  • Patent number: 8853833
    Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
  • Patent number: 8829667
    Abstract: An electronic apparatus includes a main board, a semiconductor package, an upper conductive EMI shield member, and a lower conductive EMI shield member. The main board includes a first ground pad. The semiconductor package is spaced apart from and electrically connected to the main board. The upper conductive EMI shield member covers a top surface and a sidewall of the semiconductor package. The lower conductive EMI shield member surrounds a space between the main board and the semiconductor package, and is electrically connected to the upper conductive EMI shield member and the first ground pad.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Woo Park, Wang-Ju Lee, In-Sang Song
  • Patent number: 8803298
    Abstract: With the use of a conductive shield formed on the top or bottom side of a semiconductor integrated circuit, an electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) of the semiconductor integrated circuit due to electrostatic discharge is prevented, and sufficient communication capability is obtained. With the use of a pair of insulators which sandwiches the semiconductor integrated circuit, a highly reliable semiconductor device that is reduced in thickness and size and has resistance to an external stress can be provided. A semiconductor device can be manufactured with high yield while defects of shapes and characteristics due to an external stress or electrostatic discharge are prevented in the manufacturing process.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Shingo Eguchi
  • Patent number: 8791554
    Abstract: A semiconductor device includes a substrate comprising a stack of alternating wiring layers and insulating layers. The wiring layers include conductive wiring patterns. Primary conductive vias extend through respective ones of the insulating layers and electrically connect first ones of the wiring patterns on different ones of the wiring layers to provide electrical connections between opposing first and second surfaces of the substrate. Dummy conductive vias extend through respective ones of the insulating layers and electrically connect second ones of the wiring patterns on different ones of the wiring layers. The dummy conductive vias are arranged in the substrate around a perimeter of a region including the first ones of the wiring patterns, and the dummy conductive vias and the second ones of the wiring patterns electrically connected thereto have a same electric potential to define an electromagnetic shielding structure within the substrate.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Ok Kwak, Sang-Sub Song, Sang-Ho An, Joon-Young Oh
  • Patent number: 8779563
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: July 15, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Brandl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 8779535
    Abstract: Integrated devices and methods for packaging the same can include an external housing, an internal housing positioned within the external housing, and an external cavity formed between the external housing and the internal housing. An integrated device die can be positioned within the external cavity in fluid communication with an internal cavity formed by the internal lid. An air way can extend through the external cavity to the internal cavity, and can further extend from the internal cavity to the external cavity. The air way can provide fluid communication between the package exterior and the integrated device die, while reducing contamination of the integrated device die.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: July 15, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Thomas M. Goida, Jicheng Yang
  • Patent number: 8772088
    Abstract: In a high frequency module, electronic components are mounted on a mounting surface of a collective substrate including a plurality of unit substrates that include a via conductor electrically conducted to a ground potential in a peripheral portion thereof, and the mounting surface and the electronic components are encapsulated with an encapsulation layer. The collective substrate is cut on the encapsulation layer side, thereby forming a half-cut groove penetrating through the encapsulation layer and extending halfway along the collective substrate in a thickness direction such that the via conductor is exposed only at a bottom surface of the half-cut groove. A conductive shield layer is formed to cover the encapsulation layer and is electrically conducted to the exposed via conductor. The collective substrate is then cut into individual unit substrates each including the conductive shield layer electrically conducted to the ground potential through the via conductor.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: July 8, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takayuki Horibe
  • Patent number: 8766416
    Abstract: A semiconductor package includes a substrate having opposite first and second surfaces and a ground layer therein. Further, the second surface has at least a recessed portion for exposing portions of the ground layer. The semiconductor package further includes a semiconductor chip disposed on the first surface of the substrate; an encapsulant formed on the first surface of the substrate for encapsulating the semiconductor chip; and a metal layer covering the encapsulant and the substrate and extending to the recessed portion for electrically connecting the ground layer. As such, the space for circuit layout is increased and the circuit layout flexibility is improved.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 1, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Tsung-Hsien Hsu, Hao-Ju Fang, Hsin-Lung Chung
  • Patent number: 8748230
    Abstract: An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: June 10, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventors: Patrick L. Welch, Yifan Guo
  • Patent number: 8749032
    Abstract: An integrated circuit is disclosed having through silicon vias spaced apart one from another and conductors, each coupled to one or more of the through silicon vias, the conductors in aggregate in use forming a segmented conductive plane maintained at a same potential and forming an electromagnetic shield.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: June 10, 2014
    Assignee: SiGe Semiconductor, Inc.
    Inventors: Mark Doherty, Michael McPartlin, Chun-Wen Paul Huang
  • Patent number: 8736033
    Abstract: An embedded-electronic-device package includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer, a shielding-metal layer and conductive vias. The core layer includes a first surface, a second surface opposite to the second surface and a cavity penetrating the core layer. The electronic device is disposed in the cavity including an inner surface. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers part of the electronic device. The second dielectric layer disposed on the second surface is filled in rest of the cavity, covers rest of the electronic device. The first and second dielectric layers cover the electronic device. The shielding-metal layer covers the inner surface. The conductive vias are respectively disposed in the first and second dielectric layers and extended respectively from outer surfaces of the first and second dielectric layers to the shielding-metal layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 27, 2014
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Chen Chuo, Wei-Ming Cheng
  • Patent number: 8729679
    Abstract: Consistent with an example embodiment, there is an integrated circuit device (IC) built on a substrate of a thickness. The IC comprises an active device region of a shape, the active device region having a topside and an underside. Through silicon vias (TSVs) surround the active device region, the TSVs having a depth defined by the substrate thickness. On the underside of and having the shape of the active device region, is an insulating layer. A thin-film conductive shield is on the insulating layer, the conductive shield is in electrical contact with the TSVs.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: May 20, 2014
    Assignee: NXP, B.V.
    Inventor: Chee Keong Phua
  • Patent number: 8722502
    Abstract: A method of manufacturing a semiconductor device, includes forming a trench surrounding a first area of a semiconductor substrate, the trench having a bottom surface and two side surfaces being opposite to each other, forming a silicon film on the bottom surface and side surfaces of the trench, forming an insulation film on the silicon film in the trench, grinding a bottom surface of the semiconductor substrate to expose the insulation film formed over the bottom surface of the trench, and forming a through electrode in the first area after grinding the bottom surface of the semiconductor substrate, the through electrode penetrating the semiconductor substrate.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: May 13, 2014
    Inventor: Shiro Uchiyama