Abstract: An interconnect system includes a circuit board including a substrate having a first surface and a second surface opposite the first surface, a plurality of signal conductors and a plurality of ground conductors including respective contact pads in a mating area of the substrate for engaging corresponding contacts of an electrical connector, and a plurality of ground vias extending at least partially through the substrate between the first and second surfaces. The ground vias are coupled to corresponding ground conductors. The ground vias include lossy plugs at least partially filling the ground vias. The lossy plugs are manufactured from lossy material capable of absorbing electrical resonance propagating through the substrate.

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.

Abstract: A semiconductor device or semiconductor device package for transmitting a plurality of differential signals, the reliability of which hardly deteriorates. The semiconductor device is an area array semiconductor device in which a plurality of lands (external terminals) including a plurality of lands for transmitting a plurality of differential signals are arrayed in a matrix pattern in the back surface of a wiring substrate. Some of the lands are located in the outermost periphery of the matrix pattern. Some others of the lands are located inward of the outermost periphery of the matrix pattern and in rows next to the outermost periphery. The spacing between lands in a second region between the lands located in the rows next to the outermost periphery and the side surface of the wiring substrate is larger than in a first region in the outermost periphery.

Abstract: A multi-configuration interface device for coupling different types of GPUs (graphics processor units) to a PCB (printed circuit board). The interface device comprises a GPU interface for a connection to the GPU and a PCB interface for a connection to the PCB. The GPU interface is implemented using a customizable attachment footprint for effectuating a connection to differing GPU types while maintaining the PCB interface for the connection to the PCB. The ball array for different GPUs can be configured to respectively support them. The interface device maintains a consistent PCB interface. Thus, as GPU characteristics change and evolve, or as different GPU versions are implemented, a consistent connection can be maintained for the PCB.

Abstract: Embodiments of present invention provide methods and apparatuses for connecting and/or disconnecting nodes in a semiconductor device. Embodiments of the apparatus may include a plurality of metal layers formed above a substrate and an interconnect structure formed between first and second nodes in the plurality of metal layers. The interconnect structure includes one or more metal lines formed in each of the metal layers. The metal lines are connected by a plurality of vias. Modifying one of the metal lines in any one of the metal layers changes an electrical connection between the first and second nodes.

Abstract: An apparatus includes a crystalline substrate. A cleaving guide on the substrate is positioned over a cleave plane of the crystalline substrate and positioned in a known location with respect to a feature of an electronic device on the substrate. Cleaving of the substrate along the cleave plane changes a physical characteristic of the cleaving guide and measurement of the physical characteristic provides a parameter representative of the relative position of the cleave plane and the cleaving guide.

Abstract: A stacked structure of chips including a first chip and a second chip is provided. The first chip includes a first and a second circuit blocks, a signal path, a first and a second hardwired switches. The second chip stacks with the first chip stack and includes a third circuit block, a third and a fourth hardwired switches. If the first circuit block is defective and the second and the third circuit blocks are functional, the first hardwired switch and the third hardwired switch are set correspondingly such that a power-supply bonding pad is connected to the third power terminal and disconnected to the first power terminal, and the second hardwired switch and the fourth hardwired switch are set correspondingly such that the third signal terminal is electrically connected to the signal path to make the third circuit block replace the first circuit block and provide the first function.

Abstract: The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.

Abstract: An integrated circuit and a fuse therefore are disclosed. The integrated circuit fuses includes a plurality of terminals coupled by a fuse element, wherein the fuse element is located in a non-last metal layer and/or wherein each terminal is fully-landed on an upper surface of a wire of the fuse element. As a result, there is no explosion that causes damage to surrounding material. In addition, use of the wet etchant allows positioning of a fuse in any metal layer including any non-last metal layer, thus increasing design possibilities.

Abstract: A semiconductor device with a first (101) and a second (111) semiconductor chip assembled on an insulating flexible interposer (120). The interposer, preferably about 25 to 50 ?m thick, has conductive traces (121), a central planar rectangular area and on each side of the rectangle a wing bent at an angle from the central plane. The central area has metal studs (122, 123) on the top and the bottom surface, which match the terminals of the chips, further conductive vias of a pitch center-to-center about 50 ?m or less. The side wings have contact pads (130) with metallic connectors (131) on the bottom surface; the connectors may be solder balls, metal studs, or anisotropic conductive films. The second chip is adhesively attached to a substrate, whereby the interposer faces away from the substrate. The interposer side wings have a convex bending (150) downwardly along the second chip and a concave bending (151) over the substrate; the side wing connectors are attached to the matching substrate sites.

Abstract: A semiconductor device includes a lead frame including inner lead portion having inner leads connected to outer leads and relay inner leads not connected to the outer leads. A semiconductor element is mounted on a lower surface of the lead frame. Electrode pads of the semiconductor element are connected to the inner lead portion via metal wire. One end of the relay inner lead is connected to the electrode pad via the metal wire, and the other end is connected to the outer lead via a relay metal wire disposed to step over the inner lead.

Abstract: A semiconductor device with a first (101) and a second (111) semiconductor chip assembled on an insulating flexible interposer (120). The interposer, preferably about 25 to 50 ?m thick, has conductive traces (121), a central planar rectangular area and on each side of the rectangle a wing bent at an angle from the central plane. The central area has metal studs (122, 123) on the top and the bottom surface, which match the terminals of the chips, further conductive vias of a pitch center-to-center about 50 ?m or less. The side wings have contact pads (130) with metallic connectors (131) on the bottom surface; the connectors may be solder balls, metal studs, or anisotropic conductive films. The second chip is adhesively attached to a substrate, whereby the interposer faces away from the substrate. The interposer side wings have a convex bending (150) downwardly along the second chip and a concave bending (151) over the substrate; the side wing connectors are attached to the matching substrate sites.

Abstract: An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocks 2, 4 provide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.

Abstract: Disclosed is a multichip package or system-in package which the logic chip includes a selector circuit which, by transmitting a test mode select signal or a test mode select command to the logic chip, enables access from a logic signal pin connected to the logic chip, to a memory control signal to each of the “m” number of memory chips; and the memory control signal, when viewed from the logic chip, is connected using a one-for-one wiring scheme or a one-for-up-to-m branch wiring scheme, between the selector circuit and each of the “m” number of memory chips. This multichip package or system-in package is low in noise and high in operational reliability.

Abstract: An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Abstract: Integrated circuit packages are formed from a panel where the panel is separated by laser cutting the panel. In some embodiments, the panel is attached to the carrier for the formation of interconnect layers on the panel. Afterwards, the panel is cut with a laser while on the carrier to separate the integrated circuit packages. A tape or other type of structure may be attached to the top of the packages after the laser cutting. The integrated circuit packages are removed from the carrier by releasing the adhesive and removing the integrated circuit packages with the tape. The packages are then removed from the tape.

Abstract: A system is described that can assemble substrates over one another to form a stacked substrate. The various layers of the stacked substrate can be separated from each other by using Coulomb forces. In addition, a beam substrate can be used to increase the separation. The instructions for assembly and a FSM (Finite State Machine) can be included in the stacked substrate to pave the way for a self-constructing 3-D automaton. The beam substrate can be used to carry heat, fluids, electrical power or signals between the various layers of the stacked cells besides providing a mechanical support. A stacked substrate can be assembled into a cylindrical coil, a transformer or a coupled transformer depending on the construction of the beam structure. The magnetic coupling of the transformer can be altered by changing the distance between the separated substrates.

Abstract: A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: A first device has a surface and includes a micrometer-scale or smaller geometry doped semiconductor region extending along the surface. A second device has a surface opposite the surface of the first device and includes a micrometer-scale or smaller wire extending through the second device to a position in proximity to the surface of the second device. The first and second devices are displaceable between first and second positions relative to each other. The wire is not substantially electrically coupled to the doped semiconductor region in the first position and the wire is substantially electrically coupled to the doped semiconductor region in the second position. A potential applied to the wire affects the conductivity of the doped semiconductor region in the second position.

Abstract: Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.

Abstract: A capacitance trimming circuit of a semiconductor device may include a plurality of capacitor layers and/or a plurality of fuses. The plurality of capacitor layers may be vertically stacked. The plurality of fuses may be arranged to correspond to the plurality of capacitor layers, and/or the plurality of fuses may be configured to select corresponding ones of the plurality of capacitor layers for controlling a capacitance of the plurality of capacitor layers.

Abstract: Techniques for integrated circuit packaging in a flip chip configuration that ensures a migration path between related integrated circuits and utilizes core I/O (or area I/O) are provided. An integrated circuit, having a superset of functional circuit elements as compared to a reference integrated circuit, includes first and second sets of interconnection elements to connect to a package substrate. The first and second sets have matching arrangements, and corresponding interconnection elements of the first and second set have consistent functional assignments. The first and second sets include interconnection elements of mixed functional assignments. The first set is disposed within an area matching a size and shape of the reference integrated circuit, while the second set is disposed outside the area. In a specific embodiment, the first set includes an I/O signal and is located in the core area.

Abstract: A semiconductor device having a voltage regulator is disclosed that does not have an external output condenser for phase compensation. The semiconductor device includes a semiconductor chip that includes a voltage regulator, a power supply input terminal, a ground terminal, and an output terminal for outputting a produced constant voltage; and a phase compensation condenser that is connected between the output terminal and the ground terminal for phase compensation of the voltage regulator. The semiconductor chip and the phase compensation condenser are accommodated in a single package.

Abstract: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

Abstract: A method is described for repairing failure points, regions or locations in an electronic device to have a perfect function when a semiconductor device including an LCD of other electronic device has defects. Described is a method of transferring a single or multi-layer thin film piece into a recess with the physical properties of the thin film piece unchanged. An electronic device is described incorporating a substrate; and a plurality of thin films laminated on the substrate and part of the thin films are formed on a predetermined circuit pattern, wherein a transfer film for repairing a defect is fitted into a recess where the low layers of the thin films are exposed by removing part of a single or multi-layer thin films covering a defective portion included on the thin films and its surrounding portion.

Abstract: An integrated circuit device includes a semiconductor substrate having an interlayer insulating layer thereon and a first junction block embedded in the interlayer insulating layer. The first junction block includes a first plurality of conductive junction traces located side-by-side within the interlayer insulating layer and a corresponding first plurality of pairs of conductive vias connected to opposite ends of respective ones of the first plurality of conductive junction traces. The first junction block also includes a dummy conductive trace located adjacent the first plurality of conductive junction traces and a pair of dummy conductive vias connected to opposite ends of the dummy junction trace. The integrated circuit device further includes a plurality of upper metallization traces routed on the interlayer insulating layer.

Abstract: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

Abstract: A method is described for repairing failure points, regions or locations in an electronic device to have a perfect function when a semiconductor device including an LCD or other electronic device has defects. Described is a method of transferring a single or multi-layer thin film piece into a recess with the physical properties of the thin film piece unchanged. An electronic device is described incorporating a substrate; and a plurality of thin films laminated on the substrate and part of the thin films are formed on a predetermined circuit pattern, wherein a transfer film for repairing a defect is fitted into a recess where the low layers of the thin films are exposed by removing part of a single or multi-layer thin films covering a defective portion included on the thin films and its surrounding portion.