Arrangements For Conducting Electric Current Within Device In Operation From One Component To Another, Interconnections, E.g., Wires, Lead Frames (epo) Patents (Class 257/E23.141)

  • Patent number: 10418895
    Abstract: A power module includes: a bridge unit including a bridge circuit composed including a plurality of SiC-MOSFETs Q1 and Q2 and an internal capacitor C1 connected so as to extend over between both ends of the bridge circuit; power terminals P and N of which one ends are respectively connected to both ends of the bridge unit and other ends are respectively exposed to the outside; and a snubber circuit (RB, CB) connected so as to extend over between an exposed side of the positive-side power terminal P and an exposed side of the negative-side power terminal N. A power circuit comprising the power module, and a smoothing capacitor C2 connected in parallel to the snubber circuit. There can be provided the power module and the power circuit which can simultaneously realize the low parasitic inductance and the low noise.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 17, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Hirotaka Otake
  • Patent number: 10163786
    Abstract: A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo
  • Patent number: 9041222
    Abstract: A semiconductor device is provided, which comprises a first semiconductor package, a second semiconductor package, and a connection structure. The first semiconductor package includes a first substrate. The first substrate includes a first region and a second region. The second semiconductor package is mounted on the first semiconductor package. The connection structure electrically connects the second semiconductor package and the first semiconductor package. The connection structure comprises first connection patterns at the first region. The first connection patterns provide a data signal at the first region. The connection structure further comprises second connection patterns at the second region. The second connection patterns provide a control/address signal at the second region. A number of the second connection patterns is less than a number of the first connection patterns.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yonghoon Kim, Keung Beum Kim, Seongho Shin, Seung-Yong Cha, Inho Choi
  • Patent number: 9035445
    Abstract: A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided.
    Type: Grant
    Filed: September 23, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semicondutor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsin-Hui Lee, Wen-De Wang, Shu-Ting Tsai
  • Patent number: 9000593
    Abstract: A substrate for a semiconductor device is provided. The substrate includes a first metal line, a second metal line, a metal support part, a first insulating part, and a second insulating part. The first metal line is electrically connected to a first electrode of the semiconductor device. The second metal line is electrically connected to a second electrode of the semiconductor device and spaced apart from the first metal line. The metal support part is disposed between the first metal line and the second metal line. The first insulating part is disposed between the first metal line and the metal support part and configured to electrically insulate the first metal line from the metal support part. The second insulating part is disposed between the second metal line and the metal support part and configured to electrically insulate the second metal line from the metal support part.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: April 7, 2015
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Su Jeong Suh, Hwa Sun Park, Hyeong Chul Youn
  • Patent number: 9000558
    Abstract: A packaged integrated circuit includes an integrated circuit having a Radio Frequency (RF) passive element formed therein and a wafer level chip scale flip chip package that contains the integrated circuit. The wafer level chip scale flip chip package includes at least one dielectric layer isolating a top metal layer of the integrated circuit and a package signal connection upon the at least one dielectric layer, wherein the package signal connection partially overlays the RF passive element with respect to a surface of the integrated circuit. The RF passive element may be an inductor, a transformer, a capacitor, or another passive element. The package signal connection may be a conductive ball, a conductive bump, a conductive pad, or a conductive spring, for example. A conductive structure may reside upon the at least one dielectric layer to provide shielding to the RF passive element and may include a plurality of conductive elements or a mesh.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: April 7, 2015
    Assignee: Broadcom Corporation
    Inventors: Ali Sarfaraz, Arya Reza Behzad
  • Patent number: 8994163
    Abstract: Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventor: David S. Pratt
  • Patent number: 8987909
    Abstract: According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Nansei
  • Patent number: 8987876
    Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: March 24, 2015
    Assignee: General Electric Company
    Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
  • Patent number: 8970048
    Abstract: A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiro Inohara
  • Patent number: 8963150
    Abstract: A semiconductor device includes a circuit board including a ground portion, and a semiconductor package disposed on the circuit board. The semiconductor package includes an external connecting pad and an exposed pad. The exposed pad and the ground portion are electrically connected at a first surface of the exposed pad. A semiconductor chip is disposed on a second surface of the exposed pad and electrically connected to the external connecting pad. The first surface of the exposed pad is located external to the semiconductor package, and the second surface of the exposed pad is located within the semiconductor package. A test pad is disposed on the semiconductor chip and is electrically connected to the exposed pad.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: February 24, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong-Hyun Yeo, Yong-Bum Kim, Byung-Kil Jeon, Bong-Ju Jun
  • Patent number: 8963312
    Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: February 24, 2015
    Assignee: Xintec, Inc.
    Inventors: Yen-Shih Ho, Tsang-Yu Liu, Shu-Ming Chang, Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
  • Patent number: 8952521
    Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Walter Hartner, Ottmar Geitner, Gottfried Beer, Klaus Pressel, Mehran Pour Mousavi
  • Patent number: 8952536
    Abstract: A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of Si3N4.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: February 10, 2015
    Assignee: Spansion LLC
    Inventors: Masahiko Higashi, Hiroyuki Nansei
  • Patent number: 8952538
    Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hirohisa Matsuki
  • Patent number: 8952407
    Abstract: A light emitting device package may be provided that includes: a package body which includes a first cavity and a second cavity which are formed to be depressed in at least a portion of the package body; a first light emitting device and a second light emitting device, each of which is disposed in the first cavity and the second cavity respectively; and a first fluorescent substance and a second fluorescent substance, each of which is filled in the first cavity and the second cavity respectively.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 10, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won Jin Son
  • Patent number: 8946798
    Abstract: A backside illumination type solid-state imaging device includes stacked semiconductor chips which are formed such that two or more semiconductor chip units are bonded to each other, at least a first semiconductor chip unit is formed with a pixel array and a first multi-layered wiring layer, and a second semiconductor chip unit is formed with a logic circuit and a second multi-layered wiring layer, a connection wire which connects the first semiconductor chip unit and the second semiconductor chip unit, and a first shield wire which shields adjacent connection wires in one direction therebetween.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: February 3, 2015
    Assignee: Sony Corporation
    Inventors: Machiko Horiike, Kazuichiro Itonaga
  • Patent number: 8946869
    Abstract: An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventors: Dae-Suk Kim, Jong-Chern Lee, Chul Kim
  • Patent number: 8941250
    Abstract: A redistribution pattern is formed on active surfaces of electronic components while still in wafer form. The redistribution pattern routes bond pads of the electronic components to redistribution pattern terminals on the active surfaces of the electronic components. The bond pads are routed to the redistribution pattern terminals while still in wafer form, which is a low cost and high throughput process, i.e., very efficient process.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: January 27, 2015
    Inventors: Robert Francis Darveaux, Brett Arnold Dunlap, Ronald Patrick Huemoeller
  • Patent number: 8927416
    Abstract: A first insulating film is formed on a semiconductor substrate, an interconnect groove is formed in the first insulating film, the inside of the interconnect groove is filled with a metal film, thereby forming a first interconnect. Then, a protective film is formed on the first insulating film and the first interconnect, and the surface of the protective film is exposed to reactive gas, thereby forming a reaction layer on an interface between the first interconnect and the protective film.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: January 6, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takeshi Harada, Junichi Shibata, Akira Ueki
  • Patent number: 8928118
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 6, 2015
    Inventor: Jayna Sheats
  • Patent number: 8928138
    Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: January 6, 2015
    Assignee: Vishay-Siliconix
    Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
  • Patent number: 8922005
    Abstract: Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chang Hu, Ching-Wen Hsiao, Chih-Hua Chen, Chen-Shien Chen, Tin-Hao Kuo
  • Patent number: 8916975
    Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: December 23, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang Kun Park, Seong Hwi Song, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee, Jae Min Jang
  • Patent number: 8916910
    Abstract: Reconfigurable 3D interconnect is provided that can be used for digital and RF signals. The reconfigurable 3D interconnect can include an array of vertical interconnect vias (or TSVs) providing a signal path between a first core element of a 3D IC and a second core element of the 3D IC stacked above the first core element. A routing circuit can be used to route a signal from the first core element to the second core element through selected TSVs of the array of TSVs providing the signal path between the first core element and the second core element. The routing circuit allows re-routing of the signal through different selected TSVs during operation, which can provide real time adjustments and capacity optimization of the TSVs passing the particular signal between the elements.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: December 23, 2014
    Assignee: Research Foundation of State University of New York
    Inventors: Robert E. Geer, Wei Wang, Tong Jing
  • Patent number: 8916976
    Abstract: First semiconductor element 1 being buried in first insulating material 2; second semiconductor element 5 being covered by second insulating material 6; connection electrode 4 being buried in first insulating material 2 arranged between circuit surface of first semiconductor element 1 and circuit surface of second semiconductor element 5; external connection terminal 8 being arranged on lower surface of first insulating material 2 facing in the same direction as lower surface of first semiconductor element 1 opposite to circuit surface thereof; connection electrode 4 forming a part of path for electrically connecting circuit surface of first semiconductor element 1 and circuit surface of second semiconductor element 5 to each other; first semiconductor element 1 and external connection terminal 8 being electrically connected to each other by way of wire 3 and via 7 passing through region of insulating layer other than region thereof burying connection electrode 4.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: December 23, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masamoto Tago, Yoichiro Kurita
  • Patent number: 8907487
    Abstract: An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Seung Jee Kim, Qwan Ho Chung, Jong Hyun Nam, Si Han Kim, Sang Yong Lee, Seong Cheol Shin
  • Patent number: 8901734
    Abstract: An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: December 2, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SungWon Cho, TaeWoo Kang
  • Patent number: 8901747
    Abstract: A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: December 2, 2014
    Assignee: MoSys, Inc.
    Inventors: Michael J. Miller, Mark Baumann, Richard S. Roy
  • Patent number: 8902123
    Abstract: To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: December 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Konami Izumi
  • Patent number: 8896130
    Abstract: A multi-chip stack structure and a method for fabricating the same are provided.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: November 25, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chung-Lun Liu, Jung-Pin Huang, Yi-Feng Chang, Chin-Huang Chang
  • Patent number: 8890332
    Abstract: A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: MoSys, Inc.
    Inventors: Michael J. Miller, Mark William Baumann, Richard S. Roy
  • Patent number: 8884419
    Abstract: Embodiments of the present disclosure provide a substrate, one of either a semiconductor die or an interposer disposed on the substrate, the semiconductor die or the interposer having a first surface attached to the substrate and a second surface that is opposite to the first surface, one or more interconnect structures formed on the second surface of the semiconductor die or the interposer, a mold compound formed to substantially encapsulate the semiconductor die or the interposer, and one or more vias formed in the mold compound to facilitate coupling the one or more interconnect structures with another component. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: November 11, 2014
    Assignee: Marvell International Ltd.
    Inventors: Shiann-Ming Liou, Albert Wu
  • Patent number: 8871638
    Abstract: A method for fabricating a semiconductor device includes forming a first interlayer dielectric layer having a conductive contact, forming a sacrifice layer having a conductive interconnection over the first interlayer dielectric layer such that the conductive interconnection is contacted with the conductive contact, removing the sacrifice layer, and forming a recess by removing a part of the conductive contact exposed by the conductive interconnection.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Nam-Jae Lee
  • Patent number: 8866282
    Abstract: A slew rate of a signal transmitted between a semiconductor device having a small load capacitance and a semiconductor device having a large load capacitance is improved. When a signal is transmitted to the semiconductor device (for example, a memory device) having the large load capacitance, pre-emphasis is performed, and when a signal is transmitted to the semiconductor device (for example, a memory controller) having the small load capacitance, pre-emphasis is not performed or is slightly performed. By this, when the signal is transmitted to the memory device, blunting in signal rising due to the load capacitance is suppressed, and when the signal is transmitted to the memory controller, ringing due to the reflection of the signal is suppressed, and the slew rate of the data transmission is improved.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: October 21, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Ikeda, Yutaka Uematsu, Satoshi Muraoka
  • Patent number: 8866292
    Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A first chip is disposed in the substrate. The first chip includes a plurality of contact pads at the first major surface. A via bar is disposed in the substrate. An antenna structure is disposed within the via bar.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Maciej Wojnowski, Mehran Pour Mousavi
  • Patent number: 8860224
    Abstract: A device includes a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the second thickness to the first thickness is less than about 0.33.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wen Chen, Chuang-Han Hsieh, Kun-Yu Lin, Kuan-Chi Tsai
  • Patent number: 8860226
    Abstract: A semiconductor device includes a storage node contact plug, a bit line in communication with to the storage node contact plug, and an expansion unit formed on a sidewall of the bit line. Thermal expansion of the expansion unit serves to increase capacitance by ensuring a distance between the bit line and the storage node contact plug, thereby improving a sensing margin. A cell characteristic such as a record recovery time (tWR) may be enhanced.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong Won Seo
  • Patent number: 8860095
    Abstract: An electronic circuit, includes a plurality of electronic devices configured as interconnected to provide one or more circuit functions and at least one interconnect structure that includes a first patterned conductor connected to a terminal of a first electronic device in the electronic circuit. A second patterned conductor is connected to a terminal of a second electronic device in the electronic circuit. A first electrode is connected to a portion of the first patterned conductor, and a second electrode is connected to a portion of the second patterned conductor. A metal oxide region is formed between the first electrode and the second electrode. The metal oxide region provides a reprogrammable switch function between the first patterned conductor and the second patterned conductor by providing a conductivity that is selectively controlled by a direction and an amount of current that passes through the metal oxide region during a switch setting operation for the metal oxide region.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen M. Gates, Daniel C. Edelstein, Kailash Gopalakrishnan, Ramachandran Muralidhar
  • Patent number: 8860186
    Abstract: A method for forming an integrated circuit including the steps of: forming electronic components on a first surface of a substrate; forming a stack of interconnection levels on the first surface, each interconnection level including conductive tracks separated by an insulating material; forming at least one hole from a second surface of the substrate, opposite to the first surface, the hole stopping on one of the conductive tracks; depositing, on the walls and the bottom of the hole, a conductive layer and filling the remaining space with a filling material; and forming, in an interconnection level or at the surface of the interconnection stack, and opposite to said at least one hole, at least one region of a material having a modulus of elasticity greater than 50 GPa and an elongation at break greater than 20%, insulated from the conductive tracks.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: October 14, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Mohamed Bouchoucha, Laurent-Luc Chapelon
  • Patent number: 8860035
    Abstract: Disclosed is an organic light emitting diode display including: a substrate including a display area configured to display an image and a peripheral area surrounding the display area; a plurality of pad wires at the peripheral area of the substrate; and an inspection wire having a zigzag form on the plurality of pad wires.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: October 14, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Han-Sung Bae, Won-Kyu Kwak
  • Publication number: 20140252631
    Abstract: A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier such that the sacrificial adhesive is disposed between the contact pads and temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and sacrificial adhesive is removed to leave a via over the contact pads. An interconnect structure is formed over the encapsulant. The interconnect structure includes a conductive layer which extends into the via for electrical connection to the contact pads. The semiconductor die is offset from the interconnect structure by a height of the sacrificial adhesive.
    Type: Application
    Filed: June 4, 2010
    Publication date: September 11, 2014
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8829659
    Abstract: An integrated circuit connection comprises a substrate, first and second transmission lines, a die, and a conductive ribbon. The first transmission line has a first end and is arranged on the substrate. The die is spaced from the first end. The die has a first surface, which is arranged on the substrate, and a second surface, which is opposite to the first surface and which has the second transmission line arranged thereon. The second transmission line has a second end. The conductive ribbon electrically couples the first and the second ends.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: September 9, 2014
    Assignee: Sony Corporation
    Inventors: Xiaobing Sun, Yaqiong Zhang, Yugang Ma
  • Patent number: 8823156
    Abstract: A semiconductor device package with an interposer, which serves as an intermediate or bridge circuit of various electrical pathways in the package to electrically connect any two or more electrical contacts, such as any two or more electrical contacts of a substrate and a chip. In particular, the interposer provides electrical pathways for simplifying a circuit layout of the substrate, reducing the number of layers of the substrate, thereby reducing package height and manufacturing cost. Furthermore, the tolerance of the circuit layout can be increased or maintained, while controlling signal interference between adjacent traces and accommodating high density circuit designs. Moreover, the package is suitable for a PoP process, where a profile of top solder balls on the substrate and a package body can be varied according to particular applications, so as to expose at least a portion of each of the top solder balls and electrically connect the package to another device through the exposed, top solder balls.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: September 2, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Po-Chi Hsieh
  • Patent number: 8822281
    Abstract: A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: September 2, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Seung Uk Yoon
  • Patent number: 8796832
    Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: August 5, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
  • Patent number: 8791448
    Abstract: Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-in Kim, Jae-hee Oh, Jun-hyok Kong, Sung-ho Eun, Yong-tae Oh
  • Patent number: 8785930
    Abstract: Indexing a plurality of die obtainable from a material wafer comprising a plurality of stacked material layers. Each die is obtained in a respective position of the wafer. A manufacturing stage comprises at least two steps for treating a respective superficial portion of the material wafer that corresponds to a subset of said plurality of dies using the at least one lithographic mask through the exposition to the proper radiation in temporal succession. The method may include providing a die index on each die which is indicative of the position of the respective die by forming an external index indicative of the position of the superficial portion of the material wafer corresponding to the subset of the plurality of dies including said die and may comprise a plurality of electronic components electrically coupled to each other by means of a respective common control line.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Alfredo Brambilla, Fausto Redigolo
  • Patent number: 8786063
    Abstract: A method of manufacture of an integrated circuit packaging system includes: conductively bonding a first surface of a transposer to an inner end of a lead separate from the transposer; conductively bonding a die to the first surface of the transposer; and encapsulating the inner end with a mold compound having a bottom mold surface that is exposed and is coplanar with a surface of the transposer opposite the first surface.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: July 22, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Arnel Senosa Trasporto
  • Patent number: 8785250
    Abstract: Fabrication of a semiconductor package includes placing a conductive material on a protrusion from a leadframe to form a first assembly, forming a non-conductive mask about the protrusion, and placing a die on the first assembly, the die having an active area. Fabrication can further include reflowing the conductive material to form a second assembly such that a connection extends from the die active area, through the conductive material, to the protrusion. A semiconductor package includes a leadframe having a protrusion, a conductive material reflowed to the protrusion, and a die having an active area coupled to the protrusion by the reflowed solder.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: July 22, 2014
    Assignee: Allegro Microsystems, LLC
    Inventors: Nirmal Sharma, Virgil Ararao