Arrangements For Conducting Electric Current Within Device In Operation From One Component To Another, Interconnections, E.g., Wires, Lead Frames (epo) Patents (Class 257/E23.141)

  • Patent number: 11680317
    Abstract: The invention includes apparatus and methods for instantiating and quantum printing materials, such as elemental metals, in a nanoporous carbon powder.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: June 20, 2023
    Assignee: Quantum Elements Development Inc.
    Inventor: Christopher J. Nagel
  • Patent number: 11682580
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
  • Patent number: 11683988
    Abstract: A device includes a conductive feature, a dielectric layer, a bottom electrode via, and a liner layer. The dielectric layer is over the conductive feature. The bottom electrode via is in the dielectric layer and over the conductive feature. A topmost surface of the bottom electrode via is substantially flat. A liner layer cups an underside of the bottom electrode via. The liner layer has a topmost end substantially level with the topmost surface of the bottom electrode via.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Sheng-Chih Lai, Han-Ting Tsai, Chung-Te Lin
  • Patent number: 11678493
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an Nth metal layer in a memory region and a periphery region, the periphery region spanning a wider area than the memory region, a plurality of magnetic tunneling junctions (MTJs) over the Nth metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, a top electrode via over each of the plurality of MTJs; and an (N+M)th metal layer over the plurality of MTJs. A method for manufacturing the semiconductor structure is also disclosed.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Sheng-Huang Huang, Harry-Hak-Lay Chuang, Jiunyu Tsai, Hung Cho Wang
  • Patent number: 11670690
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first source/drain region, a second source/drain region, first source/drain contact and a first dielectric spacer liner. The gate structure is over the semiconductor substrate. The first source/drain region and the second source/drain region are in the semiconductor substrate and respectively on opposite sides of the gate structure. The first source/drain contact is over the first source/drain region. The first dielectric spacer liner lines a sidewall of the first source/drain contact and extends into the first source/drain region.
    Type: Grant
    Filed: July 11, 2020
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Cheng Hung, Kei-Wei Chen, Yu-Sheng Wang, Ming-Ching Chung, Chia-Yang Wu
  • Patent number: 11640948
    Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: May 2, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Tieh-Chiang Wu
  • Patent number: 11637069
    Abstract: A semiconductor device including: an active region; first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction and correspondingly overlap the active region; a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, and overlaps the first, second and third MD contact structures; a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and, relative to the second direction, overlaps each of the first, second and third MD contact structures; and a first via-to-MD (VD) structure between the first MD contact structure and the first conductive segment, the first VD structure electrically coupling the first conductive segment, the V2V rail and the first MD contact structure; wherein at least one of the second or third MD contact structures is electrically decoupled from the V2V rail.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang, Chih-Liang Chen
  • Patent number: 11605574
    Abstract: A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: March 14, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Mark S. Rodder, Vassilios Gerousis
  • Patent number: 11594538
    Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: February 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Ho Lee, Eun A Kim, Ki Seok Lee, Jay-Bok Choi, Keun Nam Kim, Yong Seok Ahn, Jin-Hwan Chun, Sang Yeon Han, Sung Hee Han, Seung Uk Han, Yoo Sang Hwang
  • Patent number: 11569175
    Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: January 31, 2023
    Inventors: Kyungdon Mun, Myungsam Kang, Youngchan Ko, Yieok Kwon, Jeongseok Kim, Gongje Lee, Bongju Cho
  • Patent number: 11569193
    Abstract: A semiconductor package may include a semiconductor chip on a package substrate. The semiconductor package may include a plurality of conductive connections connecting the semiconductor chip to the package substrate may be disposed, a plurality of towers which are apart from one another and each include a plurality of memory chips may be disposed, wherein a lowermost memory chip of each of the plurality of towers overlaps the semiconductor chip from a top-down view. The semiconductor package further includes a plurality of adhesive layers be attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: January 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyungu Kang, Jaekyu Sung
  • Patent number: 11562961
    Abstract: A method of manufacturing a semiconductor structure includes: forming a first opening in a first dielectric material; forming a first barrier layer in the first opening; forming a first seed material including copper and manganese on the first barrier layer, in which the manganese in the first seed material is in a range of from 0.10 at % to 0.40 at %; forming a first conductive material on the first seed material; and moving at least some of the manganese of the first seed material to a location proximate an interface between the first seed material and the first barrier layer. Another method of manufacturing a semiconductor structure and a semiconductor structure are also provided.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: January 24, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsi-Hsiang Lin
  • Patent number: 11557571
    Abstract: A stack package includes a package substrate; a lower stack including lower dies stacked on the package substrate to form a zigzag shape in a vertical direction; an upper stack including upper dies that are sequentially offset stacked in an offset direction while providing a first upper side of a down staircase shape, a first end of an uppermost upper die among the upper dies protruding, in a horizontal direction, further than a first lower side of the lower stack; and a first passive device disposed on the package substrate and spaced apart from the first lower side, and disposed between a first portion of the package substrate and the first upper side.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: January 17, 2023
    Assignee: SK hynix Inc.
    Inventors: Se Jin Park, Jang Hee Lee
  • Patent number: 11538795
    Abstract: This disclosure relates to a discrete cascode semiconductor device and associated method of manufacture, the device includes: a high voltage depletion mode device die having gate, source and drain terminals arranged on a first major surface thereof; a low voltage enhancement mode device die having a gate and a source terminal formed on a first major surface thereof, and a drain terminal formed on a second major surface opposite the first major surface. The drain terminal of the high voltage device die is mounted on a drain connection; the source terminal of the low voltage device die and the gate terminal of the high voltage device are mounted on a common source connection; and the drain terminal of the low voltage device die is mounted on the source terminal of the high voltage device.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 27, 2022
    Assignee: Nexperia B.V.
    Inventors: Ricardo Lagmay Yandoc, Manoj Balakrishnan
  • Patent number: 11532540
    Abstract: A method includes forming a buffer dielectric layer over a carrier, and forming a first dielectric layer and a first redistribution line over the buffer dielectric layer. The first redistribution line is in the first dielectric layer. The method further includes performing a planarization on the first dielectric layer to level a top surface of the first dielectric layer, forming a metal post over and electrically coupling to the first redistribution line, and encapsulating the metal post in an encapsulating material. The encapsulating material contacts a top surface of the planarized top surface of the first dielectric layer.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 11482563
    Abstract: A hybrid optical and/or electronic system includes a first planar structure having a first functionality and made of at least one first material, and a second planar structure having a second functionality and made of at least one second material different from the first material, the first and second planar structures being assembled by an assembly layer, at least one of the planar structures being disposed on a rigid substrate, the system comprising at least one active zone used for implementing the functionalities, and at least one neutral zone not used to implement the functionalities and disposed at the periphery of the active zone, the system also comprising recesses made in at least one neutral zone of the planar structure which is not disposed on the rigid substrate and is referred to as hollowed-out planar structure.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 25, 2022
    Assignees: THALES, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Luc Reverchon, Florian Le Goff
  • Patent number: 11469219
    Abstract: The present application provides a semiconductor package and a manufacturing method for the semiconductor package. The semiconductor package includes a package substrate, a first semiconductor die, a second semiconductor die, a first encapsulant and a second encapsulant. The package substrate has a first side and a second side facing away from the first side, and the second side has a concave recessed from a planar portion of the second side. The first semiconductor die is attached to the first side of the package substrate. The second semiconductor die is attached to a recessed surface of the concave. The first encapsulant covers the first side of the package substrate and encapsulates the first semiconductor die. The second encapsulant fills up the concave and encapsulates the second semiconductor die.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: October 11, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 10418895
    Abstract: A power module includes: a bridge unit including a bridge circuit composed including a plurality of SiC-MOSFETs Q1 and Q2 and an internal capacitor C1 connected so as to extend over between both ends of the bridge circuit; power terminals P and N of which one ends are respectively connected to both ends of the bridge unit and other ends are respectively exposed to the outside; and a snubber circuit (RB, CB) connected so as to extend over between an exposed side of the positive-side power terminal P and an exposed side of the negative-side power terminal N. A power circuit comprising the power module, and a smoothing capacitor C2 connected in parallel to the snubber circuit. There can be provided the power module and the power circuit which can simultaneously realize the low parasitic inductance and the low noise.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 17, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Hirotaka Otake
  • Patent number: 10163786
    Abstract: A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo
  • Patent number: 9041222
    Abstract: A semiconductor device is provided, which comprises a first semiconductor package, a second semiconductor package, and a connection structure. The first semiconductor package includes a first substrate. The first substrate includes a first region and a second region. The second semiconductor package is mounted on the first semiconductor package. The connection structure electrically connects the second semiconductor package and the first semiconductor package. The connection structure comprises first connection patterns at the first region. The first connection patterns provide a data signal at the first region. The connection structure further comprises second connection patterns at the second region. The second connection patterns provide a control/address signal at the second region. A number of the second connection patterns is less than a number of the first connection patterns.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yonghoon Kim, Keung Beum Kim, Seongho Shin, Seung-Yong Cha, Inho Choi
  • Patent number: 9035445
    Abstract: A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided.
    Type: Grant
    Filed: September 23, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semicondutor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsin-Hui Lee, Wen-De Wang, Shu-Ting Tsai
  • Patent number: 9000593
    Abstract: A substrate for a semiconductor device is provided. The substrate includes a first metal line, a second metal line, a metal support part, a first insulating part, and a second insulating part. The first metal line is electrically connected to a first electrode of the semiconductor device. The second metal line is electrically connected to a second electrode of the semiconductor device and spaced apart from the first metal line. The metal support part is disposed between the first metal line and the second metal line. The first insulating part is disposed between the first metal line and the metal support part and configured to electrically insulate the first metal line from the metal support part. The second insulating part is disposed between the second metal line and the metal support part and configured to electrically insulate the second metal line from the metal support part.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: April 7, 2015
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Su Jeong Suh, Hwa Sun Park, Hyeong Chul Youn
  • Patent number: 9000558
    Abstract: A packaged integrated circuit includes an integrated circuit having a Radio Frequency (RF) passive element formed therein and a wafer level chip scale flip chip package that contains the integrated circuit. The wafer level chip scale flip chip package includes at least one dielectric layer isolating a top metal layer of the integrated circuit and a package signal connection upon the at least one dielectric layer, wherein the package signal connection partially overlays the RF passive element with respect to a surface of the integrated circuit. The RF passive element may be an inductor, a transformer, a capacitor, or another passive element. The package signal connection may be a conductive ball, a conductive bump, a conductive pad, or a conductive spring, for example. A conductive structure may reside upon the at least one dielectric layer to provide shielding to the RF passive element and may include a plurality of conductive elements or a mesh.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: April 7, 2015
    Assignee: Broadcom Corporation
    Inventors: Ali Sarfaraz, Arya Reza Behzad
  • Patent number: 8994163
    Abstract: Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventor: David S. Pratt
  • Patent number: 8987876
    Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: March 24, 2015
    Assignee: General Electric Company
    Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
  • Patent number: 8987909
    Abstract: According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Nansei
  • Patent number: 8970048
    Abstract: A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiro Inohara
  • Patent number: 8963312
    Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: February 24, 2015
    Assignee: Xintec, Inc.
    Inventors: Yen-Shih Ho, Tsang-Yu Liu, Shu-Ming Chang, Yu-Lung Huang, Chao-Yen Lin, Wei-Luen Suen, Chien-Hui Chen
  • Patent number: 8963150
    Abstract: A semiconductor device includes a circuit board including a ground portion, and a semiconductor package disposed on the circuit board. The semiconductor package includes an external connecting pad and an exposed pad. The exposed pad and the ground portion are electrically connected at a first surface of the exposed pad. A semiconductor chip is disposed on a second surface of the exposed pad and electrically connected to the external connecting pad. The first surface of the exposed pad is located external to the semiconductor package, and the second surface of the exposed pad is located within the semiconductor package. A test pad is disposed on the semiconductor chip and is electrically connected to the exposed pad.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: February 24, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong-Hyun Yeo, Yong-Bum Kim, Byung-Kil Jeon, Bong-Ju Jun
  • Patent number: 8952407
    Abstract: A light emitting device package may be provided that includes: a package body which includes a first cavity and a second cavity which are formed to be depressed in at least a portion of the package body; a first light emitting device and a second light emitting device, each of which is disposed in the first cavity and the second cavity respectively; and a first fluorescent substance and a second fluorescent substance, each of which is filled in the first cavity and the second cavity respectively.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 10, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won Jin Son
  • Patent number: 8952536
    Abstract: A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of Si3N4.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: February 10, 2015
    Assignee: Spansion LLC
    Inventors: Masahiko Higashi, Hiroyuki Nansei
  • Patent number: 8952538
    Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hirohisa Matsuki
  • Patent number: 8952521
    Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Walter Hartner, Ottmar Geitner, Gottfried Beer, Klaus Pressel, Mehran Pour Mousavi
  • Patent number: 8946798
    Abstract: A backside illumination type solid-state imaging device includes stacked semiconductor chips which are formed such that two or more semiconductor chip units are bonded to each other, at least a first semiconductor chip unit is formed with a pixel array and a first multi-layered wiring layer, and a second semiconductor chip unit is formed with a logic circuit and a second multi-layered wiring layer, a connection wire which connects the first semiconductor chip unit and the second semiconductor chip unit, and a first shield wire which shields adjacent connection wires in one direction therebetween.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: February 3, 2015
    Assignee: Sony Corporation
    Inventors: Machiko Horiike, Kazuichiro Itonaga
  • Patent number: 8946869
    Abstract: An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventors: Dae-Suk Kim, Jong-Chern Lee, Chul Kim
  • Patent number: 8941250
    Abstract: A redistribution pattern is formed on active surfaces of electronic components while still in wafer form. The redistribution pattern routes bond pads of the electronic components to redistribution pattern terminals on the active surfaces of the electronic components. The bond pads are routed to the redistribution pattern terminals while still in wafer form, which is a low cost and high throughput process, i.e., very efficient process.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: January 27, 2015
    Inventors: Robert Francis Darveaux, Brett Arnold Dunlap, Ronald Patrick Huemoeller
  • Patent number: 8928118
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 6, 2015
    Inventor: Jayna Sheats
  • Patent number: 8927416
    Abstract: A first insulating film is formed on a semiconductor substrate, an interconnect groove is formed in the first insulating film, the inside of the interconnect groove is filled with a metal film, thereby forming a first interconnect. Then, a protective film is formed on the first insulating film and the first interconnect, and the surface of the protective film is exposed to reactive gas, thereby forming a reaction layer on an interface between the first interconnect and the protective film.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: January 6, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takeshi Harada, Junichi Shibata, Akira Ueki
  • Patent number: 8928138
    Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: January 6, 2015
    Assignee: Vishay-Siliconix
    Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
  • Patent number: 8922005
    Abstract: Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chang Hu, Ching-Wen Hsiao, Chih-Hua Chen, Chen-Shien Chen, Tin-Hao Kuo
  • Patent number: 8916910
    Abstract: Reconfigurable 3D interconnect is provided that can be used for digital and RF signals. The reconfigurable 3D interconnect can include an array of vertical interconnect vias (or TSVs) providing a signal path between a first core element of a 3D IC and a second core element of the 3D IC stacked above the first core element. A routing circuit can be used to route a signal from the first core element to the second core element through selected TSVs of the array of TSVs providing the signal path between the first core element and the second core element. The routing circuit allows re-routing of the signal through different selected TSVs during operation, which can provide real time adjustments and capacity optimization of the TSVs passing the particular signal between the elements.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: December 23, 2014
    Assignee: Research Foundation of State University of New York
    Inventors: Robert E. Geer, Wei Wang, Tong Jing
  • Patent number: 8916976
    Abstract: First semiconductor element 1 being buried in first insulating material 2; second semiconductor element 5 being covered by second insulating material 6; connection electrode 4 being buried in first insulating material 2 arranged between circuit surface of first semiconductor element 1 and circuit surface of second semiconductor element 5; external connection terminal 8 being arranged on lower surface of first insulating material 2 facing in the same direction as lower surface of first semiconductor element 1 opposite to circuit surface thereof; connection electrode 4 forming a part of path for electrically connecting circuit surface of first semiconductor element 1 and circuit surface of second semiconductor element 5 to each other; first semiconductor element 1 and external connection terminal 8 being electrically connected to each other by way of wire 3 and via 7 passing through region of insulating layer other than region thereof burying connection electrode 4.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: December 23, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masamoto Tago, Yoichiro Kurita
  • Patent number: 8916975
    Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: December 23, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang Kun Park, Seong Hwi Song, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee, Jae Min Jang
  • Patent number: 8907487
    Abstract: An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Seung Jee Kim, Qwan Ho Chung, Jong Hyun Nam, Si Han Kim, Sang Yong Lee, Seong Cheol Shin
  • Patent number: 8902123
    Abstract: To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: December 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Konami Izumi
  • Patent number: 8901747
    Abstract: A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: December 2, 2014
    Assignee: MoSys, Inc.
    Inventors: Michael J. Miller, Mark Baumann, Richard S. Roy
  • Patent number: 8901734
    Abstract: An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: December 2, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SungWon Cho, TaeWoo Kang
  • Patent number: 8896130
    Abstract: A multi-chip stack structure and a method for fabricating the same are provided.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: November 25, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chung-Lun Liu, Jung-Pin Huang, Yi-Feng Chang, Chin-Huang Chang
  • Patent number: 8890332
    Abstract: A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: MoSys, Inc.
    Inventors: Michael J. Miller, Mark William Baumann, Richard S. Roy
  • Patent number: 8884419
    Abstract: Embodiments of the present disclosure provide a substrate, one of either a semiconductor die or an interposer disposed on the substrate, the semiconductor die or the interposer having a first surface attached to the substrate and a second surface that is opposite to the first surface, one or more interconnect structures formed on the second surface of the semiconductor die or the interposer, a mold compound formed to substantially encapsulate the semiconductor die or the interposer, and one or more vias formed in the mold compound to facilitate coupling the one or more interconnect structures with another component. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: November 11, 2014
    Assignee: Marvell International Ltd.
    Inventors: Shiann-Ming Liou, Albert Wu