Abstract: An electronic card comprising: a first card portion including lightning protection components, a first ground plane and a first ground zone; a second card portion comprising functional components, a second ground plane and a second ground zone; a third card portion, which separates and electrically isolates the first ground plane and the first ground zone from the second ground plane and from the second ground zone; the first ground zone and the second ground zone being unvarnished; the first ground zone and the second ground zone being arranged in order to be applied onto a housing element that is electrically conductive and that belongs to a housing in which the electronic card is integrated.

Abstract: Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die.

Abstract: Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die.

Abstract: A chip card in the form of an ID-1 card, a plug-in SIM or a USB token has a layered compound (12) with two (4, 5) or three (4, 5, 9) layers extending over the complete chip card (1). An exterior foil layer (4) has on its outward facing front side (4a) a communication contact layout (2) and on its back side (4b) a flip chip (7), as well as a flip chip contact layout (6) which is electroconductively connected with the communication contact layout (2) on the front side.

Abstract: A semiconductor device and a method for fabricating the same, wherein a portion of a substrate comprising a pad is removed to form a via hole. An insulating layer is formed on the substrate. A portion of the insulating layer is removed to form a plurality of openings exposing portions of the pad. A through electrode is formed to fill the via hole and to be electrically connected to the pad through one of the plurality of openings. A portion of the pad is exposed by another opening among the plurality of openings.

Abstract: A chip card in the form of an ID-1 card, a plug-in SIM or a USB token has a layered compound (12) with two (4, 5) or three (4, 5, 9) layers extending over the complete chip card (1). An exterior foil layer (4) has on its outward facing front side (4a) a communication contact layout (2) and on its back side (4b) a flip chip (7), as well as a flip chip contact layout (6) which is electroconductively connected with the communication contact layout (2) on the front side.

Abstract: An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s).

Abstract: The present invention provides an ID chip or an IC card in which the mechanical strength of an integrated circuit can be enhanced without suppressing a circuit scale. An ID chip or an IC card of the present invention has an integrated circuit in which a TFT (a thin film transistor) is formed from an insulated thin semiconductor film. Further, an ID chip or an IC card of the present invention has a light-emitting element and a light-receiving element each using a non-single-crystal thin film for a layer conducting photoelectric conversion. Such a light-emitting element or a light-receiving element may be formed consecutively to (integrally with) an integrated circuit or may be formed separately and attached to an integrated circuit.

Abstract: The present invention provides a microwave annealing method for a plastic substrate. The method comprises pulsed microwave annealing to an organic photo-voltaic device to avoid warpage and degradation of the plastic substrate. Utilizing pulsed microwave annealing method can improve the wettability of the organic layer on the plastic substrate verified by contact angle measurement, and achieving the organic solar cell fabricated with higher power conversion efficiency.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit a signal using proximity communication. A layer of fill metal is located in proximity to this array of transmission pads, wherein the layer of fill metal is “floating” (e.g., not connected to any signal). Leaving this layer of fill metal floating reduces the parasitic capacitance for the array of transmission pads, which can reduce the amount of power needed to transmit the signal.

Abstract: A memory card includes a circuit board, a first semiconductor chip mounted on the circuit board with a bump sandwiched between the first semiconductor chip and the circuit board, a second semiconductor chip mounted on the circuit board with a bump sandwiched between the second semiconductor chip and the circuit board with a clearance not greater than 1 mm between the first semiconductor chip and the second semiconductor chip, a first sealing resin layer surrounding the bump and existing between the first semiconductor chip and the circuit board, and a second sealing resin layer surrounding the bump and existing between the second semiconductor chip and the circuit board, and a cover covering the first semiconductor chip, the second semiconductor chip on a principal face of the circuit board.

Abstract: In order to extend the communication distance of an electronic tag chip, it is required to reduce power consumption of the electronic tag chip. After having formed capacitors and diodes on an SOI (Silicon on Insulator), remove a silicon substrate of the SOI. It becomes possible to reduce the capacitors and diodes of the electronic tag chip in parasitic capacitance relative to the ground, which makes it possible to reduce the power consumption of the electronic tag chip, thereby enabling the electronic tag chip to increase in communication distance thereof.

Abstract: A leadframe design for forming leadframe-based semiconductor packages having curvilinear shapes is disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts.

Abstract: In the present application, is disclosed a method of manufacturing a flexible semiconductor device having an excellent reliability and tolerance to the loading of external pressure. The method includes the steps of: forming a separation layer over a substrate having an insulating surface; forming an element layer including a semiconductor element comprising a non-single crystal semiconductor layer, over the separation layer; forming an organic resin layer over the element layer; providing a fibrous body formed of an organic compound or an inorganic compound on the organic resin layer; heating the organic resin layer; and separating the element layer from the separation layer. This method allows the formation of a flexible semiconductor device having a sealing layer in which the fibrous body is impregnated with the organic resin.

Abstract: A memory card includes a circuit board, a first semiconductor chip mounted on the circuit board with a bump sandwiched between the first semiconductor chip and the circuit board, a second semiconductor chip mounted on the circuit board with a bump sandwiched between the second semiconductor chip and the circuit board with a clearance not greater than 1 mm between the first semiconductor chip and the second semiconductor chip, a first sealing resin layer surrounding the bump and existing between the first semiconductor chip and the circuit board, and a second sealing resin layer surrounding the bump and existing between the second semiconductor chip and the circuit board, and a cover covering the first semiconductor chip, the second semiconductor chip on a principal face of the circuit board.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: A carrier structure embedded with semiconductor chips is disclosed, which comprises a core board and a plurality of semiconductor chips mounted therein. The core board comprises two metal plates between which an adhesive material is disposed. An etching stop layer is deposited on the both surfaces of the core board. Pluralities of cavities are formed to penetrate through the core board. The semiconductor chips each have an active surface on which a plurality of electrode pads are disposed, and those are embedded in the cavities and mounted in the core board. An etching groove formed on the core board between the neighboring semiconductor chips is filled with the adhesive material. The present invention avoids the production of metal burrs when the carrier structure is cut.

Abstract: The present invention is to provide a semiconductor device that achieves high mechanical strength without reducing the circuit scale and that can prevent the data from being forged and altered illegally while suppressing the cost. The present invention discloses a semiconductor device typified by an ID chip that is formed from a semiconductor thin film including a first region with high crystallinity and a second region with the crystallinity inferior to the first region. Specifically, a TFT (thin film transistor) of a circuit requiring high-speed operation is formed by using the first region and a memory element for an identifying ROM is formed by using the second region.

Abstract: The Invention, titled the “Split Chip” by the Inventor, contemplates an RFID enabled consumer oriented tracking system which protects consumer privacy by splitting a miniaturized silicon RFID transponder circuit into a retained piece and a detached piece. The two pieces are electrically connected by a fine piece of conductive material. Each piece is dependent upon the other in order to disgorge data. The electrical connection between the two pieces can be severed by the consumer by tearing the fine piece of conductive material at a designated spot on the substrate making the Split Chip moribund. Upon a return or refund of the consumer item the original data can be recovered through a laser guidance system which connects the retained piece and its alpha numeric identifier to a back end host computer administration network.

Abstract: A semiconductor device is disclosed. Embodiments relate to a semiconductor device which includes an active region including a source region, a drain region, and a channel region. A gate electrode, source electrodes, and a drain electrode are formed around the active region. A plurality of gate fingers diverge from the gate electrode into the channel region. A plurality of source fingers diverge from the source electrodes into the source region, the source fingers being disposed between the gate fingers in a predetermined pattern, the source fingers having at least two finger lines connected to each other via at least one grid line. A plurality of drain fingers diverge from the drain electrode into the drain region, the drain fingers being disposed between the gate fingers where the source fingers are not disposed.

Abstract: A Flash memory card is disclosed comprising a substrate, a Flash memory die on top of the substrate, a controller die on top of the Flash memory die, and an interposer coupled to with the controller die and on top of the Flash memory die wherein the interposer results in substantial reduced wire bonding to the substrate. The interposer can surround or be placed side by side with the controller die. A system and method in accordance with the present invention achieves the following objectives: (1) takes advantage of as large of a Flash memory die as possible, to increase the density of the Flash card by reducing the number of wire bond pads on the substrate and enabling insertion of the largest die possible that can fit inside a given card interior boundary; (2) more efficiently stacks Flash memory dies to increase density of the Flash card; and (3) has a substantially less number of bonding wires to the substrate as possible, to improve production yield.

Abstract: One embodiment of a semiconductor package described herein includes a substrate having a first through-hole extending therethrough; a conductive pattern overlying the substrate and extending over the first through-hole; a first semiconductor chip facing the conductive pattern such that at least a portion of the first semiconductor chip is disposed within the first through-hole; and a first external contact terminal within the first through-hole and electrically connecting the conductive pattern to the first semiconductor chip.

Abstract: Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.

Abstract: A method is provided for manufacturing an integrated electronic component arranged on a substrate wafer. According to the method, at least one metallization step is performed, and a value of an electrical parameter of the integrated electronic component is determined after the at least one metallization step. A subsequent metallization step is performed after determining the value of the electrical parameter. The subsequent metallization step is performed using an adjustment mask chosen from n predefined masks based on a desired value of the electrical parameter, so as to obtain the desired value of the electrical parameter of the integrated electronic component after manufacturing. In one preferred embodiment, a series of electrical tests is performed on the wafer using test equipment, and the value of the electrical parameter is determined using the same test equipment as is used to perform the series of electrical tests.

Abstract: A process yield of a semiconductor device is enhanced. To that end, there is provided a semiconductor device comprising a substrate having a component mount face with semiconductor chips mounted thereon, the substrate being provided with a plurality of connection leads, and a cap made of resin, placed over the component mount face of the substrate so as to cover the same, the a cap having a first body part, and a second body part larger in thickness than the first body part. Because product information in the form of inscriptions is engraved on the top surface side of the second body part of the cap, the product information can be displayed without the use of an ink mark, it is possible to prevent occurrence of marking defects due to ink bleed, and so forth, thereby enhancing the process yield of a memory card (the semiconductor device).

Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allow the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.

Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allowed the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.

Abstract: A chip card with a chip module having an integrated circuit and, for external contacting, has on a main face a contact zone with a number of contact areas which are spaced apart from one another and are electrically connected to the integrated circuit. At least one contact area is made up of first functional regions with first surfaces and of second functional regions with second surfaces, and the first surfaces of the first functional regions lie higher with respect to the main face than the second surfaces of the second functional regions.

Abstract: A memory card includes: a package in the form of a thin plate made of an insulating material and configured to be inserted into and removed from a slot of an external apparatus; a plurality of contacts provided on the package and configured to transmit a signal to and from the external apparatus; the contacts being juxtaposed in a direction perpendicular to a loading/unloading direction, in which the memory card is loaded into or unloaded from the external apparatus, in a region of a flat face, which is one of faces of the package in a thicknesswise direction, except locations on the opposite sides in the direction perpendicular to the loading/unloading direction; and a pair of side labels adhered to the locations on the opposite sides of the upper face of the package and extending along the loading/unloading direction.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: A non-contact identification semiconductor device is provided with a semiconductor chip including a receiving circuit that receives an inquiry to the non-contact identification semiconductor device, a memory that stores identification information of multiple bits and a sending circuit that sends the identification information. An antenna coupled to said semiconductor chip receives the identification information from said semiconductor chip and transmits the identification information outside of said non-contact semiconductor. The long side length of the semiconductor chip is not greater than 0.5 mm in plane dimension, and the identification information is stored by a pattern printed by an electron beam.

Abstract: Provided is a non-contact ID card which is superior in the productivity and the electrical properties, and a method capable of manufacturing such non-contact ID card. The non-contact ID card of the present invention is characterized in that the non-contact ID card comprises an antenna circuit board in which an antenna is formed on a substrate and an interposer board in which an enlarged electrode, which is connected to an electrode of an IC chip, is formed on a substrate on which the IC chip is mounted. The non-contact ID card is formed by laminating both boards in such a manner that the electrode of the antenna and the enlarged electrode are bonded, in which both electrodes are adhesively bonded by an insulating adhesive filled in minute recesses dispersed on bonding faces of the electrode of the antenna and/or the enlarged electrode.

Abstract: A semiconductor device comprises a substrate, an external terminal provided on the substrate, an internal wiring pattern electrically connected to the external terminal, a semiconductor chip mounted on the substrate and electrically connected to the internal wiring pattern, and an antenna pattern. The antenna pattern provided at each of adjacent two corner portions of the substrate and is grounded.

Abstract: A chip package is provided. The chip package includes at least one chip, an interconnection structure, a plurality of second pads and at least one panel-shaped component, wherein the chip includes a plurality of first pads on a surface thereof. The interconnection structure is disposed on the chip, and the first pads of the chip are electrically coupled to the interconnection structure. The second pads are disposed on the interconnection structure, and the panel-shaped component is embedded in the interconnection structure. The panel-shaped component also includes a plurality of electrodes on its two opposite surfaces, and the second pads are electrically coupled to the first pads of the chip through the interconnection structure and the panel-shaped component.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: A semiconductor arrangement is disclosed, having transistors based on organic semiconductors and non-volatile read/write memory cells. The invention relates to a semiconductor arrangement, constructed from transistors, in the case of which the semiconductor path is composed of an organic semiconductor, and memory cells based on a ferroelectric effect perferably in a polymer, for use in RF-ID tags, for example.

Abstract: In the stacked semiconductor package, on a first semiconductor chip, a second semiconductor chip is stacked offset such that a portion of the first semiconductor chip is exposed. At least one first conductor electrically connects the exposed portion of the first semiconductor chip to the second semiconductor chip. The first conductor may be formed such that the first conductor does not extend beyond a periphery of the first semiconductor chip. The first conductor electrically connects at least one bond pad on the first semiconductor chip with at least one bond pad on the second semiconductor chip, and a redistribution pattern electrically connects the bond pad on the second semiconductor chip to a differently positioned bond pad on the second semiconductor chip.

Abstract: A chip embedded package structure is provided. A stiffener is disposed on a tape. The tape has at least an alignment mark and the stiffener has at least a chip opening. A chip having a plurality of bonding pads thereon is disposed on the tape within the chip opening such that the bonding pads face the tape. A plurality of through holes is formed in the tape to expose the bonding pads respectively. After that, an electrically conductive material is deposited to fill the through holes and form a plurality of conductive vias that connects with the bonding pads respectively. A multi-layered interconnection structure is formed on the surface of the tape away from the chip. The multi-layered interconnection structure has an inner circuit that connects to the conductive vias. The inner circuit has a plurality of metallic pads disposed on the outer surface of the multi-layered interconnection structure.

Abstract: An approach to DRAM memory chip packaging leveraging the chip center position for wire bond pads to minimize time-of-flight and impedance effects resulting from stacking in a BGA application. A top layer of a dual device stack of center bus chips is stacked with an offset in a single direction with respect to a bottom layer of the dual device stack. The top layer of chips may be wire bonded to the opposite side of the module substrate. The center bus may be made to traverse to the substrate between two memory devices on the lower layer. To assemble the offset stacking devices into a high density module, devices are placed sequentially on a module substrate such that approximately one half of the protruding lower memory device is used as a support for the overhanging upper memory device chip of the next device stack.