Abstract: A semiconductor device includes a wiring board having a wiring pattern, a semiconductor chip that has an integrated circuit and is mounted on a first surface of the wiring board to electrically connect with the wiring pattern, a spacer that is disposed on a second surface of the wiring board and has inside thereof an electronic component that is electrically connected with the wiring pattern and an external terminal that is disposed on the second surface and electrically connected with the wiring pattern.

Abstract: A chip package is provided. The chip package includes at least one chip, an interconnection structure, a plurality of second pads and at least one panel-shaped component, wherein the chip includes a plurality of first pads on a surface thereof. The interconnection structure is disposed on the chip, and the first pads of the chip are electrically coupled to the interconnection structure. The second pads are disposed on the interconnection structure, and the panel-shaped component is embedded in the interconnection structure. The panel-shaped component also includes a plurality of electrodes on its two opposite surfaces, and the second pads are electrically coupled to the first pads of the chip through the interconnection structure and the panel-shaped component.

Abstract: A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

Abstract: A three-dimensional stacked semiconductor package includes first and second chips, first and second adhesives, first and second wire bonds, a lead and an encapsulant. The chips are disposed on opposite sides of the lead, and the wire bonds contact the same side of the lead.

Abstract: A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being exposed outside. A metal layer is formed over the dielectric layer and the exposed bond fingers and electric contacts, and patterned to form a plurality of conductive traces that electrically connect the electric contacts of the chip to the bond fingers of the substrate. The conductive traces replace conventional wire bonding technology and thus eliminate the occurrence of wire sweep or short circuits in fabrication processes. Therefore, a low profile chip with a reduced pitch between adjacent electric contacts can be used without being limited to feasibility of the wire bonding technology.

Abstract: A semiconductor package without bonding wires and a fabrication method are provided. The semiconductor package includes a substrate having a front surface and a back surface, two chips formed on the front surface, two dielectric layers formed on the chips respectively, two conductive trace layers formed on the dielectric layers respectively, an insulating layer formed on one of the dielectric layers, and a plurality of solder balls implanted on the back surface of the substrate. One of the dielectric layers is formed on one of the chips and attached to an entire non-active surface of the other of the chips.

Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.

Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Abstract: A microelectronic package includes a microelectronic element having contacts accessible at a surface thereof, a layer overlying the microelectronic element, the layer having a first surface and a sloping peripheral edge extending away from the first surface of the layer, and conductive terminals overlying the microelectronic element, wherein the layer supports the conductive terminals over the microelectronic element. The package also includes conductive traces having first ends electrically connected with the contacts of the microelectronic element and second ends electrically connected with the conductive terminals, with at least one of the conductive traces having a section that is in contact with and extends along the sloping peripheral edge of the layer, and a compliant material disposed between the conductive terminals and the microelectronic element so that the conductive terminals are movable relative to the microelectronic element.

Abstract: A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.