Abstract: Systems for and methods for generating precise structure reconstruction using slice and view images, are disclosed. An example method comprises, obtaining a slice and view images of a sample that depicts a 3D fiducial and cross-sections of a structure in the sample. The 3D fiducial is configured such that when a layer of material having a uniform thickness is removed from a surface of the sample that includes the 3D fiducial the cross-sectional shape of the 3D fiducial in the new surface is consistent. Relative positions are determined between the 3D fiducial the cross-sections of the structure in individual images. Positional relationships are then determined between the cross-sections of the structure in different images in a common reference frame based on the relative positions.

Abstract: Embodiments of the present invention provide an optical structure, an optical coupling method, and a photonic integrated circuit chip. The optical structure includes: two optical coupling structures with different structures, that is, a first optical coupling structure and a second optical coupling structure. The first optical coupling structure includes a first optical transmission structure, and a first coupling port and a second coupling port both connected to the first optical transmission structure. The second optical coupling structure includes a second optical transmission structure, and a third coupling port and a photoelectric conversion structure both connected to the second optical transmission structure. When optical signals are provided in different methods or optical coupling is performed in different scenarios, optical signal coupling can be realized by using optical coupling structures of different structures in the abovementioned optical structure.

Abstract: Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a device region, an inner ring surrounding the device region, an outer ring surrounding the inner ring, a first corner area between an outer corner of the inner ring and an inner corner of the outer ring, and a second corner area disposed at an outer corner of the outer ring. The first corner area includes a first active region including a channel region and a source/drain region, a first gate structure over the channel region of the first active region, and a first source/drain contact over the source/drain region of the first active region. The first source/drain contact continuously extends from a first edge of the first corner area to a second edge of the first corner area.

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

Abstract: A method for manufacturing a semiconductor device structure with overlay marks is provided. The method includes providing a substrate; forming a first light-emitting feature on the substrate; forming a first pattern on the first light-emitting feature; and forming a second pattern on the first pattern. The first light-emitting feature is configured to emit a light of a first wavelength, and the first pattern has a first transmittance to the light of the first wavelength, the second pattern has a second transmittance to the light of the first wavelength, and the first transmittance is different from the second transmittance.

Abstract: A printed circuit board includes: a base substrate; a pad region having a plurality of pad patterns disposed on one surface of the base substrate; and a dummy region having a plurality of conductive dummy patterns separated from the plurality of pad patterns to be disposed on the one surface of the base substrate. The pad region includes a first edge region, and a second edge region disposed in a diagonal direction of the first edge region on the one surface of the base substrate. The dummy region includes a third edge region, and a fourth edge region disposed in a diagonal direction of the third edge region on the one surface of the base substrate.

Abstract: An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

Abstract: An electronic component module includes a substrate, a mounting-type electronic component, a mounting-type electronic component, an insulating resin, and an insulating resin. The mounting-type electronic component is mounted on a first main surface of the substrate. The mounting-type electronic component is mounted on a second main surface of the substrate. The insulating resin covers the first main surface and the first mounting-type electronic component. The insulating resin covers the second main surface and the second mounting-type electronic component. The first mounting-type electronic component is an electronic component including a semiconductor substrate. A top surface of the semiconductor substrate of the first mounting-type electronic component opposite to the first main surface is exposed from the insulating resin. Printing is applied to the top surface, which is an exposed surface of the semiconductor substrate.

Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, disposed over the third metal layer; a third level including a plurality of third transistors, disposed over the second level; a via disposed through the second and third levels; a fourth metal layer disposed over the third level; a fifth metal layer disposed over the fourth metal layer; and a fourth level including a second single crystal silicon layer and is disposed over the fifth metal layer, where each of the plurality of second transistors includes a metal gate, and the via has a diameter of less than 450 nm.

Abstract: The present application discloses a semiconductor device having integral alignment marks with decoupling features and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a dielectric stack positioned on the substrate; two conductive features positioned in the dielectric stack; a decoupling unit positioned in the dielectric stack, between the two second conductive features, and comprising a bottle-shaped cross-sectional profile; and an alignment mark positioned on the decoupling unit. The alignment mark comprises a fluorescence material.

Abstract: An IC module is provided that includes an IC having a terminal electrode, and a substrate having a first surface and a second surface opposite to each other and having a land formed on the first surface. Moreover, the land is connected to the terminal electrode of the IC. On the first surface of the substrate, an insulator layer that covers an area outside of a formation area of the land is formed. A difference between a thickness of the insulator layer and a thickness of the IC is smaller than a difference between the thickness of the insulator layer and a thickness of the substrate, and the thickness of the substrate is smaller than the thickness of the insulator layer.

Abstract: A chip device with a logic circuitry (105) protected by a randomized logic encryption based on a key (K) for preventing a designated usage of the logic circuitry (105) by an unauthorized user comprises: a physically unclonable function, PUF, (110), a storage (120), and a chip enabler (130) with one or more registers (132). The physically unclonable function, PUF, (110) is configured to generate a device-individual response (Re) based on a challenge (Ch). The storage (120) has stored the challenge (Ch) and a data element (C), the data element (C) being an encryption of the key (K) with the response (Re) of the PUF (110) as encryption key. The enabler (130) is configured to enable the logic circuitry (105) for the designated usage only, when the key (K) is transferred to the register(s) (132), the key (K) being a decryption of the data element (C) with the response (Re) as the encryption key.

Abstract: There is provided a semiconductor apparatus including: a memory operation terminal for inputting a first signal; a high-speed communication terminal for inputting a second signal to a high-speed communication controller; an inspection terminal for performing debugging; and a terminal mounting surface at which a plurality of coupling terminals including the memory operation terminal, the high-speed communication terminal, and the inspection terminal are provided, in which the terminal mounting surface includes a first side, a second side, a third side, and a fourth side, the plurality of coupling terminals include a first terminal row located adjacent to the third side and arranged from the first side toward the second side; the first terminal row includes a first inspection terminal among the plurality of inspection terminals, and the first inspection terminal is located closest to the first side in the first terminal row.

Abstract: Embodiments of this invention provide a measurement map configuration method and apparatus. A wafer to be inspected is provided. The wafer includes a plurality of inspection marks. A first inspection result is obtained based on a first set of inspection marks. A second set of inspection marks is selected based on a preset rule. The second set of inspection marks is less than the first set of inspection marks. A second inspection result is obtained based on the second set of inspection marks. If an overlay accuracy of the second inspection result matches an overlay accuracy the first inspection result, a measurement map for the wafer is set based on target inspection marks. The target inspection marks are the second set of inspection marks of the measurement map.

Abstract: The present technology relates to a memory device and a method of manufacturing the same. A memory device according to an embodiment of the present disclosure includes a main chip region, a chip guard region disposed adjacent to the main chip region, a plurality of chip guard patterns formed in the chip guard region, and a buffer slit formed in a space between the plurality of chip guard patterns.

Abstract: A semiconductor device includes: a substrate; a first connection structure disposed on the substrate, the first connection structure Including a first connection conductor; a transistor disposed between the substrate and the first connection structure; a first bonding structure Including a first bonding pad connected to the first connection conductor; a second bonding structure including a second bonding pad connected to the first bonding pad; a second connection structure including a second connection conductor connected to the second bonding pad; a stack structure disposed on the second connection structure; a channel structure penetrating the stack structure; and a chip guard penetrating the second connection structure, the second bonding structure, the first bonding structure, and the first connection structure, the chip guard surrounding the stack structure and the channel structure.

Abstract: A substrate testing device includes a first testing component configured to couple to electrical pads of a substrate and perform electrical testing on one or more dies of the substrate during a test. The substrate testing device includes a second testing component configured to perform optical testing of the one or more dies during the test. The substrate testing device further includes a third testing component comprising a three-dimensional scanner configured to perform a dimensional scan of the one or more dies of the substrate, wherein the third testing component is to perform geometrical testing on the one or more dies during the test.

Abstract: An assembly. In some embodiments, the assembly includes a first semiconductor chip, a substrate, and a first alignment element. The alignment of the first semiconductor chip and the substrate may be determined at least in part by engagement of the first alignment element with a first recessed alignment feature, in a surface of the first semiconductor chip.

Abstract: An electronic device is provided with an electronic component having a base material and a terminal electrode formed on a first surface of the base material, and a circuit substrate in which a pad for mounting the electronic component is formed on a first surface. A hole for light transmission is formed in the pad, and the pad and the terminal electrode are electrically and mechanically connected to each other with a cured product of optical firing paste obtained by receiving light from a second surface that is a surface opposite to the first surface of the circuit substrate.

Abstract: A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first electronic device and a second electronic device. The first electronic device has an active surface and a lateral surface angled with the active surface, and the lateral surface includes a first portion and a second portion that is non-coplanar with the first portion. The second electronic device is disposed on the active surface of the first electronic device.

Abstract: To provide a wiring formation method that can increase the wiring density in a case where wiring is formed on an inclined surface by three-dimensional additive manufacturing. The wiring formation method of the present disclosure includes a metal member forming step of forming multiple metal members with a first fluid containing metal particles, a resin layer forming step of forming a resin layer including an upper surface and an inclined surface inclined downward from the upper surface, and a connection wiring forming step of forming multiple connection wirings on the inclined surface and the upper surface of the resin layer with a second fluid containing metal particles, and the connection wirings being formed to individually connect the multiple connection wirings to the multiple metal members on a lower surface of the inclined surface.

Abstract: A stress sensor includes a semiconductor substrate with a first transistor arrangement and a second transistor arrangement. The first transistor arrangement includes a first transistor with a first source-drain channel region and a second transistor with a second source-drain channel region. The first transistor and the second transistor are aligned relative to each other such that the current flow directions in the first and the second source-drain channel regions are opposite to each other. The second transistor arrangement includes a third transistor with a third source-drain channel region and a fourth transistor with a fourth source-drain channel region. The third transistor and the fourth transistor are aligned relative to each other such that the current flow directions in the third and the fourth source-drain channel regions are opposite to each other. The stress sensor generates a gradient-compensated output signal used to determine a mechanical stress acting on the semiconductor substrate.

Abstract: A physically unclonable function includes a circuit that translates a normally distributed sequence of raw sample into a sequence of uniformly distributed binned values across sub-bins of bins. Helper circuitry generates centering values and parity bits based on binned values generated during registration. Each centering value is associated with a raw sample value corresponding to a binned value and indicates an offset of a sub-bin in one of the bins. A distance calculator generates a set of distances from each raw sample value based on the centering value associated with the raw sample value. Each distance indicates a difference between the respective raw sample value and a raw sample value equivalent to a midpoint of a sub-bin offset by the associated centering value in a bin. A trellis decoder generates a PUF signature based on the candidate symbols, sets of distances, and parity bits.

Abstract: An apparatus for thermally joining thermoplastic fiber composite components includes a pressurization arrangement for jointly covering, at least in a region of a joining zone, thermoplastic fiber composite components to be joined and applying pressure to the thermoplastic fiber composite components to press the thermoplastic fiber composite components against one another, at least in the joining zone, the pressurization arrangement being flexible, at least in some section or sections. A welding device is configured for welding the fiber composite components in the joining zone during pressurization. The pressurization arrangement and welding device are configured to weld the thermoplastic fiber composite components in a pressurized state in the joining zone. The pressurization arrangement is configured to maintain pressurization independently of the welding device until the joining zone solidifies.

Abstract: A micro-LED transfer method, including: moving a passing substrate to a position above a donor substrate and moving the pasting substrate in a direction approaching the donor substrate to paste up LED grains so that the LED grains are separated from the bearing substrate; moving the pasting substrate with the LED grains to a position above a target substrate with the LED grains being closer to the target substrate than the pasting substrate, and conducting an alignment so that the LED grains are directly opposite to positions on the target substrate where the LED grains are to be arranged; and heating the pasting substrate with the LED grains to a first temperature greater than or equal to a melting temperature of the hot melt adhesive film to melt the hot melt adhesive film, so that the LED grains are separated from the pasting substrate and transferred to the target substrate.

Abstract: A method for thinning a fingerprint identification module includes the steps of: providing at least one fingerprint identification module, wherein the fingerprint identification module includes a glass substrate and a plurality of laminated fingerprint identification members; providing a protective layer on each laminated fingerprint identification member; providing a dissociable sealant around each laminated fingerprint identification member and the protective layer of the fingerprint identification module and being adhered to support plate to form a carrier plate to be etched; etching the carrier plate to be etched and allowing an etching solution to etch the glass substrate until a thickness to be thinned is etched to form a semi-finished carrier plate; dissociating the dissociable sealant of the semi-finished carrier plate to reduce its viscosity; and removing the support plate, the dissociable sealant and the protective layer to complete a finished product of the thinned fingerprint identification module

Abstract: A wafer manufacturing method for manufacturing a wafer from an ingot includes forming a peeling layer within the ingot by positioning a condensing point at a depth corresponding to the thickness of the wafer to be produced, and irradiating the ingot with a first laser beam, forming a character, a number, or a mark representing information regarding resistivity in or on the ingot by positioning a condensing point in a region in which devices are not to be formed and irradiating the ingot with a second laser beam, and dividing the ingot with the peeling layer as a starting point.

Abstract: The method for forming overlay marks includes: providing a substrate, a surface of the substrate having a mark layer and a first mask layer; forming first trenches and second trenches in the first mask layer; forming a spacer layer covering side walls of the first trenches and side walls of the second trenches; backfilling the first trenches and the second trenches; removing the spacer layer; and etching the mark layer and forming main overlay marks and dummy overlay marks.

Abstract: A method and a testing apparatus related to wafer testing are provided. In the method, testing raw data is obtained by a testing apparatus operating with a Unix-related system. The testing raw data is a testing result of probe testing on one or more wafers by the testing apparatus. The testing raw data is converted into converted data by the testing apparatus. The converted data is related to the defect information of the wafer. Analyzed data is generated by the testing apparatus according to the converted data. The analyzed data is used for a graphical interface. Therefore, real-time defect analysis during the testing procedure may be provided.

Abstract: Embodiments are directed to short and/or near short etch rework. A microfluidic device is positioned on a portion of a circuit having a defect. The microfluidic device is caused to dispense etchant that removes the defect of the circuit, where a flow of the etchant is controlled to access the portion of the circuit having the defect to thereby etch away the defect, the flow of the etchant being obstructed from accessing other portions of the circuit. The microfluidic device is used to extract the etchant from the portion of the circuit such that the etchant avoids contact with the other portions of the circuit. The microfluidic device is removed from the circuit.

Abstract: A cleaning apparatus includes a spinner table for holding a workpiece thereon, a cleaning nozzle for supplying cleaning water to the workpiece held on the spinner table, an ultrasonic vibrator for applying ultrasonic vibrations to the cleaning water supplied from the cleaning nozzle to the workpiece, a water layer forming unit for forming a layer of the cleaning water in a clearance between the cleaning nozzle and the workpiece, the water layer forming unit having a cover surrounding the cleaning nozzle, and a drain unit for draining the cleaning water out of the cleaning apparatus, the drain unit having a flow channel for allowing the cleaning water supplied from the cleaning nozzle to the workpiece to flow therethrough.

Abstract: A device chip manufacturing method for dividing a silicon wafer formed with devices in each of regions of a front surface partitioned by a plurality of streets includes coating the front surface of the silicon wafer with a resist film, exposing the silicon wafer by removing the resist film in regions along the streets, forming deep grooves by alternately repeating isotropic etching and coating with a passivation film, and subjecting bottom portions of the deep grooves to anisotropic etching to form division grooves, thereby dividing the silicon wafer.

Abstract: A semiconductor package comprises a lead frame, a die pad, bond pads, and leads. A die may be arranged on the die pad, the die comprising an integrated circuit. In an example, the die and at least a portion of the lead frame are encapsulated with a molding compound (MC). A first thickness of the MC over a first portion of the die is less than a second thickness over a second portion of the die to form a cavity in the MC and the MC directly contacts the first portion and the second portion of the die.

Abstract: A semiconductor device including a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected a chip pad; a process monitoring structure on the edge region; and dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer.

Abstract: Semiconductor devices having measurement features and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a plurality of stacked semiconductor dies each having measurement features formed along an outer periphery of a surface thereof. One or more image capture devices can image the semiconductor device and a controller can detect the measurement features in imaging data received from the image capture devices. The controller can further determine the distance between two or more of the measurement features to estimate a bond line thickness between semiconductor dies in the stack.

Abstract: Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.

Abstract: A method for manufacturing a semiconductor device in which probes and the layout of the electrode pads of a test element group (TEG) are associated is provided. As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Thus, it is necessary to associate the probes and the layout of the electrode pad. According to the method, a layout of a TEG electrode pad corresponding to a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology is provided.

Abstract: A processing apparatus configured to process a processing target object includes a holder configured to hold the processing target object; a holder moving mechanism configured to move the holder in a horizontal direction; a modifying device configured to radiate laser light to an inside of the processing target object to form multiple internal modification layers in a spiral shape; a modifying device moving mechanism configured to move the modifying device in the horizontal direction; and a controller configured to control an operation of forming the internal modification layers. The controller controls operations of the holder and the modifying device such that a spiral processing movement according to the formation of the internal modification layers and an eccentricity follow-up movement of correcting an eccentric amount between the holder and the processing target object held by the holder are shared by the holder and the modifying device.

Abstract: A method is provided and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.

Abstract: For securing a provable resource possession on a host device having spawned a set of virtual machines providing services to a client device, the client device is able to send a challenge request to each virtual machine, the challenge request containing a physically unclonable function (PUF) challenge and a filter rule; receive a PUF filtered response from each virtual machine, the PUF filtered response being a PUF response that is filtered according to the filter rule and obtained by challenging; combine the PUF filtered responses into a reconstructed PUF according to the filter rule; and if the reconstructed PUF corresponds to an expected response in the challenge-response database, validate that the set of virtual machines is effectively running on the right host device.

Abstract: Disclosed is a substrate, associated patterning device and a method for measuring a position of the substrate. The method comprises performing an alignment scan of an alignment mark to obtain simultaneously: a first measurement signal detected in a first measurement channel and a second measurement signal detected in a second measurement channel. The first and second measurement signals are processed by subtracting a first direction component of the first measurement signal from a first direction component of the second measurement signal to obtain a first processed signal, the first direction components relating to said first direction. The position of an alignment mark is determined with respect to the first direction from the first processed signal.

Abstract: A substrate with an electronic component embedded therein includes: a core layer having a through-portion; an electronic component disposed in the through-portion; an encapsulant disposed on a lower surface of the core layer, disposed in at least a portion of the through-portion, and covering at least a portion of a lower surface of the electronic component; and a build-up structure disposed on an upper surface of the core layer, and including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers.

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

Abstract: A substrate for pattern formation, the substrate including at least a base material and a perfluoro(poly)ether group-containing silane compound-derived portion, wherein the base material includes at least one main face having a first region and a second region which is a region for pattern formation, adjacent to the first region, and the perfluoro(poly)ether group-containing silane compound-derived portion is disposed in the first region.

Abstract: In some embodiments, the present disclosure relates to a method that includes aligning a stealth laser apparatus over a wafer using an infrared camera coupled to the stealth laser apparatus. The stealth laser apparatus is used to form a stealth damage region within the wafer that is continuously connected around the wafer and separates an inner region from an outer region of the wafer. The stealth damage region is also arranged at a first distance from an edge of the wafer and extends from a first depth to a second depth beneath a top surface of the wafer. Further, the method includes forming a groove in the wafer to separate the outer region from the inner region of the wafer. The outer region of the wafer is removed using a blade, and a top portion of the inner region of the wafer is removed using a grinding apparatus.

Abstract: The technology disclosed relates to systems and methods for generating a multi-part place identifier with at least one part. The system includes logic to receive a location address and a place name wherein the location address is a validated address. The system includes logic to calculate a geocode for the location address and use the geocode to identify a geometrical boundary encompassing the location address. The system includes logic to convert the identified geometrical boundary to an alpha-numeric identifier forming a Where part of the multi-part place identifier. The system can use an input location address or a place name to match a previously generated and stored multi-part place identifier. The system can provide the generated or matched multi-part place identifier to a user for use in further analysis.

Abstract: A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.

Abstract: A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature.

Abstract: A laser processing apparatus includes a laser light output section, a laser light scanning section, a distance measurement light emitting section which emits distance measurement light, a pair of light receiving elements which receives the distance measurement light emitted from the distance measurement light emitting section and reflected by the workpiece, optical axes of the pair of light receiving elements being arranged inside the housing so as to sandwich an optical axis of the distance measurement light emitting section, a distance measuring section which measures a distance to the surface of the workpiece, and a light receiving lens which is arranged such that each of the optical axes of the pair of light receiving elements passes through the light receiving lens, and condenses the distance measurement light that has been reflected by the workpiece on respective light receiving surfaces of the pair of light receiving elements.