Marks Applied To Semiconductor Devices Or Parts, E.g., Registration Marks, Test Patterns, Alignment Structures, Wafer Maps (epo) Patents (Class 257/E23.179)
  • Patent number: 10388609
    Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 20, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dale Ohmart, Balamurugan Subramanian, Renato Heracleo Orduna Leano, Sonny Evangelista Dipasupil, Ronald Jay V. Peralta
  • Patent number: 10365639
    Abstract: Feature extraction and classification is used for process window monitoring. A classifier, based on combinations of metrics of masked die images and including a set of significant combinations of one or more segment masks, metrics, and wafer images, is capable of detecting a process non-compliance. A process status can be determined using a classifier based on calculated metrics. The classifier may learn from nominal data.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: July 30, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Shabnam Ghadar, Sina Jahanbin, Himanshu Vajaria, Bradley Ries
  • Patent number: 10342138
    Abstract: A chip part includes a substrate having a first main surface on one side thereof and a second main surface on the other side thereof, a functional device famed at a first main surface side of the substrate, an external terminal formed at the first main surface side of the substrate and electrically connected to the functional device, and a light diffusion reflection structure formed at a second main surface side of the substrate and diffusely reflecting light irradiated toward the second main surface of the substrate.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: July 2, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Yasuhiro Kondo, Katsuya Matsuura, Hiroshi Tamagawa
  • Patent number: 10290354
    Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 14, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Avinash Rajagiri, Shantanu Gupta, Jagdish Sabde, Ashish Ghai, Deepak Bharadwaj, Sukhminder Singh Lobana, Shrikar Bhagath
  • Patent number: 10229886
    Abstract: A system is disclosed for providing backward and forward traceability by a methodology which identifies discrete components (die, substrate and/or passives) that are included in a semiconductor device. The present technology further includes a system for generating a unique identifier and marking a semiconductor device with the unique identifier enabling the semiconductor device, and the discrete components within that device, to be tracked and traced through each process and test in the production of the semiconductor device.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: March 12, 2019
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Cheeman Yu, Didier Chavet
  • Patent number: 10210526
    Abstract: An image sensor module that comprises a die, wherein the die comprises light sensors and optics; and wherein the optics comprises luminescent elements that represent die manufacturing information that is indicative of a manufacturing process of the die.
    Type: Grant
    Filed: April 19, 2015
    Date of Patent: February 19, 2019
    Assignees: TOWER SEMICONDUCTOR LTD., HILLBERRY GAT LTD.
    Inventors: Yakov Roizin, Viktor Goldovsky, Avi Strum, Yohanan Davidovich, Amos Fenigstein, Assaf Lahav, David Avner
  • Patent number: 10168378
    Abstract: An electronic device and method of determining an abnormality or a normality of a connecting unit in an electronic device is provided. The electronic device includes an external device connecting unit having a first function connecting unit and a second function connecting unit, wherein the first function connecting unit includes a first identification (first ID) pin configured to detect a connection with an external electronic device, and wherein the second function connecting unit includes a second identification (second ID) pin configured to detect the connection with the external electronic device, and a processor configured to determine that an abnormality occurs in the external device connecting unit when values measured from the first ID pin and the second ID pin satisfy a predetermined condition.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: January 1, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Yeon-Beom Kim
  • Patent number: 10158210
    Abstract: A high power diode laser module is provided with improved high temperature handling and reliability, the module including a housing made of a thermally conductive material and providing a module interior extending between a plurality of housing surfaces, at least one diode laser disposed in the module interior and situated to emit a laser beam, one or more optical components disposed in the module interior and coupled to the at least one diode laser so as to change one or more characteristics of the laser beam, a waveguide in optical communication with the module interior and situated to receive the laser beam from the one or more optical components, and an optical absorber disposed in the housing and situated to receive stray light which is associated with the laser beam and which is propagating in the module interior so as to absorb the stray light and conduct heat associated with the stray light away from the module interior and into the housing.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: December 18, 2018
    Assignee: nLIGHT, Inc.
    Inventors: David C. Dawson, Wolfram Urbanek, David Martin Hemenway
  • Patent number: 10142833
    Abstract: Methods, apparatus and systems are described for identifying potentially counterfeited products or goods.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 27, 2018
    Assignee: OneSpan North America Inc.
    Inventor: Frank Coulier
  • Patent number: 10132858
    Abstract: A method of identifying a component by a response to a challenge is disclosed, the component comprising an array of bipolar transistors connectable in parallel so as to have a common collector contact, a common emitter contact and a common base contact, the challenge comprising a value representative of a total collector current value, the method comprising: receiving the challenge; supplying the total collector current to the common collector contact; detecting instability in each of a group of the transistors; and determining the response in dependence on the group. A circuit configured to operate such a method is also disclosed.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: November 20, 2018
    Assignee: NXP B.V.
    Inventors: Tony Vanhoucke, Viet Nguyen
  • Patent number: 9991892
    Abstract: Electronic device comprising at least: a plurality of MOSFET FD-SOI type transistors among which the first transistors are such that each first transistor comprises a channel in which a concentration of the same type of dopants as those present in the source and drain of said first transistor is greater than the concentration in the channel of each of the other transistors in said plurality of transistors; and an identification circuit capable of determining a unique identifier of the electronic device starting from at least one intrinsic electrical characteristic of each of the first transistors, the value of which depends at least partly on the conductance of said first transistor; and in which the length of a gate of each of the first transistors is less than or equal to about 20 nm.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: June 5, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Romain Wacquez, Jacques Fournier, Carlo Reita
  • Patent number: 9904994
    Abstract: A method for analyzing the shape of a wafer according to an embodiment comprises the steps of: acquiring a sectional image showing a wafer to be analyzed; finding a coordinate row of the surface contour of the wafer in the sectional image; and obtaining shape analysis data, including information about the shape of the wafer, using the coordinate row.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: February 27, 2018
    Assignee: LG SILTRON INCORPORATED
    Inventors: Jae Hyeong Lee, Ja Young Kim
  • Patent number: 9870829
    Abstract: A flash memory apparatus having a physical unclonable function (PUF) and an embodying method of the same are provided. To elaborate, the flash memory apparatus includes a flash memory unit that comprises a main memory area and a peripheral memory area; a challenge input unit that receives input of a challenge value; a read voltage setting unit that sets a read voltage based on the input challenge value; a data reading unit that reads data by applying the read voltage to a memory cell included in a pre-set memory area in the peripheral memory area each time the challenge value is input; and a response output unit that outputs the read data as a response value corresponding to the challenge value, wherein the pre-set memory area consists of a plurality of memory cells comprising two or more memory cells having different threshold voltage values.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: January 16, 2018
    Assignee: Korea University Research and Business Foundation
    Inventors: Jong Sun Park, Sang Kyu Lee
  • Patent number: 9791502
    Abstract: Disclosed is an integrated circuit (IC) chip having an on-chip usable life depletion meter. This meter incorporates programmable bits, which represent units of usable life. These programmable bits are sequentially ordered from an initial programmable bit to a last programmable bit and are automatically programmed in order, as the expected usable life of the IC chip is depleted. These programmable bits are readable to determine the remaining usable life of the IC chip. Also disclosed is a method that uses the on-chip usable life depletion meter. In the method, the remaining usable life of an IC chip, once known, is used either as the basis for allowing re-use of the IC chip (e.g., for a non-critical application and when the remaining usable life is sufficient) or as the basis for preventing re-use of the IC chip (e.g., for a critical application or when the remaining usable life is insufficient).
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jeanne P. Bickford, Nazmul Habib, Baozhen Li, Tad J. Wilder
  • Patent number: 9791495
    Abstract: Unique systems, methods, techniques and apparatuses of fault location in DC power distribution systems are disclosed. One exemplary embodiment is a DC power distribution system comprising at least one DC power distribution network and at least two protective devices operatively coupled to the DC power distribution network. Each protective device is structured to sense one or more electrical characteristics associated with the DC power distribution network and to controllably interrupt current through the DC power distribution line. A control system is structured to determine the location of a high impedance fault between two of the protective devices using one or more electrical characteristics sensed by the two protective devices to calculate the inductance and resistance of the portion of the DC power distribution line between one of the protective devices and the high impedance fault.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: October 17, 2017
    Assignee: ABB Schweiz AG
    Inventors: Li Qi, Xianyong Feng
  • Patent number: 9766966
    Abstract: Systems and methods are provided for optimizing operation of an integrated circuit. In one implementation, a system is provided for optimizing operation of an integrated circuit by adjusting an operational parameter of the integrated circuit based on a reference count stored in non-volatile memory fabricated on the integrated circuit. In another implementation, a method is provided for optimizing operation of an integrated circuit by generating, during operation of the integrated circuit, a first oscillator count of an oscillator, comparing the first oscillator count with at least one reference count stored on the integrated circuit, and activating, a control circuit to adjust an operational parameter of the integrated circuit based on a result of the comparison.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 19, 2017
    Assignee: Marvell International Ltd.
    Inventor: Neal C. Jaarsma
  • Patent number: 9728509
    Abstract: Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: August 8, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Anthony K. Stamper, Edward C. Cooney, III, Laurie M. Krywanczyk
  • Patent number: 9720043
    Abstract: A method of testing a fuse in apparatus for monitoring electrical insulation surrounding first and second electrical conductors in a cable, the fuse being connected to the conductors, comprises: applying an electrical signal, with respect to a reference, to the fuse from a source; obtaining a value for the resistance of the insulation with respect to the reference; determining if the resistance value is greater than a fuse test resistance threshold and, if it is, causing the application of the signal to cease; and monitoring the decay of the signal to determine if the time for it to decay below a set value exceeds a set time limit, indicative of the fuse being satisfactory, or is less than the limit indicative of the fuse being blown.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 1, 2017
    Assignee: GE Oil & Gas UK Limited
    Inventors: Timothy Adam Boxshall, Julian Jefferis
  • Patent number: 9696920
    Abstract: A memory device includes a memory component that store data. The memory device also includes a processor that receives a signal indicating that the memory component is coupled to the processor and retrieves information from the memory component. The information may include one or more algorithms capable of being performed by the memory component. The processor may then receive one or more packets associated with one or more data operations regarding the memory component. The processor may then perform the one or more data operations by using the memory component to employ the one or more algorithms.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: July 4, 2017
    Assignee: Micron Technology, Inc.
    Inventor: J. Thomas Pawlowski
  • Patent number: 9690927
    Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: June 27, 2017
    Assignee: International Business Machines Corporation
    Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
  • Patent number: 9627393
    Abstract: A NAND flash memory has word lines in a memory array area and contact pads and lead lines in a word line hookup area, each of the word lines connected to a corresponding contact pad by a lead line. The word lines in the memory array area have a first height and low-profile areas of lead lines in the word line hookup area have a second height that is less than the first height.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 18, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Hideki Hara
  • Patent number: 9625811
    Abstract: An object provided with a particular alignment arrangement for use in aligning the object and a further object with respect to each other is disclosed. The alignment arrangement includes a first fine alignment mark in the form of a substantially regular grating, and a second coarse alignment mark located in the same area as the first alignment mark.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: April 18, 2017
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Sander Frederik Wuister, Arie Jeffrey Den Boef, Yvonne Wendela Kruijt-Stegeman
  • Patent number: 9598784
    Abstract: A contact element (25) (electroformed product) is produced by electroforming. The contact element (25) has a surface on which an insulating film (28) having been formed by use of a dry film resist or the like is provided. In a process of producing the contact element (25), the insulating film (28) is provided after a step of producing the contact element 25. This makes it possible to provide electroformed components configured so that respective electroformed products (contact terminals) are arranged at narrow pitches while maintaining electrical insulation of the electroformed products from each other.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: March 21, 2017
    Assignee: OMRON Corporation
    Inventors: Yoshinobu Hemmi, Takahiro Sakai, Hideaki Ozaki, Hirotada Teranishi
  • Patent number: 9532461
    Abstract: A first alignment mark is given to a substrate, and a second alignment mark is given to a mask. The mask forms an electronic circuit pattern on the substrate. A control unit performs alignment of the mask and the substrate based on the first and second alignment marks. The second alignment mark is formed to surround the first alignment mark. The second alignment mark has a step pattern therein.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: December 27, 2016
    Assignee: TDK CORPORATION
    Inventors: Naozumi Ishikawa, Fumio Watanabe, Hiroshi Kamiyama
  • Patent number: 9497862
    Abstract: The present invention relates a packaging structure including: a carrier board and a cementing layer on the surface of the carrier board; chips and passive devices having functional side thereof attached to the cementing layer; and a sealing material layer for packaging and curing, the sealing material being formed on the carrier board on the side attached to the chips and the passive devices. The present invention integrates chips and passive devices and then packages the chips and the passive devices together, and is therefore a packaged product having not single-chip functionality but integrated-system functionality. The present invention is highly integrated, reduces interfering factors such as system-internal electric resistance and inductance, and accommodates growing demand for lighter, thinner, shorter, and smaller semiconductor packaging.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: November 15, 2016
    Assignee: Nantong Fujitsu Microelectronics Co., Ltd.
    Inventors: Lei Shi, Yujuan Tao, Guohua Gao, Guoji Yang, Honglei Li, Haijun Shen
  • Patent number: 9430685
    Abstract: Apparatus, systems, and methods are provided to generate markings on the side of a substrate. The markings represent information. In an embodiment, the information provided in the markings may be used to collect information during an assembly process.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: August 30, 2016
    Assignee: Intel Corporation
    Inventors: Sergei Voronov, Rose Mulligan, Sarita Evans
  • Patent number: 9385040
    Abstract: A method of manufacturing a semiconductor device includes providing a wafer, grinding a backside of the wafer, disposing a backside film on the backside of the wafer, cutting the wafer to singulate a plurality of dies from the wafer, and forming a mark on the backside film disposed on each of the plurality of dies by a laser operation.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: July 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsai-Tsung Tsai, Wen-Hsiung Lu, Yu-Peng Tsai, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9350330
    Abstract: A physical unclonable function is provided 100, comprising a plurality of bus-keepers 110, each bus-keeper of the plurality of bus-keepers 110 being configured to settle into one of at least two different stable states upon power-up, the particular stable state into which a particular bus-keeper of the plurality of bus-keepers settles being dependent at least in part upon the at least partially random physical characteristics of the particular bus-keeper, and a reading circuit 120 for reading the plurality of stable states into which the plurality of bus-keepers settled after a power-up, the plurality of bus-keepers being read-only.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: May 24, 2016
    Assignee: INTRINSIC ID B.V.
    Inventors: Petrus Wijnandus Simons, Erik Van Der Sluis
  • Patent number: 9324660
    Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: April 26, 2016
    Assignee: STMicroelectronics, Inc.
    Inventors: John H. Zhang, Walter Kleemeier, Paul Ferreira, Ronald K. Sampson
  • Patent number: 9262819
    Abstract: Methods of the present disclosure can include a method for estimating a spatial characteristic of an integrated circuit (IC), the method comprising: calculating a correlation between a dimension of a photoresist layer and exposure to a scanning electron microscope (SEM) for at least one reference IC pattern in the photoresist layer, the correlation providing a relationship between the dimension of the photoresist and the spatial characteristic, wherein the calculating is based on: an SEM image of the at least one reference IC pattern produced from reducing the dimension of the photoresist layer with the SEM from an initial value to a reduced value, the initial value of the dimension, and the reduced value of the dimension; and estimating the spatial characteristic of a target IC based on the correlation.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: February 16, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Taher E. Kagalwala, Narender Rana, Yunlin Zhang
  • Patent number: 9229058
    Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: January 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dale Ohmart, Balamurugan Subramanian, Renato Heracleo Orduna Leano, Sonny Evangelista Dipasupil, Ronald Jay V. Peralta
  • Patent number: 9041162
    Abstract: A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Giuseppe Miccoli, Bhaskaran Jayachandran, Friedrich Steffen, Alfred Vater
  • Patent number: 9029986
    Abstract: Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-1). PL-1 and part of the semiconductor layer are etched to form a device mesa. A second passivation layer (PL-2) is formed over PL-1 and exposed edges of the mesa. Vias are etched through PL-1 and PL-2 to the semiconductor layer where source, drain and gate are to be formed. Conductors are applied in the vias for ohmic contacts for the source-drain and a Schottky contact for the gate. Interconnections over the edges of the mesa couple other circuit elements. PL-1 avoids adverse surface states near the gate and PL-2 insulates edges of the mesa from overlying interconnections to avoid leakage currents. An opaque alignment mark is desirably formed at the same time as the device to facilitate alignment when using transparent semiconductors.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, Haldane S. Henry
  • Patent number: 9030032
    Abstract: Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Kitahara, Hiroshi Koguma
  • Patent number: 9024457
    Abstract: A method for manufacturing a semiconductor device includes a first photolithography step of forming a first device pattern corresponding to a first pattern, and a plurality of alignment marks corresponding to a plurality of marks, upon a step of exposing the entire device region in one shot using a first mask including the first pattern and the plurality of marks, and a second photolithography step of, after the first photolithography step, forming second device patterns respectively corresponding to second patterns in a plurality of divided regions which form the device region, upon steps of individually exposing the plurality of divided regions using second masks each including the second pattern corresponding thereto.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: May 5, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Taikan Kanou
  • Patent number: 8994196
    Abstract: A semiconductor device includes a backing plate, a semiconductor wafer, and integrated devices. The semiconductor wafer includes a plurality of semiconductor die having edges oriented along a reference line, a front surface facing the backing plate, and a backside surface. The backside surface is formed opposite the front surface and includes linear grind marks oriented along the reference line and diagonal with respect to the edges of the plurality of semiconductor die. The linear grind marks are formed by a linear motion of an abrasive surface, such as by a cylinder or wheel having an abrasive surface, and in one embodiment are oriented at 45 degrees with respect to the reference line. The linear grind marks increase a strength of the plurality of semiconductor die to resist cracking. Integrated devices are formed on the front surface of the semiconductor wafer.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SungYoon Lee, JungHoon Shin, BoHan Yoon
  • Patent number: 8987840
    Abstract: Sensor packages and methods for making a sensor device package for side mounting on a circuit board. A sensor device(s) in a mechanical layer of silicon is sandwiched between first and second layers of glass to create a wafer. A first via(s) is created in the first or second layers to expose a predefined area of the mechanical layer of silicon. A second via(s) is created in the first or second layers. The least one second via has a depth dimension that is less than a depth dimension of the first via. A metallic trace is applied between the exposed area on the mechanical layer and a portion of the second via. The wafer is sliced such that the second via is separated into two sections, thereby creating a sensor die. The sensor die is then electrically and mechanically bonded to a circuit board at the sliced second via.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: March 24, 2015
    Assignee: Honeywell International Inc.
    Inventor: Michael Foster
  • Patent number: 8987009
    Abstract: A method for tracking an interposer die of a stacked silicon interconnect technology (SSIT) product includes forming a plurality of dummy components on the interposer die, and modifying one or more of the plurality of dummy components on the interposer die to form a unique identifier for the interposer die. An apparatus for a stacked silicon interconnect technology (SSIT) product includes an interposer die, and a plurality of dummy components at the interposer die. One or more of the plurality of dummy components is modifiable to form a unique identifier for the interposer die.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Xilinx, Inc.
    Inventors: Cinti X. Chen, Myongseob Kim, Xiao-Yu Li, Mohsen H. Mardi
  • Patent number: 8963313
    Abstract: Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 24, 2015
    Assignee: Raytheon Company
    Inventors: Sankerlingam Rajendran, Monte R. Sanchez, Susan M. Eshelman, Douglas R. Gentry, Thomas A. Hanft
  • Patent number: 8957457
    Abstract: A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: February 17, 2015
    Assignee: STMicroelectronics SA
    Inventors: Richard Fournel, Pierre Dautriche
  • Patent number: 8957512
    Abstract: An embodiment of an interposer is disclosed. For this embodiment of the interposer, a first circuit portion is created responsive to a first printing region. A second circuit portion is created responsive to a second printing region. The interposer has at least one of: (a) a length dimension greater than a maximum reticle length dimension, and (b) a width dimension greater than a maximum reticle width dimension.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: February 17, 2015
    Assignee: Xilinx, Inc.
    Inventor: Toshiyuki Hisamura
  • Patent number: 8956947
    Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N?-type layer formed on an N+-type substrate. This trench is used to leave voids after the formation of a P?-type epitaxial film on the N?-type layer. Then, the voids formed in the N?-type layer can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: February 17, 2015
    Assignees: Sumco Corporation, Denso Corporation
    Inventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Nobuhiro Tsuji, Toshiyuki Morishita
  • Patent number: 8957504
    Abstract: An integrated structure with a silicon-through via includes a substrate, a through-silicon via penetrating the substrate, a conductive protective structure surrounding the through-silicon via and a first and a second conductive dummy patterns with different shapes disposed between the through-silicon via and the conductive protective structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: IP Enval Consultant Inc.
    Inventors: Huang Chao-Yuan, Ho Yueh-Feng, Yang Ming-Sheng, Chen Hwi-Huang
  • Patent number: 8956946
    Abstract: Methods for forming RX pads having gate alignment marks configured to enable noise reduction between layers while resulting in little or no non-uniformity of CMP processes for the IC, and the resulting devices, are disclosed. Embodiments include: providing, on a substrate, a RX pad having a SPM with a SPM horizontal and vertical positions at horizontal and vertical midpoints, respectively, of the first RX pad; providing a second RX pad abutting the first RX pad and a first STI pad abutting the second RX pad, each having a vertical midpoint at the SPM vertical position; forming a first gate alignment mark on the second RX pad and having vertical endpoints horizontally aligned with vertical endpoints of the second RX pad; and forming a second gate alignment mark on the first STI pad and having vertical endpoints horizontally aligned with vertical endpoints of the first STI pad.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 17, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ming Hao Tang, Michael Hsieh, Frank Kahlenberg
  • Patent number: 8952454
    Abstract: An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: February 10, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Shimizu, Junichi Yamashita, Takuichiro Shitomi
  • Patent number: 8952497
    Abstract: A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines includes a metal-feature containing scribe line comprising metal features therein, and a metal-feature free scribe line parallel to, and adjoining, the metal-feature containing scribe line. A second plurality of scribe lines is between the columns of the plurality of chips.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: U-Ting Chen, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Jeng-Shyan Lin, Shuang-Ji Tsai
  • Patent number: 8928121
    Abstract: The present invention relates to a method for thermal stress reduction on a wafer, comprising the steps of providing a patterned wafer with saw lanes between adjacent dies, forming thin holes within the silicon substrate, which holes create a dotted groove in the saw lanes, and wherein no second layer on an opposing side of the wafer is formed, a patterned wafer obtained by said method. The forming of the holes is preferably combined with other processing steps or another step to avoid additional operations and manipulations prior to, or after standard wafer processing, and it therefore optimizes fabrication quality and costs. Preferably the holes within the silicon substrate having a depth of more than 3 to 50 ?m, preferably from 5-40 ?m, like 20 ?m.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: January 6, 2015
    Assignee: NXP B.V.
    Inventor: Alain Cousin
  • Patent number: 8916874
    Abstract: Sacrificial optical test structures are constructed upon a wafer of pre-cleaved optical chips for testing the optical functions of the pre-cleaved optical chips. The sacrificial optical structures are disabled upon the cleaving the optical chips from the wafer and the cleaved optical chips can be used for their desired end functions. The test structures may remain on the cleaved optical chips or they may be discarded.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: December 23, 2014
    Assignee: Oclaro Technology Limited
    Inventors: Neil David Whitbread, Lloyd Nicholas Langley, Andrew Cannon Carter
  • Patent number: 8916416
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: December 23, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Glenn Omandam, Yaojian Lin, Hin Hwa Goh
  • Patent number: 8901756
    Abstract: Embodiments of the present invention include a substrate package, a method for multi-chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 2, 2014
    Assignee: Spansion LLC
    Inventors: Sally Foong, Seshasayee Gaddamraja, Teoh Lai Beng, Lai Nguk Chin, Suthakavatin Aungkul