Marks Applied To Semiconductor Devices Or Parts, E.g., Registration Marks, Test Patterns, Alignment Structures, Wafer Maps (epo) Patents (Class 257/E23.179)
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Patent number: 8445907Abstract: The semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area. The peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device.Type: GrantFiled: December 8, 2010Date of Patent: May 21, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-Hyun Han
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Publication number: 20130119382Abstract: A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the contact without removing the protective layer over the test pad. With the protective layer still on the test pad, a conductive layer may be plated onto the contact without plating it onto the test pad. After the contact has been plated, the protective layer over the contact may be removed.Type: ApplicationFiled: November 16, 2011Publication date: May 16, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Fu Kao, Cheng-Lin Huang, Jing-Cheng Lin
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Patent number: 8440569Abstract: Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first pattern and remains within narrow a space defined by the first pattern; and removing the first pattern from the substrate. In one embodiment, the first pattern can comprise sacrificial material, which can include, for example, polysilicon material. The deposition can comprise physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition or other deposition techniques.Type: GrantFiled: December 7, 2007Date of Patent: May 14, 2013Assignee: Cadence Design Systems, Inc.Inventors: Milind Weling, Abdurrahman Sezginer
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Reprogrammable circuit board with alignment-insensitive support for multiple component contact types
Patent number: 8436454Abstract: The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.Type: GrantFiled: February 23, 2012Date of Patent: May 7, 2013Inventor: Richard Norman -
Patent number: 8435865Abstract: A method of manufacturing a super-junction semiconductor device facilitates suppressing the shape change caused in the alignment mark in the upper epitaxial layer transferred from the alignment mark in the lower epitaxial layer to be small enough to detect the transferred alignment mark with a few additional steps, even if the epitaxial layer growth rate is high. Alignment mark groups, each formed of trenches including parallel linear planar patterns and used in any of the multiple epitaxial layer growth cycles, are formed collectively on a scribe line between semiconductor chip sections; and the mesa region width between the trenches in each alignment mark group indicated by the distance between the single-headed arrows, facing opposite to each other and drawn in alignment mark groups is set to be one fourth of the designed total epitaxial layer thickness at the end of each epitaxial layer growth cycle or longer.Type: GrantFiled: May 18, 2011Date of Patent: May 7, 2013Assignee: Fuji Electric Co., Ltd.Inventor: Naoko Kodama
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Patent number: 8435868Abstract: With a general wafer level package process, in order to prevent corrosion of an aluminum type pad electrode in a scribe region in a plating process, the pad electrode is covered with a pad protective resin film at the same layer as an organic type protective film in a product region. However, this makes it impossible to perform the probe test on the pad electrode in the scribe region after rewiring formation. The present invention provides a method for manufacturing a semiconductor integrated circuit device of a wafer level package system. The organic type protective films in the chip regions and the scribe region are mutually combined to form an integral film pattern. In a pelletization step, the surface layer portion including the organic type protective film at the central part of the scribe region is first removed by laser grooving, to form a large-width groove. Then, a dicing processing of the central part in this groove results in separation into the chip regions.Type: GrantFiled: December 30, 2009Date of Patent: May 7, 2013Assignee: Renesas Electronics CorporationInventors: Hisao Shigihara, Hiromi Shigihara, Akira Yajima
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Publication number: 20130107259Abstract: An overlay target for use in imaging based metrology is disclosed. The overlay target includes a plurality of target structures including three or more target structures, each target structure including a set of two or more pattern elements, wherein the target structures are configured to provide metrology information pertaining to different pitches, different coverage ratios, and linearity. Pattern elements may be separated from adjacent pattern elements by non-uniform distance; pattern elements may have non-uniform width; or pattern elements may be designed to demonstrate a specific offset as compared to pattern elements in a different layer.Type: ApplicationFiled: April 13, 2012Publication date: May 2, 2013Applicant: KLA-Tencor CorporationInventors: Dongsub Choi, David Tien
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Publication number: 20130106000Abstract: An alignment accuracy (AA) mark is described, including N (N?3) pattern sets defined by N exposure steps respectively. The N exposure steps are performed also to a device area disposed on a wafer together with the AA mark. The i-th (i=1, 2 . . . N?1) pattern set surrounds the (i+1)-th pattern set. Each pattern set includes a 1st set of x-directional linear patterns, a 2nd set of x-directional linear patterns arranged opposite to the 1st set of x-directional linear patterns in the y-direction, a 1st set of y-directional linear patterns, and a 2nd set of y-directional linear patterns arranged opposite to the 1st set of y-directional linear patterns in the x-direction, wherein each set of x- or y-directional linear patterns include at least three separate parallel linear patterns.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kai-Lin Chuang, Wen-Liang Huang, Chia-Hung Lin, Chun-Chi Yu
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Publication number: 20130099235Abstract: A semiconductor wafer includes a plurality of semiconductor chips having bonding pads; and a connection wiring line coupling the plurality of semiconductor chips such that a test signal, which is inputted through bonding pads of an arbitrary semiconductor chip among the plurality of semiconductor chips, is transmitted to bonding pads of other semiconductor chips among the plurality of semiconductor chips.Type: ApplicationFiled: February 7, 2012Publication date: April 25, 2013Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Kwon Whan HAN
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Patent number: 8426987Abstract: A misalignment detection device comprising a substrate, at least one integrated circuit (IC), and at least one detection unit is disclosed. The substrate comprises a first positioning pad and a second positioning pad adjacent to the first positioning pad. The integrated circuit is disposed on the substrate and comprises a first positioning bump and a second positioning bump adjacent to the first positioning bump. The first and second positioning bumps substantially correspond to the first and second positioning pads, respectively. The at least one detection unit is electrically coupled to the substrate, wherein the detection unit outputs a fault signal in response to a positioning shift occurring between the first and second positioning pads and the first and second positioning bumps.Type: GrantFiled: February 5, 2010Date of Patent: April 23, 2013Assignee: Au Optronics Corp.Inventors: Chun-Yu Lee, Shih-Ping Chou, Chien-Liang Chen, Wen-Hung Lai
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Patent number: 8426946Abstract: In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein, a first wiring electrode and a second wiring electrode extend to the inside of a interposed groove part from a first device region and a second device region respectively, and are separated from each other. In the laminated semiconductor substrate, a through hole which the first wiring electrode appears is formed. The laminated semiconductor substrate has a through electrode. The through electrode is contact with all of the first wiring electrodes appearing in the through hole. The laminated semiconductor substrate has a plurality of laminated chip regions.Type: GrantFiled: June 28, 2010Date of Patent: April 23, 2013Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
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Patent number: 8426857Abstract: A method for producing a semiconductor device comprising a process step of forming a device configuration pattern in a device formation region in a chip formation region on a film side of a semiconductor wafer having the film for forming a pattern, and forming inspection patterns in a plurality of inspection regions in the chip formation region, and an inspection step, wherein the inspection patterns have a repeat pattern and a uniform pattern formed in a first inspection region in the plurality of inspection regions, the inspection step has at least a pattern inspection step including a first inspection to measure a parameter of the repeat pattern, by using an optical measurement method capable of measuring a three-dimensional pattern shape, and a second inspection to measure a film thickness of the uniform pattern by using an optical measurement method capable of measuring the film thickness.Type: GrantFiled: May 11, 2009Date of Patent: April 23, 2013Assignee: Sharp Kabushiki KaishaInventor: Noritaka Kamikubo
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Publication number: 20130093455Abstract: The disclosure describes a novel method and apparatus for testing TSVs in a single die or TSV connections in a stack of die.Type: ApplicationFiled: October 11, 2012Publication date: April 18, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: TEXAS INSTRUMENTS INCORPORATED
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Publication number: 20130092937Abstract: A display device according to an exemplary embodiment of the present invention includes a display portion including a plurality of display pixels displaying an image and a dummy portion including a plurality of dummy pixels formed in a periphery region of the display portion. An electrostatic test element group (TEG) may be formed in at least one of the dummy pixels.Type: ApplicationFiled: March 27, 2012Publication date: April 18, 2013Inventors: Jae-Seob Lee, Chang-Yong Jeong, Yong-Hwan Park, Kyung-Mi Kwon
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Patent number: 8420410Abstract: A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure.Type: GrantFiled: July 7, 2010Date of Patent: April 16, 2013Assignee: QUALCOMM IncorporatedInventors: Michael Laisne, Xiangdong Pan, Foua Vang, Prayag B. Patel, Donald D. Lyons, Martin Villafana
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Publication number: 20130087891Abstract: Disclosed is a method of fabricating a semiconductor chip. The method includes forming a silicon layer; forming a first layer formed on the silicon layer and including a first seal ring surrounding a first chip area and a second seal ring surrounding a second chip area; and forming a second layer formed on the first layer and including a metal interconnection connecting one of the first and second chip areas and an external terminal.Type: ApplicationFiled: October 9, 2012Publication date: April 11, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: SAMSUNG ELECTRONICS CO., LTD.
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Publication number: 20130088255Abstract: A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.Type: ApplicationFiled: October 7, 2011Publication date: April 11, 2013Inventors: PERRY H. PELLEY, Kevin J. Hess, Michael B. McShane
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Publication number: 20130087934Abstract: A method for manufacturing a substrate for a display device comprises forming a first pattern within an active region of the substrate and at the same time forming a first overlay pattern at corner regions of the active region; and forming a second pattern within the active region of the substrate and at the same time forming a second overlay pattern at corner regions of the active region, wherein the first overlay pattern includes gradations arranged in a predetermined direction, and the second overlay pattern includes gradations arranged in the predetermined direction to face the gradations of the first overlay pattern.Type: ApplicationFiled: October 3, 2012Publication date: April 11, 2013Applicant: LG Display Co., Ltd.Inventor: LG Display Co., Ltd.
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Patent number: 8415813Abstract: A semiconductor wafer includes multiple dies and a die identification region adjacent to or on each die. The die identification region can include a wafer indicator and a pattern of die locations representing die locations on the wafer. A die identification marker is provided in each pattern of die locations in the die identification region specifying a location of a respective die on the wafer.Type: GrantFiled: June 15, 2011Date of Patent: April 9, 2013Assignee: Truesense Imaging, Inc.Inventors: Shen Wang, Robert P. Fabinski, James E. Doran, Laurel J. Pace, Eric J. Meisenzahl
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Patent number: 8415260Abstract: A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip.Type: GrantFiled: April 8, 2010Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Albert J. Banach, Timothy H. Daubenspeck, Wolfgang Sauter
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Patent number: 8415770Abstract: Apparatus and methods for uniform metal plating onto a semiconductor wafer, such as GaAs wafer, are disclosed. One such apparatus can include an anode and a showerhead body. The anode can include an anode post and a showerhead anode plate. The showerhead anode plate can include holes sized to dispense a particular plating solution, such as plating solution that includes gold, onto a wafer. The showerhead body can be coupled to the anode post and the showerhead anode plate. The showerhead body can be configured to create a seal sufficient to substantially prevent a reduction of pressure in the plating solution flowing from the anode post to holes of the showerhead anode plate.Type: GrantFiled: May 2, 2012Date of Patent: April 9, 2013Assignee: Skyworks Solutions, Inc.Inventors: Jens A. Riege, Heather L. Knoedler, Shiban K. Tiku
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Publication number: 20130082408Abstract: A method for producing semiconductor device includes: performing first, second and third exposures of a photoresist film formed on a semiconductor wafer via a mask; wherein: first, second and third shot regions respectively defined by the first, second and third exposures are aligned in a first direction; the mask has a shot region including a peripheral scribe region having a first and second side crossing the first direction; the photoresist film is of positive type, a first pattern is formed as a light shielding pattern disposed on the first side, and a second pattern is formed as a light transmitting region disposed on the second side; the first and second exposures are performed in such a manner that the first and second patterns do not overlap each other; and the second and third exposures are performed in such a manner that the first and second patterns overlap each other.Type: ApplicationFiled: August 10, 2012Publication date: April 4, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: MITSUFUMI NAOE
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Publication number: 20130075726Abstract: The semiconductor wafer for a silicon-on-insulator integrated circuit comprises an insulating region located between a first semiconductor substrate intended to receive the integrated circuit and a second semiconductor substrate containing at least one buried layer comprising at least one metal silicide.Type: ApplicationFiled: September 14, 2012Publication date: March 28, 2013Applicant: STMICROELECTRONICS (ROUSSET) SASInventor: Pascal Fornara
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Publication number: 20130075938Abstract: A photolithography alignment mark and a mask and semiconductor wafer containing said mark are described. The alignment mark comprises: a plurality of first alignment lines arranged parallel with each other in a first direction; a plurality of second alignment lines arranged parallel with each other in a second direction perpendicular to the first direction, and wherein each of the plurality of first alignment lines is composed of a predetermined number of first fine alignment lines uniformly spaced from each other, and each of the plurality of second alignment lines is composed of a predetermined number of second fine alignment lines uniformly spaced from each other. Alignment marks can be located in non-circuit pattern regions of the mask and on a plurality of layers in mark regions on the wafer.Type: ApplicationFiled: December 16, 2011Publication date: March 28, 2013Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: XIAOSONG YANG, Yibo Yan, Tzu Hsuan Lu
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Publication number: 20130075869Abstract: A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Applicant: Infineon Technologies AGInventors: Gunther Mackh, Gerhard Leschik, Adolf Koller, Harald Seidl
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Publication number: 20130069205Abstract: A semiconductor wafer and a method which are capable of reducing chippings or cracks generated during the die sawing process. The semiconductor wafer comprises a plurality of dies formed on the semiconductor wafer in row and column directions and separated from each other by scribe lane areas, and a passivation layer formed on the plurality of dies and the scribe lane areas, wherein a groove structure is formed in the passivation layer. The groove structure includes grooves formed along the scribe lane areas, and corners of the passivation layer at intersections of the grooves being removed.Type: ApplicationFiled: December 14, 2011Publication date: March 21, 2013Applicant: Semiconductor Manufacturing International (Beijing) CorporationInventor: XIANJIE NING
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Publication number: 20130069063Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate having a test pad with element pads; forming a conductive layer over the test pad, the conductive layer having element layers directly on the element pads; and mounting an integrated circuit over the substrate.Type: ApplicationFiled: September 21, 2011Publication date: March 21, 2013Inventors: Bao Xusheng, Rui Huang
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Publication number: 20130069206Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.Type: ApplicationFiled: September 14, 2012Publication date: March 21, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazutaka Yoshizawa, Taiji Ema, Takuya Moriki
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Publication number: 20130062604Abstract: A photodetector includes a semiconductor substrate having an irradiation zone configured to generate charge carriers having opposite charge carrier types in response to an irradiation of the semiconductor substrate. The photodetector further includes an inversion zone generator configured to operate in at least two operating states to generate different inversion zones within the substrate, wherein a first inversion zone generated in a first operating state differs from a second inversion zone generated in a second operating state, and wherein the first inversion zone and the second inversion zone have different extensions in the semiconductor substrate. A corresponding method for manufacturing a photodetector and a method for determining a spectral characteristic of an irradiation are also described.Type: ApplicationFiled: September 14, 2011Publication date: March 14, 2013Applicant: Infineon Technologies AGInventor: Thoralf Kautzsch
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Publication number: 20130063202Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.Type: ApplicationFiled: September 13, 2012Publication date: March 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yan Zun Li, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
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Patent number: 8395218Abstract: The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may extend in a second direction substantially perpendicular to the first direction. The gate electrode may have a height in a third direction substantially perpendicular to the first and second directions and may partially surround the nanowire channel. The insulation layer pattern may be formed between and around the source/drain layers on the semiconductor substrate and may cover the nanowire channel and a portion of the gate electrode. Thus, a size of the gate electrode may be reduced, and/or a gate induced drain leakage (GIDL) and/or a gate leakage current may be reduced.Type: GrantFiled: August 19, 2010Date of Patent: March 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Dae Suk, Dong-Won Kim, Kyoung-Hwan Yeo
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Publication number: 20130056857Abstract: A manufacturing method for a device chip having a substrate, a device formed on the front side of the substrate, and chip identification information marked inside the substrate includes preparing a device wafer having a base wafer and a plurality of devices formed on the front side of the base wafer so as to be partitioned by division lines, next applying a laser beam having a transmission wavelength to the device wafer from the back side thereof in the condition where the focal point of the laser beam is set inside the base wafer at the positions respectively corresponding to the devices, thereby forming a plurality of modified layer marks as the chip identification information inside the base wafer at the positions respectively corresponding to the devices, and finally dividing the device wafer along the division lines to obtain a plurality of device chips.Type: ApplicationFiled: September 6, 2012Publication date: March 7, 2013Applicant: DISCO CORPORATIONInventor: Koichi KONDO
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Publication number: 20130056886Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.Type: ApplicationFiled: November 2, 2012Publication date: March 7, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Taiwan Semiconductor Manufacturing Company, L
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Patent number: 8389384Abstract: An object to be processed 1 comprising a substrate 4 and a plurality of functional devices 15 formed on a front face 3 of the substrate 4 is irradiated with laser light L while locating a converging point P within the substrate 4, so as to form at least one row of a divided modified region 72, at least one row of a quality modified region 71 positioned between the divided modified region 72 and the front face 3 of the substrate 4, and at least one row of an HC modified region 73 positioned between the divided modified region 72 and a rear face 21 of the substrate 4 for one line to cut 5. Here, in a direction along the line to cut, a forming density of the divided modified region 72 is made lower than that of the quality modified region 71 and that of the HC modified region 73.Type: GrantFiled: December 26, 2006Date of Patent: March 5, 2013Assignee: Hamamatsu Photonics K.K.Inventors: Takeshi Sakamoto, Kenichi Muramatsu
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Publication number: 20130048980Abstract: An integrated circuit includes a seal ring structure disposed around a circuit that is disposed over a substrate. A first pad is electrically coupled with the seal ring structure. A leakage current test structure is disposed adjacent to the seal ring structure. A second pad electrically coupled with the leakage current test structure, wherein the leakage current test structure is configured to provide a leakage current test between the seal ring structure and the leakage current test structure.Type: ApplicationFiled: August 26, 2011Publication date: February 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ying YANG, Hsien-Wei CHEN
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Publication number: 20130048982Abstract: A passive bond pad condition sense structure may be configured to be electrically stimulated and tested for detecting an anomalous or altered electrical characteristic caused by stress or aging of the bond pad capacitively coupled to it. The related bond pad condition testing or monitoring system may include relatively simple stimulating and sensing circuits that may be wholly embedded in the integrated circuit device.Type: ApplicationFiled: August 30, 2012Publication date: February 28, 2013Applicant: STMicroelectronics S.r.I.Inventors: Davide Giuseppe Patti, Manuela Larosa
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Patent number: 8386801Abstract: A group of devices are fabricated based on a common design, each device having a corresponding plurality of measurable characteristics that is unique in the group to that device, each device having a measurement module for measuring the measurable characteristics. Authentication of one of the group of devices is enabled by selective measurement of one or more of the plurality of measurable characteristics of the device.Type: GrantFiled: March 3, 2011Date of Patent: February 26, 2013Assignee: Massachusetts Institute of TechnologyInventors: Srinivas Devadas, Blaise Gassend
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Publication number: 20130043566Abstract: A semiconductor device includes a substrate having a circuit formation region, an interlayer insulating film formed on the substrate, a first seal ring formed in the interlayer insulating film to surround the circuit formation region, a first protective film formed on the interlayer insulating film in the circuit formation region and on the first seal ring, and a second protective film formed on the first protective film and inside relative to the first seal ring. The first protective film has a first surface contacting the second protective film, a second surface located directly on the first seal ring, and a third surface connecting the first surface and the second surface together, and an end of the second protective film is located inside relative to the third surface.Type: ApplicationFiled: October 23, 2012Publication date: February 21, 2013Applicant: Panasonic CorporationInventor: Panasonic Corporation
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Publication number: 20130043470Abstract: The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.Type: ApplicationFiled: August 21, 2011Publication date: February 21, 2013Inventors: Tse-Yao Huang, Yi-Nan Chen, Hsien-Wen Liu
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Publication number: 20130043565Abstract: A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.Type: ApplicationFiled: October 22, 2012Publication date: February 21, 2013Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventor: GLOBALFOUNDRIES Singapore Pte. Ltd.
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Patent number: 8377800Abstract: Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.Type: GrantFiled: April 23, 2012Date of Patent: February 19, 2013Assignee: Infineon Technologies AGInventors: Sajan Marokkey, Chandrasekhar Sarma, Alois Gutmann
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Patent number: 8378494Abstract: A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.Type: GrantFiled: June 16, 2011Date of Patent: February 19, 2013Assignee: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
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Patent number: 8378460Abstract: Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.Type: GrantFiled: December 24, 2010Date of Patent: February 19, 2013Assignee: National Semiconductor CorporationInventors: Peter J. Hopper, Peter Johnson, Peter Smeys, William French
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Publication number: 20130037916Abstract: A break pattern of a silicon wafer includes a line to be cut which is set in the silicon wafer assuming a surface as a (110) face in a surface direction of a first (111) face perpendicular to the (110) face; and through holes which are provided in a plurality of rows on the line to be cut, wherein each of the through holes has a first (111) face, a second (111) face which intersects the first (111) face, and a third (111) face which intersects the second (111) face and the first (111) face, an intersecting point with end edges of the second (111) face and the third (111) face is assumed as a point closest to the adjacent through holes.Type: ApplicationFiled: August 9, 2012Publication date: February 14, 2013Applicant: SEIKO EPSON CORPORATIONInventor: Isamu TOGASHI
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Publication number: 20130037968Abstract: A semiconductor apparatus includes a semiconductor substrate having a main surface, a multilayer structure circuit formed over the main surface of the semiconductor substrate, a protective wall formed in the same layer as an uppermost layer of the multilayer structure circuit so as to surround the multilayer structure circuit in plan view, and an alignment mark formed in the same layer as the uppermost layer. The alignment mark is formed so as to contact at least part of the protective wall.Type: ApplicationFiled: July 19, 2012Publication date: February 14, 2013Inventor: Masahiro ISHIDA
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Publication number: 20130037802Abstract: Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.Type: ApplicationFiled: August 8, 2011Publication date: February 14, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Luke G. England, Paul A. Silvestri, Michel Koopmans
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Patent number: 8373288Abstract: An alignment mark formed by using a first mask used in forming a same memory cell pattern on a substrate and formed together with the memory cell pattern includes: a first pattern for position detection used for alignment in forming a first wiring pattern; and a first irregular reflection prevention mark that suppresses, when a position detection signal is irradiated as alignment in forming a second wiring pattern further on an upper layer side than the first wiring pattern, irregular reflection of a position detection signal from a second pattern for position detection formed further in a lower layer than the first pattern for position detection.Type: GrantFiled: March 18, 2010Date of Patent: February 12, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Hiroomi Nakajima
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Publication number: 20130032800Abstract: A semiconductor device includes a circuit board including a ground portion, and a semiconductor package disposed on the circuit board. The semiconductor package includes an external connecting pad and an exposed pad. The exposed pad and the ground portion are electrically connected at a first surface of the exposed pad. A semiconductor chip is disposed on a second surface of the exposed pad and electrically connected to the external connecting pad. The first surface of the exposed pad is located external to the semiconductor package, and the second surface of the exposed pad is located within the semiconductor package. A test pad is disposed on the semiconductor chip and is electrically connected to the exposed pad.Type: ApplicationFiled: December 12, 2011Publication date: February 7, 2013Inventors: Dong-Hyun Yeo, Yong-Bum Kim, Byung-Kil Jeon, Bong-Ju Jun
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Publication number: 20130032712Abstract: A method comprises providing a semiconductor substrate having a first layer and a second layer above the first layer. The first layer haw a plurality of first patterns, vias or contacts. The second layer has second patterns corresponding to the first patterns, vias or contacts. The second patterns have a plurality of in-plane offsets relative to the corresponding first patterns, vias or contacts. A scanning electron microscope is used to measure line edge roughness (LER) values of the second patterns. An overlay error is calculated between the first and second layers based on the measured LER values.Type: ApplicationFiled: August 2, 2011Publication date: February 7, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yuan SHIH, I-Hsiung HUANG, Heng-Hsin LIU
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Publication number: 20130032956Abstract: A method for manufacturing a semiconductor device includes a first photolithography step of forming a first device pattern corresponding to a first pattern, and a plurality of alignment marks corresponding to a plurality of marks, upon a step of exposing the entire device region in one shot using a first mask including the first pattern and the plurality of marks, and a second photolithography step of, after the first photolithography step, forming second device patterns respectively corresponding to second patterns in a plurality of divided regions which form the device region, upon steps of individually exposing the plurality of divided regions using second masks each including the second pattern corresponding thereto.Type: ApplicationFiled: July 25, 2012Publication date: February 7, 2013Applicant: CANON KABUSHIKI KAISHAInventor: Taikan Kanou