Characterized By Material Or Arrangement Of Seals Between Parts, E.g., Between Cap And Base Of Container Or Between Leads And Walls Of Container (epo) Patents (Class 257/E23.193)
  • Patent number: 12080614
    Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; a semiconductor die mounted on the top surface of the substrate; and a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die. The lid comprises an annular lid base and a cover plate removably installed on the annular lid base. The semiconductor package can be uncovered by removing the cover plate and a forced cooling module can be installed in place of the cover plate.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: September 3, 2024
    Assignee: MEDIATEK INC.
    Inventors: Shih-Chao Chiu, Chi-Yuan Chen, Wen-Sung Hsu, Ya-Jui Hsieh, Yao-Pang Hsu, Wen-Chun Huang
  • Patent number: 11772960
    Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
  • Patent number: 11229122
    Abstract: Techniques are described for an electronic device to increase the exposure of the externally bound components, such as sensors and antennas, which performance is improved by such exposure. A flexible printed circuit board (PCB) is affixed to the top surface of the device's enclosure, thereby placing the flexible PCB outside of the enclosure. Externally bound component(s) are integrated onto the flexible PCB, which has multiple layers, including an interface layer and a spacer layer. The spacer layer has an aperture extending through the layer at the locations corresponding to the externally bound components, thereby exposing the externally bound component's surface.
    Type: Grant
    Filed: October 3, 2020
    Date of Patent: January 18, 2022
    Assignee: PHYSIGHT SOLUTIONS LLC
    Inventor: Davit Shaghgamyan
  • Patent number: 11205670
    Abstract: An image sensor assembly and a method for assembling. The assembly includes: a ceramic package; at least one wall raised from the ceramic package, one of the walls for dividing a first surface region and a second surface region of the ceramic package; a frame supported by the ceramic package; a first set of fiducial markers and a second set of fiducial markers visible on the frame; a first die for placement onto the first surface region, the first die including an image sensor and respective fiducial markers for alignment with the first set of fiducial markers; a second die for placement onto the second surface region, the second die including an image sensor and respective fiducial markers for alignment with the second set of fiducial markers; and at least one optical filter each associated with one of the dice and supported by at least one of the walls.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: December 21, 2021
    Assignee: Teledyne Digital Imaging, Inc.
    Inventor: Anton Petrus Maria Van Arendonk
  • Patent number: 10916565
    Abstract: The present disclosure provides a field of display technologies, and in particular, to a LTPS substrate and a fabricating method thereof, a thin film transistor thereof, an array substrate thereof, and a display device thereof. The LTPS substrate, able to be used for the fabrication of a thin film transistor, includes a light shielding layer, the light shielding layer mainly composed of amorphous silicon doped with a lanthanide element. The present disclosure mainly employs an amorphous silicon film layer doped with the lanthanide element as the light shielding layer of the LTPS substrate, which not only ensures the light shielding efficiency but also reduces the production process, and further prevents the occurrence of the H explosion problem due to H exuding during the ELA process.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: February 9, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Haixu Li, Zhanfeng Cao, Qi Yao, Dapeng Xue, Da Lu
  • Patent number: 10892201
    Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: January 12, 2021
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Malta) Ltd
    Inventors: Jerome Lopez, Roseanne Duca
  • Patent number: 10105544
    Abstract: The present disclosure provides medical devices and methods of manufacturing medical devices wherein the medical device includes at least one bonding surface that has been roughed by laser etching to increase its surface area and improve its bonding characteristics. In many embodiments, the medical device is an implantable medical device that includes a hermetically sealed metallic housing that is bonded to a prefabricated non-metallic header. The hermetically sealed metallic housing includes at least one surface that has been subjected to a laser etching and roughening process to increase its surface area and improve its bonding characteristics. The laser etched surface may include spots created in a non-overlapping honeycomb-type pattern that may additionally include a series of spikes protruding therefrom to further improve bonding characteristics.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 23, 2018
    Assignee: PACESETTER, INC.
    Inventors: Asghar Dadashian, Avi Bilu, Ofer Rosenzweig, Sean Portune
  • Patent number: 9975757
    Abstract: A microelectromechanical systems (MEMS) structure with a cavity hermetically sealed using a mask layer is provided. A capping substrate is arranged over a MEMS substrate, which includes a movable element. The capping substrate includes the cavity arranged over and opening to the movable element, and includes a seal opening in fluid communication with the cavity. The mask layer is arranged over the capping substrate. The mask layer overhangs the seal opening and laterally surrounds a mask opening arranged over the seal opening. A seal layer is arranged over the mask layer and the mask opening. The seal layer is configured to hermetically seal the cavity. A method for manufacturing the MEMS structure is also provided.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lee-Chuan Tseng, Chung-Yen Chou, Shih-Chang Liu, Yuan-Chih Hsieh
  • Patent number: 9912115
    Abstract: The invention relates to methods of producing a cap substrate, to methods of producing a packaged radiation-emitting device at the wafer level, and to a radiation-emitting device. By producing a cap substrate, providing a device substrate in the form of a wafer including a multitude of radiation-emitting devices, arranging the substrates one above the other such that the substrates are bonded along an intermediate bonding frame, and dicing the packaged radiation-emitting devices, improved packaged radiation-emitting devices are provided which are advantageously arranged within a cavity free from organics and can be examined, still at the wafer level, in terms of their functionalities in a simplified manner prior to being diced.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 6, 2018
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Wolfgang Reinert, Hans Joachim Quenzer
  • Patent number: 9831392
    Abstract: To provide a cover glass for light emitting diode package, which is capable of preventing deterioration in transmittance characteristics during use for a long period of time, and a light emitting device. The cover glass for light emitting diode package has a basic composition comprising, by mass % as calculated as oxides, from 55 to 80% of SiO2, from 0.5 to 15% of Al2O3, from 5 to 25% of B2O3, from 0 to 7% of Li2O, from 0 to 15% of Na2O, from 0 to 10% of K2O (provided Li2O+Na2O+K2O=from 2 to 20%), from 0 to 0.1% of SnO2 and from 0.001 to 0.1% of Fe2O3, it does not substantially contain As2O3, Sb2O3 and PbO, and it has an average thermal expansion coefficient of from 45 to 70×10?7/° C. in a temperature range of from 0 to 300° C.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: November 28, 2017
    Assignee: Asahi Glass Company, Limited
    Inventors: Makoto Shiratori, Yoko Mitsui, Satoshi Takeda
  • Patent number: 9725301
    Abstract: A structure and a formation method of a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a cap substrate and a MEMS substrate bonded with the cap substrate. The MEMS substrate includes a first movable element and a second movable element. The MEMS device also includes a first enclosed space surrounded by the MEMS substrate and the cap substrate, and the first movable element is in the first enclosed space. The MEMS device further includes a second enclosed space surrounded by the MEMS substrate and the cap substrate, and the second movable element is in the second enclosed space. In addition, the MEMS device includes a pressure-changing layer in the first enclosed space.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng, Shang-Ying Tsai, Chin-Wei Liang
  • Patent number: 9567204
    Abstract: A method for manufacturing a microelectromechanical systems (MEMS) device is provided. According to the method, a semiconductor structure is provided. The semiconductor structure includes an integrated circuit (IC) substrate, a dielectric layer arranged over the IC substrate, and a MEMS substrate arranged over the IC substrate and the dielectric layer to define a cavity between the MEMS substrate and the IC substrate. The MEMS substrate includes a MEMS hole in fluid communication with the cavity and extending through the MEMS substrate. A sealing layer is formed over or lining the MEMS hole to hermetically seal the cavity with a reference pressure while the semiconductor structure is arranged within a vacuum having the reference pressure. The semiconductor structure resulting from application of the method is also provided.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ming Hung, Shao-Chi Yu, Hsiang-Fu Chen, Wen-Chuan Tai, Hsin-Ting Huang
  • Patent number: 9567210
    Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package having two MEMS devices with different pressures, and an associated method of formation. In some embodiments, the (MEMS) package includes a device substrate and a cap substrate bonded together. The bonded substrate comprises a first cavity corresponding to a first MEMS device having a first pressure and a second cavity corresponding to a second MEMS device having a different second pressure. The second cavity comprises a major volume and a vent hole connected by a lateral channel disposed between the device substrate and the cap substrate and the vent hole is hermetically sealed by a sealing structure.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Kuei-Sung Chang
  • Patent number: 9018755
    Abstract: A joint structure includes: a ceramic member; a metallized layer formed on a surface of the ceramic member; and a metal member joined to the metallized layer via a brazing material. The metal member includes a base part erected on the metallized layer, and an extended part extended from the base part to define a predetermined gap with respect to the metallized layer. The base part includes an end joined to the metallized layer by a brazing material layer including the brazing material, and a side joined to the metallized layer around the base part by a fillet including the brazing material formed on the metallized layer around the base part. The extended part defines a recess at a position facing the metallized layer on which the fillet is formed.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: April 28, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Sadahiro Nishimura, Naoki Tsuda
  • Patent number: 9018753
    Abstract: A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics Pte Ltd
    Inventor: Wing Shenq Wong
  • Patent number: 9006875
    Abstract: Provided is a semiconductor device and method of fabricating the semiconductor memory device. The semiconductor device may be formed by forming a first welding groove along outside edges of one case of a pair of upper and lower cases, forming a first welding protrusion along outside edges of the other case, the first welding protrusion being formed to correspond to the first welding groove and having a volume larger than a volume of the first welding groove. The method may further include inserting the first welding protrusion into the first welding groove to enclose a memory module in an inner accommodating space of the upper and lower cases, melting the first welding protrusion so that a first portion of the first welding protrusion fills the first welding groove and a second portion of the first welding protrusion fills a space between welding portions of the upper case and the lower case, and solidifying the first and second portions of the first welding protrusion.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronis Co., Ltd.
    Inventor: Jae-Hwan Han
  • Patent number: 8963291
    Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Patent number: 8952497
    Abstract: A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines includes a metal-feature containing scribe line comprising metal features therein, and a metal-feature free scribe line parallel to, and adjoining, the metal-feature containing scribe line. A second plurality of scribe lines is between the columns of the plurality of chips.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: U-Ting Chen, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Jeng-Shyan Lin, Shuang-Ji Tsai
  • Patent number: 8927996
    Abstract: An organic light emitting diode (OLED) display device, including a first substrate and a second substrate facing each other, a sealant arranged between the first and second substrates to adhere the first and second substrates together, a plurality of interconnections arranged on one of the first and second substrates and a plurality of cladding parts covering at least a portion of each of the plurality of interconnections at a location that corresponds to the sealant, each of the cladding parts including a material having a higher melting point than that of the interconnections. By including the cladding parts, a short circuit between the interconnections caused by heat applied to the sealant can be prevented, and safety and reliability of the OLED display device can be improved.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: January 6, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Yeon Cho, Zail Lhee, Tae-Wook Kang, Hun Kim, Mi-Sook Suh, Hyun-Chol Bang
  • Patent number: 8890309
    Abstract: A circuit module includes a circuit substrate, at least one mount component, sealing bodies, and a shield. The circuit substrate includes a mount surface. The mount component is mounted on the mount surface. The sealing body is formed on the mount surface, covers the mount component and has a first sealing body section having a first thickness and a second sealing body section having a second thickness larger than the first thickness. The shield covers the sealing body and has a first shield section formed on the first sealing body section and having a third thickness and a second shield section formed on the second sealing body section and having a fourth thickness smaller than the third thickness. The sum of the fourth thickness and the second thickness equals to the sum of the first thickness and the third thickness.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: November 18, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Eiji Mugiya, Takehiko Kai, Masaya Shimamura, Tetsuo Saji, Hiroshi Nakamura
  • Patent number: 8829668
    Abstract: There is provided an electronic device in which the deterioration of the device is prevented and an aperture ratio is improved without using a black mask and without increasing the number of masks. In the electronic device, a first electrode (113) is disposed on another layer different from the layer on which a gate wiring (145) is disposed as a gate electrode, and a semiconductor layer of a pixel switching TFT is superimposed on the gate wiring (145) so as to be shielded from a light. Thus, the deterioration of the TFT is suppressed, and a high aperture ratio is realized.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kazutaka Inukai
  • Patent number: 8829667
    Abstract: An electronic apparatus includes a main board, a semiconductor package, an upper conductive EMI shield member, and a lower conductive EMI shield member. The main board includes a first ground pad. The semiconductor package is spaced apart from and electrically connected to the main board. The upper conductive EMI shield member covers a top surface and a sidewall of the semiconductor package. The lower conductive EMI shield member surrounds a space between the main board and the semiconductor package, and is electrically connected to the upper conductive EMI shield member and the first ground pad.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Woo Park, Wang-Ju Lee, In-Sang Song
  • Patent number: 8802475
    Abstract: A method of fabricating a microelectronic device structure including increased thermal dissipation capabilities. The structure including a three-dimensional (3D) integrated chip assembly that is flip chip bonded to a substrate. The chip assembly including a device substrate including an active device disposed thereon. A cap layer is physically bonded to the device substrate to at least partially define a hermetic seal about the active device. The microelectronic device structure provides a plurality of heat dissipation paths therethrough to dissipate heat generated therein.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: August 12, 2014
    Assignee: General Electric Company
    Inventors: Kaustubh Ravindra Nagarkar, Christopher Fred Keimel
  • Patent number: 8803301
    Abstract: A semiconductor package may include a substrate, a semiconductor chip disposed on the substrate, a communication terminal and a static electricity inducing terminal connected to a ground. The package may include a first sealant that comprises a voltage sensitive material and that covers the semiconductor chip and a static electricity blocking layer that provides a conductive pathway from the first sealant to only the static electric inducing terminal. The static electricity blocking layer may prevent the communication terminal from being electrically connected to the first sealant. If a buildup of charge is applied to the device, the first sealant may become polarized and/or conductive. The extra voltage may travel through the first sealant to the static electricity inducing terminal via an opening in the static electricity blocking layer. The semiconductor chip and the communication terminal may not be affected by the extra charge.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyong-soon Cho, Seung-kon Mok, Kwan-jai Lee, Jae-min Jung
  • Patent number: 8729695
    Abstract: In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 20, 2014
    Assignees: Agency for Science, Technology and Research, Seiko Instruments, Inc.
    Inventors: Chirayarikathu Veedu Sankarapillai Premachandran, Rakesh Kumar, Nagarajan Ranganathan, Won Kyoung Choi, Ebin Liao, Yasuyuki Mitsuoka, Hiroshi Takahashi, Ryuta Mitsusue
  • Patent number: 8716852
    Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
  • Patent number: 8698258
    Abstract: A microelectronic device structure including increased thermal dissipation capabilities. The structure including a three-dimensional (3D) integrated chip assembly that is flip chip bonded to a substrate. The chip assembly including a device substrate including an active device disposed thereon. A cap layer is physically bonded to the device substrate to at least partially define a hermetic seal about the active device. The microelectronic device structure provides a plurality of heat dissipation paths therethrough to dissipate heat generated therein.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: April 15, 2014
    Assignee: General Electric Company
    Inventors: Kaustubh Ravindra Nagarkar, Christopher Fred Keimel
  • Patent number: 8674498
    Abstract: An MEMS package is proposed, wherein a chip having MEMS structures on its top side is connected to a rigid covering plate and a frame structure, which comprises a polymer, to form a sandwich structure in such a way that a closed cavity which receives the MEMS structures is formed. Solderable or bondable electrical contact are arranged on the rear side of the chip or on the outer side of the covering plate which faces away from the chip, and are electrically conductively connected to at least one connection pad by means of an electrical connection structure.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: March 18, 2014
    Assignee: Epcos AG
    Inventors: Gregor Feiertag, Hans Krüger, Alexander Schmajew
  • Patent number: 8610224
    Abstract: In a MEMS element 500 where a MEMS structure 201 is hermetically sealed in a cavity 110 by a substrate 301 and laminated structure 120, interface sealing layers 101, 102 and 103 are provided between two layers that constitute the laminated structure 120, so as to prevent gas from breaking into the cavity 110 through the interface between two layers along the direction parallel to the surface of the substrate 301.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: December 17, 2013
    Assignees: Panasonic Corporation, IMEC
    Inventors: Yasuyuki Naito, Philippe Helin, Hendrikus Tilmans
  • Patent number: 8610156
    Abstract: Embodiments include a light emitting device package. The light emitting device package comprises a housing including a cavity; a light emitting device positioned in the cavity; a lead frame including a first section electrically connected to the light emitting device in the cavity, a second section, which penetrates the housing, extending from the first section and a third section, which is exposed to outside air, extending from the second section; and a metal layer positioned on an area defined by a distance which is distant from the housing in the second section of the lead frame.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: December 17, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Ki Bum Kim
  • Patent number: 8604599
    Abstract: A semiconductor housing is provided that includes a metal support and a semiconductor body, a bottom side thereof being connected to the metal support. The semiconductor body has metal surfaces that are connected to pins by bond wires and a plastic compound, which completely surrounds the bond wires and partially surrounds the semiconductor body. The plastic compound has an opening on the top side of the semiconductor body, and a barrier is formed on the top side of the semiconductor body. The barrier has a top area and a base area spaced from the edges of the semiconductor body and an internal clearance of the barrier determines a size of the opening. Whereby, a portion of the plastic compound has a height greater than the barrier, and a fixing layer is formed between the base area of the barrier and the top side of the semiconductor body.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: December 10, 2013
    Assignee: Micronas GmbH
    Inventors: Tobias Kolleth, Pascal Stumpf, Christian Joos
  • Patent number: 8592959
    Abstract: A semiconductor device includes a semiconductor element, a wiring board including a conductor portion formed on a first surface thereof on which the semiconductor element is mounted, the conductor portion being electrically connected to the semiconductor element, and a concave cap provided to seal the first surface of the wiring board, the concave cap being mounted through an adhesive on the first surface of the wiring board In the semiconductor device, a sidewall portion of the concave cap includes an inside surface facing toward the conductor portion of the wiring board, an outside surface positioned on an opposite side to the inside surface, and a bottom surface adhered onto the first surface of the wiring board. The sidewall portion of the concave cap is provided so that a thickness thereof becomes thinner at a portion extending from the outside surface to the bottom surface.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: November 26, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Tomoharu Fujii
  • Patent number: 8587107
    Abstract: A hermetically sealed integrated circuit package that includes a cavity housing a semiconductor die, whereby the cavity is pressurized during assembly and when formed. The invention prevents the stress on a package created when the package is subject to high temperatures at atmospheric pressure and then cooled from reducing the performance of the die at high voltages. By packaging a die at a high pressure, such as up to 50 PSIG, in an atmosphere with an inert gas, and providing a large pressure in the completed package, the dies are significantly less likely to arc at higher voltages, allowing the realization of single die packages operable up to at least 1200 volts. Moreover, the present invention is configured to employ brazed elements compatible with Silicon Carbide dies which can be processed at higher temperatures.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: November 19, 2013
    Assignee: Microsemi Corporation
    Inventor: Tracy Autry
  • Patent number: 8575752
    Abstract: A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen plasma. Tensile stress in a center layer of the film is reduced by increasing N2 gas flow to the nitrogen plasma, resulting in a Ti:N stoichiometry between 1:2.1 to 1:2.3. TiN films thicker than 40 nanometers without cracks are attained by the disclosed process.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: November 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Charles Herdt, Joseph W. Buckfeller
  • Patent number: 8575748
    Abstract: A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: November 5, 2013
    Assignee: Sandia Corporation
    Inventor: Anthony J. Farino
  • Patent number: 8546933
    Abstract: A semiconductor apparatus according to aspects of the invention can include a metal base; resin case having a bonding plane facing metal base; a coating groove formed in bonding plane and holding adhesive for bonding resin case to metal base at a predetermined position, with the top plane of the wall that forms coating groove being spaced apart from the plane which contains bonding plane such that an escape space is formed between the metal base and the resin case; the escape space receiving the excess amount of adhesive which has flowed out from the coating groove; and a receiver groove communicating to the escape space and receiving securely the excess amount of adhesive which the escape space has failed to receive. If an excess amount of adhesive too much for the receiver groove to receive is coated, the excess amount of adhesive can be received in a stopper groove.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: October 1, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Shin Soyano
  • Patent number: 8513056
    Abstract: Provided is a semiconductor device and method of fabricating the semiconductor memory device. The semiconductor device may be formed by forming a first welding groove along outside edges of one case of a pair of upper and lower cases, forming a first welding protrusion along outside edges of the other case, the first welding protrusion being formed to correspond to the first welding groove and having a volume larger than a volume of the first welding groove. The method may further include inserting the first welding protrusion into the first welding groove to enclose a memory module in an inner accommodating space of the upper and lower cases, melting the first welding protrusion so that a first portion of the first welding protrusion fills the first welding groove and a second portion of the first welding protrusion fills a space between welding portions of the upper case and the lower case, and solidifying the first and second portions of the first welding protrusion.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: August 20, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hwan Han
  • Patent number: 8508036
    Abstract: A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: August 13, 2013
    Assignee: Tessera, Inc.
    Inventors: Kenneth Allen Honer, Philip Damberg
  • Patent number: 8471382
    Abstract: A package includes: a metal wall disposed on a conductive base plate; a through-hole disposed in input/output portions of the metal wall; a lower layer feed through disposed on the conductive base plate; a wiring pattern disposed on the lower layer feed through; an upper layer feed through disposed on a part of the lower layer feed through and a part of the wiring pattern; and a terminal disposed on the wiring pattern, wherein a width of a part of the lower layer feed through and a width of the upper layer feed through are wider than a width of the through-hole, the lower layer feed through is adhered to a side surface of the metal wall, the upper layer feed through is adhered to the side surface of metal wall, and an air layer is formed between the wiring pattern and an internal wall of the through-hole.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: June 25, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 8395177
    Abstract: A package (1; 20) for protecting a device (2; 21) from ambient substances, the package comprising an enclosure surrounding the device (2; 21). The enclosure includes a multi-layer barrier (7; 24) and an internal substance binding member (14; 27) which is provided inside the enclosure to bind at least one of said ambient substances having penetrated the enclosure. The package (1; 20) further comprises an intermediate substance binding member (14; 29) which is provided between an inner (11a-b; 25) and an outer (16a-b; 28) barrier layer of the multi-layer barrier (7; 24) to bind a fraction of the substance having penetrated the outer barrier layer (16a-b; 28).
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: March 12, 2013
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Edward Willem Albert Young, Johannes Krijne
  • Patent number: 8390111
    Abstract: One embodiment of a micro-electronic device includes a substrate including micro-electronic components thereon, and a cover including a ring of sealing material secured to the substrate and a raised ring of material positioned opposite the cover from the ring of sealing material.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: March 5, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Kirby Sand
  • Patent number: 8334582
    Abstract: A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: December 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wei Chen, Shang-Yun Hou, Hao-Yi Tsai, Anbiarshy N. F. Wu, Yu-Wen Liu
  • Publication number: 20120292757
    Abstract: In various embodiments, a semiconductor component may include a semiconductor layer having a front side and a back side; at least one electronic element formed at least partially in the semiconductor layer; at least one via formed in the semiconductor layer and leading from the front side to the back side of the semiconductor layer; a front side metallization layer disposed over the front side of the semiconductor layer and electrically connecting the at least one electronic element to the at least one via; a cap disposed over the front side of the semiconductor layer and mechanically coupled to the semiconductor layer, the cap being configured as a front side carrier of the semiconductor component; a back side metallization layer disposed over the back side of the semiconductor layer and electrically connected to the at least one via.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 22, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Anton MAUDER, Gerald LACKNER, Oliver HAEBERLEN
  • Patent number: 8313970
    Abstract: Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 20, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Emmanuel P. Quevy, Pezhman Monadgemi, Roger T. Howe
  • Patent number: 8288835
    Abstract: Microshells including a perforated pre-sealing layer and an integrated getter layer are provided. The integrated getter layer may be disposed between other layers of a perforated pre-sealing layer. The perforated pre-sealing layer may include at least one perforation, and a sealing layer may be provided on the pre-sealing layer to close the perforation.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: October 16, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Emmanuel P. Quevy, Pezhman Monadgemi, Roger T. Howe
  • Patent number: 8288851
    Abstract: A system for hermetically sealing devices includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of a predetermined thickness, which includes a plurality of recessed regions arranged in a spatial manner as a second array and each of the recessed regions are bordered by a standoff region. The substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: October 16, 2012
    Assignee: Miradia Inc.
    Inventors: Xiao Yang, Dongmin Chen
  • Patent number: 8283769
    Abstract: A protective modular package cover has first and second fastening sections located at opposing first and second ends with one or more subassembly receiving sections disposed thereto and is configured to fasten the protective modular package cover to a core. Each fastening section has a foot surface located on a bottom surface of a fastening section and configured to make contact with the core, a mounting hole configured to receive a fastener, and a torque element. Each subassembly receiving section is configured to receive a subassembly and has a cross member formed along the underside of the protective modular package cover. Activation of the first torque element transfers a downward clamping force generated at the fastening element to a top surface of one or more subassemblies disposed in the one or more subassembly receiving sections via the cross member of each of the one or more subassembly receiving sections.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: October 9, 2012
    Assignee: STMicroelectronics, Inc.
    Inventors: Craig J. Rotay, John Ni, David Lam, David Lee DeWire, John W. Roman, Richard J. Ross
  • Patent number: 8273594
    Abstract: Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: September 25, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Emmanuel P. Quevy, Pezhman Monadgemi, Roger T. Howe
  • Patent number: 8268670
    Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: September 18, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazuhiro Tashiro, Keisuke Fukuda, Naohito Kohashi, Shigeyuki Maruyama
  • Patent number: 8232635
    Abstract: A hermetically sealed semiconductor package that includes a power semiconductor die having electrodes thereof electrically connected to the external surface mountable terminals of the package without the use of wirebonds.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: July 31, 2012
    Assignee: International Rectifier Corporation
    Inventor: Weidong Zhuang