Containers; Seals (epo) Patents (Class 257/E23.18)
  • Patent number: 11804479
    Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 31, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John J. Wuu, Milind S. Bhagavat, Brett P. Wilkerson, Rahul Agarwal
  • Patent number: 11791312
    Abstract: Monolithic microwave integrated circuits (MMICs) with backside interconnects for fanout-style packaging are disclosed. Fanout-style packaging, such as fanout wafer (FOWLP) or fanout panel-level packaging (FOPLP), facilitates a high density package for MMICs. However, the fanout-style packaging may produce undesired electromagnetic (EM) coupling between a MMIC die and metal features in a redistribution layer (RDL) of the FOW/PLP package and/or a next higher assembly (NHA). In an exemplary aspect, a circuit package according to this disclosure includes the MMIC die and an RDL. The MMIC includes a chip side with components which may undesirably couple to metal signal lines (e.g., package metal interconnects) in the RDL. The chip side of the MMIC is oriented away from the RDL to reduce such EM coupling.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: October 17, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Andrew Arthur Ketterson, Christo Pavel Bojkov
  • Patent number: 11756844
    Abstract: A semiconductor device includes a substrate; a die attached over the substrate; and a metal enclosure continuously encircling a space and extending vertically between the substrate and the die.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: September 12, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street, Mark E. Tuttle
  • Patent number: 11658079
    Abstract: Embodiments described herein are directed to a temporary interconnect for use in testing one or more devices (e.g., one or more dies, inductors, capacitors, etc.) formed in semiconductor package. In one scenario, a temporary interconnect acts an electrical bridge that electrically couples a contact pad on a surface of a substrate and the test pad. Coupling the contact pad and the test pad to each other enables the device(s) coupled the contact pad to be tested. Following testing, the temporary interconnect can be removed or severed so that an electrical break is formed in the conductive path between test pad and the contact pad.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Hyoung Il Kim, Yi Xu, Florence Pon
  • Patent number: 11631650
    Abstract: An approach for transferring solder to a laminate structure in IC (integrated circuit) packaging is disclosed. The approach comprises of a device and method of applying the device. The device comprises of a substrate, a laser ablation layer and solder layer. The device is made by depositing a laser ablation layer onto a glass/silicon substrate and plenty of solder powder/solder pillar is further deposited onto the laser ablation layer. The laminate packaging substrate includes pads with a pad surface finishing layer made from gold. The solder layer of the device is bonded to the laminate packaging substrate. Once bonded, using laser to irradiate the laser ablation layer, the substrate is removed from the laminate.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: April 18, 2023
    Assignee: International Business Machines Corporation
    Inventor: Katsuyuki Sakuma
  • Patent number: 11610814
    Abstract: The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: March 21, 2023
    Assignee: Qorvo US, Inc.
    Inventor: Deep C. Dumka
  • Patent number: 11598742
    Abstract: Described examples include a sensor device having at least one conductive elongated first pillar positioned on a central pad of a first conductor layer over a semiconductor substrate, the first pillar extending in a first direction normal to a plane of a surface of the first conductor layer. Conductive elongated second pillars are positioned in normal orientation on a second conductor layer over the semiconductor substrate, the conductive elongated second pillars at locations coincident to via openings in the first conductor layer. The second conductor layer is parallel to and spaced from the first conductor layer by at least an insulator layer, the conductive elongated second pillars extending in the first direction through a respective one of the via openings. The at least one conductive elongated first pillar is spaced from surrounding conductive elongated second pillars by gaps.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 7, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Enis Tuncer, Vikas Gupta
  • Patent number: 11600687
    Abstract: An electronic device package includes: a substrate including a central region, and a first side region and a second side region at opposite sides of the central region; a first component in the first side region or the second side region, the first component having a first height above a surface of the substrate; a second component in the central region, the second component having a second height above the surface of the substrate that is lower than the first height; a reinforcement member in the central region and overlapping the second component, the reinforcement member having a third height above the surface of the substrate that is lower than the first height and higher than the second height; and an encapsulation member covering the first component and the second component.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: March 7, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung Hwan Cheong, Sung Bae Park, Myung Joon Yoon, Kyu Min Han
  • Patent number: 11456270
    Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a die and a first adhesive layer; a surface of the substrate is provided with an insulation layer; the die is arranged on a surface of the insulation layer via the first adhesive layer; the insulation layer is provided with at least one slot; a position of the at least one slot corresponds to at least a part of an edge of the first adhesive layer; a second adhesive layer is arranged in the at least one slot; at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; and an elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: September 27, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Mingxing Zuo
  • Patent number: 11309275
    Abstract: A sensor package structure is provided and includes a substrate, a sensor chip disposed on the substrate, a padding layer disposed on the substrate, a plurality of wires, a support, and a light-permeable layer disposed on the support. A top side of the padding layer is coplanar with a top surface of the sensor chip, the support is disposed on the top side of the padding layer and the top surface of the sensor chip, and the wires are embedded in the support. Terminals at one end of the wires are connected to the top surface of the sensor chip, and terminals at the other end of the wires are connected to the top side of the padding layer, so that the sensor chip can be electrically coupled to the substrate through the wires and the padding layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 19, 2022
    Assignee: KINGPAK TECHNOLOGY INC.
    Inventor: Chung-Hsien Hsin
  • Patent number: 10005660
    Abstract: The present disclosure relates to a semiconductor package device. The semiconductor package device includes a carrier, a first Micro Electro Mechanical Systems (MEMS) and a first electronic component. The carrier has a first surface and a second surface opposite the first surface. The MEMS is disposed in the carrier. The first MEMS is exposed from the first surface of the carrier and is exposed from the second surface of the carrier. The first electronic component is disposed on the first surface of the carrier and is electrically connected to the first MEMS.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: June 26, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Kay Stefan Essig
  • Patent number: 9873610
    Abstract: A MEMS device is described. The device includes a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, a semiconductor substrate including a second bonding layer, and a cap including a third bonding layer, the cap coupled to the semiconductor substrate by bonding the second bonding layer to the third bonding layer. The first bonding layer includes silicon, the semiconductor substrate is electrically coupled to the MEMS substrate by bonding the first bonding layer to the second bonding layer, and the MEMS substrate is hermetically sealed between the cap and the semiconductor substrate.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Hsien Lin, Chia-Hua Chu, Li-Cheng Chu, Yuan-Chih Hsieh, Chun-Wen Cheng
  • Patent number: 8975105
    Abstract: Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: March 10, 2015
    Assignee: Raytheon Company
    Inventor: Cody B. Moody
  • Patent number: 8933539
    Abstract: An integrated circuit (IC) and a seal ring thereof are provided. The IC includes a first seal ring. The first seal ring is disposed in the IC. The first seal ring includes at least one stagger structure. The at least one stagger structure includes at least one stagger unit. The at least one stagger unit makes staggered connection with another neighboring stagger unit.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: January 13, 2015
    Assignee: VIA Telecom Co., Ltd.
    Inventors: Bing-Jye Kuo, Hong-Wen Lin, Yu-Jie Ji
  • Patent number: 8906744
    Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Meow Koon Eng, Yong Poo Chia, Suan Jeung Boon
  • Patent number: 8896113
    Abstract: According to one embodiment, the base plate includes first and a second faces that are opposed to each other; the second face has a contoured rear surface, and the first area is set in the center of the plate. There is a second area with via holes in the peripheral areas of the center part. Also, the thickness of the second area is less than the thickness of the first area.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eitaro Miyake
  • Patent number: 8890309
    Abstract: A circuit module includes a circuit substrate, at least one mount component, sealing bodies, and a shield. The circuit substrate includes a mount surface. The mount component is mounted on the mount surface. The sealing body is formed on the mount surface, covers the mount component and has a first sealing body section having a first thickness and a second sealing body section having a second thickness larger than the first thickness. The shield covers the sealing body and has a first shield section formed on the first sealing body section and having a third thickness and a second shield section formed on the second sealing body section and having a fourth thickness smaller than the third thickness. The sum of the fourth thickness and the second thickness equals to the sum of the first thickness and the third thickness.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: November 18, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Eiji Mugiya, Takehiko Kai, Masaya Shimamura, Tetsuo Saji, Hiroshi Nakamura
  • Patent number: 8884384
    Abstract: A semiconductor element of the electric circuit includes a semiconductor layer over a gate electrode. The semiconductor layer of the semiconductor element is formed of a layer including polycrystalline silicon which is obtained by crystallizing amorphous silicon by heat treatment or laser irradiation, over a substrate. The obtained layer including polycrystalline silicon is also used for a structure layer such as a movable electrode of a structure body. Therefore, the structure body and the electric circuit for controlling the structure body can be formed over one substrate. As a result, a micromachine can be miniaturized. Further, assembly and packaging are unnecessary, so that manufacturing cost can be reduced.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: November 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mayumi Yamaguchi, Konami Izumi
  • Patent number: 8872352
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8872347
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8872353
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8866289
    Abstract: A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 21, 2014
    Assignee: Silex Microsystems AB
    Inventors: Thorbjorn Ebefors, Edward Kalvesten, Niklas Svedin, Anders Eriksson
  • Patent number: 8853861
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 7, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8847403
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8847372
    Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: September 30, 2014
    Inventors: Robert Francis Darveaux, Michael Barrow, Miguel Angel Jimarez, Jae Dong Kim, Dae Keun Park, Ki Wook Lee, Ju Hoon Yoon
  • Patent number: 8841775
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 23, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8829681
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8803290
    Abstract: The amount of signal propagation and moisture penetration and corresponding reliability problems due to moisture penetration degradation in an IC can be reduced by fabricating two seal rings with non-adjacent gaps. In one embodiment, the same effect can be achieved by fabricating a wide seal ring with a channel having offset ingress and egress portions. Either of these embodiments can also have grounded seal ring segments which further reduce signal propagation.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: August 12, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Norman Frederick, Jr., Tom Myers
  • Patent number: 8791576
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8785231
    Abstract: A semiconductor device includes a sensor portion, a cap portion, and an ion-implanted layer. The sensor portion has a sensor structure at a surface portion of a surface. The cap portion has first and second surfaces opposite to each other and includes a through electrode. The surface of the sensor portion is joined to the first surface of the cap portion such that the sensor structure is sealed between the sensor portion and the cap portion. The ion-implanted layer is located on the second surface of the cap portion. The through electrode extends from the first surface to the second surface and is exposed through the ion-implanted layer.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: July 22, 2014
    Assignee: DENSO CORPORATION
    Inventors: Kazuhiko Sugiura, Tetsuo Fujii, Hisanori Yokura
  • Patent number: 8779570
    Abstract: A stackable integrated circuit package system including mounting an integrated circuit device over a package carrier, mounting a stiffener over the package carrier and mounting a mountable package carrier over the stiffener with a vertical gap between the integrated circuit device and the mountable package carrier.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: July 15, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Seong Bo Shim, TaeWoo Kang, Yong Hee Kang
  • Patent number: 8729695
    Abstract: In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 20, 2014
    Assignees: Agency for Science, Technology and Research, Seiko Instruments, Inc.
    Inventors: Chirayarikathu Veedu Sankarapillai Premachandran, Rakesh Kumar, Nagarajan Ranganathan, Won Kyoung Choi, Ebin Liao, Yasuyuki Mitsuoka, Hiroshi Takahashi, Ryuta Mitsusue
  • Patent number: 8728866
    Abstract: A method for manufacturing a semiconductor device comprises: forming a circuit pattern and a first metal film on a first major surface of a body wafer; forming a through-hole penetrating the body wafer from a second major surface of the body wafer and reaching the first metal film; forming a second metal film on a part of the second major surface of the body wafer, on an inner wall of the through-hole, and on the first metal film exposed in the through-hole; forming a recess on a first major surface of a lid wafer; forming a third metal film on the first major surface of the lid wafer including inside the recess of the lid wafer; with the recess facing the circuit pattern, and the first metal film contacting the third metal film, joining the lid wafer to the body wafer; and dicing the joined body wafer and lid wafer along the through-hole.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: May 20, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ko Kanaya, Yoshihiro Tsukahara, Shinsuke Watanabe
  • Patent number: 8729687
    Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: May 20, 2014
    Assignee: STATS ChipPac Ltd.
    Inventors: Hun Teak Lee, Tae Keun Lee, Soo Jung Park
  • Patent number: 8716852
    Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
  • Patent number: 8716850
    Abstract: An object is to realize a hermetically sealed package which ensures long-term airtightness inside the package by sealing using a substrate, or a sealing structure for reducing destruction caused by pressure from the outside. A frame of a semiconductor material is provided over a first substrate, which is bonded to a second substrate having a semiconductor element so that the semiconductor element is located inside the frame between the first substrate and the second substrate. The frame may be formed using, as frame members, two L-shaped semiconductor members in combination or four or more stick semiconductor members in combination.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: May 6, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideaki Kuwabara
  • Patent number: 8710638
    Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a first substrate; bonding a second substrate to the first substrate, the second substrate including a microelectromechanical system (MEMS) device; and bonding a third substrate to the first substrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ting-Hua Wu
  • Patent number: 8704361
    Abstract: A sealing glass, a sealing material, and a sealing material paste, which suppress metal deposition by reducing glass components (metal oxides) without decreasing the reactivity with and the adhesion to a semiconductor substrate. The sealing glass, contains a low temperature melting glass containing, by mass ratio: from 0.1 to 5% of at least one metal oxide selected from the group consisting of Fe, Mn, Cr, Co, Ni, Nb, Hf, W, Re, a rare earth element, and optionally Mo; and from 5 to 100 ppm by mass ratio of K2O, wherein the low temperature melting glass has a softening point of at most 430° C. The sealing material device, contains the sealing glass and an inorganic filler in an amount of from 0 to 40% by volume ratio. The sealing material paste contains a mixture of the sealing material and a vehicle.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 22, 2014
    Assignee: Asahi Glass Company, Limited
    Inventor: Hiroki Takahashi
  • Patent number: 8674498
    Abstract: An MEMS package is proposed, wherein a chip having MEMS structures on its top side is connected to a rigid covering plate and a frame structure, which comprises a polymer, to form a sandwich structure in such a way that a closed cavity which receives the MEMS structures is formed. Solderable or bondable electrical contact are arranged on the rear side of the chip or on the outer side of the covering plate which faces away from the chip, and are electrically conductively connected to at least one connection pad by means of an electrical connection structure.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: March 18, 2014
    Assignee: Epcos AG
    Inventors: Gregor Feiertag, Hans Krüger, Alexander Schmajew
  • Patent number: 8659019
    Abstract: At a semiconductor device, an integrated circuit including an optoelectronic conversion device is formed on a front face of a sensor chip. A rewiring layer, which leads from pad electrodes, and post electrodes, on the rewiring layer, are formed on the sensor chip. At least a portion of surroundings of the rewiring layer and the post electrodes is sealed with sealing resin, so as to be open above the integrated circuit face. A light-transmissive substrate is disposed over the sealed sensor chip. Penetrating electrodes, corresponding with positions of the post electrodes disposed on the sensor chip, are formed in the light-transmissive substrate, and external terminals such as solder balls or the like are formed so as to electrically connect with the penetrating electrodes.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: February 25, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Yoshinori Shizuno
  • Publication number: 20140035106
    Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 6, 2014
    Applicant: PLX TECHNOLOGY, INC.
    Inventors: Duc Anh VU, Jayalakshmana Kumar PRAGASAM, Vijay MEDURI, Seyed ATTARAN, Michael J. GRUBISICH, Syed AHMED, Aniket SINGH
  • Patent number: 8633049
    Abstract: A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: January 21, 2014
    Assignee: Invensense, Inc.
    Inventors: Steven S. Nasiri, Anthony F. Flannery, Jr.
  • Patent number: 8633595
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: January 21, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8610261
    Abstract: A power semiconductor device includes a power semiconductor module having cylindrical conductors which are joined to a wiring pattern so as to be substantially perpendicular to the wiring pattern and whose openings are exposed at a surface of transfer molding resin, and an insert case having a ceiling portion and peripheral walls, the ceiling portion being provided with external terminals that are fitted into, and passed through, the ceiling portion, the external terminals having outer-surface-side connecting portions at the outer surface side of the ceiling portion and inner-surface-side connecting portions at the inner surface side of the ceiling portion. The power semiconductor module is set within the insert case such that the inner-surface-side connecting portions of the external terminals are inserted into the cylindrical conductors.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: December 17, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiji Oka, Yoshiko Obiraki, Takeshi Oi
  • Publication number: 20130313700
    Abstract: A method (30) of forming a semiconductor package (20) entails applying (56) an adhesive (64) to a portion (66) of a bonding perimeter (50) of a base (22), with a section (68) of the perimeter (50) being without the adhesive (64). A lid (24) is placed on the base (22) so that a bonding perimeter (62) of the lid (24) abuts the bonding perimeter (50) of the base (22). The lid (24) includes a cavity (25) in which dies (38) mounted to the base (22) are located. A gap (70) is formed without the adhesive (64) at the section (68) between the base (22) and the lid (24). The structure vents from the gap (70) as air inside the cavity (25) expands during heat curing (72). Following heat curing (72), another adhesive (80) is dispensed in the section (68) to close the gap (70) and seal the cavity (25).
    Type: Application
    Filed: May 23, 2012
    Publication date: November 28, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Stephen R. Hooper, Philip H. Bowles
  • Patent number: 8575748
    Abstract: A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: November 5, 2013
    Assignee: Sandia Corporation
    Inventor: Anthony J. Farino
  • Patent number: 8569113
    Abstract: A method for producing a microfluid component includes: Producing a single polymer layer made of at least one plastic or a plastic composite and having a microfluid structure, fitting the polymer layer with at least one semiconductor element, and/or with at least one electronic component, and/or with an optical or optoelectronic component, sealing the microfluid structure.
    Type: Grant
    Filed: September 7, 2009
    Date of Patent: October 29, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Holger Reinecks, Johanna May
  • Patent number: 8558371
    Abstract: Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: JiSun Hong, Taeje Cho, Un-Byoung Kang, Hyuekjae Lee, Youngbok Kim, Hyung-sun Jang
  • Patent number: 8552544
    Abstract: A package structure includes first and second substrates, a sealant and a filler. The first substrate has a surface including an active region and a bonding region. The first substrate has a component in the active region and a pad in bonding region. The pad is electrically connected to the component. The sealant is disposed on the surface surrounding the active region. The sealant has a breach at a side of the active region. The second substrate is bonded to the first substrate via the sealant. The second substrate has a first opening corresponding to the pad, and a second opening corresponding to the breach. The filler fills the second opening, covers the breach such that the first substrate, the second substrate, the sealant and the filler together form a sealed space for accommodating the component.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: October 8, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Ching-Hong Chuang
  • Patent number: 8552559
    Abstract: A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: October 8, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou