Protection Against Mechanical Damage (epo) Patents (Class 257/E23.194)
  • Patent number: 9041220
    Abstract: A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: May 26, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Brian M. Henderson, Shiqun Gu
  • Patent number: 9018748
    Abstract: A housing for a power semiconductor, providing a compartment for installation of a power semiconductor, and including a first and a second terminal. The terminals are for connection of a power semiconductor installed in the compartment, and for leading current to and from the compartment. The housing includes a contact mechanism for bypassing the compartment, the contact mechanism including at least one movable contact arranged for electrically connecting the first and second terminal, the at least one movable contact being movable between a disconnected first position and a connected second position. The contact mechanism further includes a bypass actuator arranged inside the compartment and provided for transforming a pressure from an exploding semiconductor into motion, the bypass actuator is operatively connected to the movable contact and arranged to move the movable contact from the first to the second position when subjected to the pressure of an exploding semiconductor.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: April 28, 2015
    Assignee: ABB Technology AG
    Inventor: Mauro Monge
  • Patent number: 8994185
    Abstract: A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. A conductive micro via array is formed outside a footprint of the semiconductor die and over the semiconductor die and encapsulant. A first through-mold-hole (TMH) is formed including a step-through-hole structure through the encapsulant to expose the conductive micro via array. An insulating layer is formed over the semiconductor die and the encapsulant. A micro via array is formed through the insulating layer and outside the footprint of the semiconductor die. A conductive layer is formed over the insulating layer. A conductive ring is formed comprising the conductive micro via array. A second TMH is formed partially through the encapsulant to a recessed surface of the encapsulant. A third TMH is formed through the encapsulant and extending from the recessed surface of the encapsulant to the conductive micro via array.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen
  • Patent number: 8952497
    Abstract: A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines includes a metal-feature containing scribe line comprising metal features therein, and a metal-feature free scribe line parallel to, and adjoining, the metal-feature containing scribe line. A second plurality of scribe lines is between the columns of the plurality of chips.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: U-Ting Chen, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Jeng-Shyan Lin, Shuang-Ji Tsai
  • Patent number: 8912076
    Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: December 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Basab Chatterjee
  • Patent number: 8884390
    Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-I Cheng, Chih-Kang Chao, Volume Chien, Chi-Cherng Jeng, Pin Chia Su, Chih-Mu Huang
  • Patent number: 8877611
    Abstract: An apparatus that comprises a device on a substrate and a crack stop in the substrate. Methods of forming a device are also disclosed. The methods may include providing a device, such as a semiconductor device, on a substrate having a first thickness, reducing the thickness of the substrate to a second thickness, and providing a crack stop in the substrate. Reducing the thickness of the substrate may include mounting the substrate to a carrier substrate for support and then removing the carrier substrate. The crack stop may prevent a crack from reaching the device.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: November 4, 2014
    Assignee: Cree, Inc.
    Inventors: Van Allen Mieczkowski, Daniel James Namishia
  • Patent number: 8860215
    Abstract: A semiconductor device has a wiring substrate, a first semiconductor chip, a second semiconductor chip, and a sealing member. The second semiconductor chip has a chip-layered structure with a plurality of semiconductor chip components stacked in the height direction of the semiconductor device. The first semiconductor chip has an upper surface located at the same height from a surface of the wiring substrate as an upper surface of the second semiconductor chip.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: October 14, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Yumiko Miura
  • Patent number: 8859390
    Abstract: A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G Farooq, John A Griesemer, William F Landers, Ian D Melville, Thomas M Shaw, Huilong Zhu
  • Patent number: 8841753
    Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: September 23, 2014
    Assignee: Panasonic Corporation
    Inventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
  • Patent number: 8836084
    Abstract: A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Yu-Wen Liu, Hao-Yi Tsai
  • Patent number: 8810040
    Abstract: A wiring substrate includes an insulating layer having a first surface on which a projecting part is formed, and an electrode pad being formed on the projecting part and including a first electrode pad surface and a second electrode pad surface on a side opposite to the first electrode pad surface. The first electrode pad surface is exposed from the projecting part of the insulating layer. The second electrode pad surface is covered by the insulating layer. A cross-section of the projecting part is a tapered shape. One side of the cross-section toward the first electrode pad surface is narrower than another side of the cross-section toward the first surface of the insulating layer.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: August 19, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kentaro Kaneko, Kazuhiro Kobayashi
  • Patent number: 8791562
    Abstract: A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: July 29, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Chung-sun Lee, Jung-Hwan Kim, Yun-hyeok Im, Ji-hwan Hwang, Hyon-chol Kim, Kwang-chul Choi, Eun-kyoung Choi, Tae-hong Min
  • Patent number: 8786102
    Abstract: A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: July 22, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Masanori Yoshida, Fumitomo Watanabe
  • Patent number: 8786054
    Abstract: A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chyi Harn, Sophia Wang, Chun-Hung Lin, Hsien-Wei Chen, Ming-Yen Chiu
  • Patent number: 8779556
    Abstract: Devices and methods for pattern alignment are disclosed. In one embodiment, a semiconductor device includes a die including an integrated circuit region, an assembly isolation region around the integrated circuit region, and a seal ring region around the assembly isolation region. The device further includes a die alignment mark disposed within the seal ring region or the assembly isolation region.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 8779535
    Abstract: Integrated devices and methods for packaging the same can include an external housing, an internal housing positioned within the external housing, and an external cavity formed between the external housing and the internal housing. An integrated device die can be positioned within the external cavity in fluid communication with an internal cavity formed by the internal lid. An air way can extend through the external cavity to the internal cavity, and can further extend from the internal cavity to the external cavity. The air way can provide fluid communication between the package exterior and the integrated device die, while reducing contamination of the integrated device die.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: July 15, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Thomas M. Goida, Jicheng Yang
  • Patent number: 8759965
    Abstract: A protective modular package assembly with one or more subassemblies, each having a base element, a sidewall element coupled to the base element, and a semiconductor device disposed within and coupled to the sidewall element and the base element; a protective modular package cover having fastening sections located at opposing ends of the cover, torque elements disposed on the opposing ends and configured to fasten the cover to a core, and subassembly receiving sections disposed between the fastening sections with each subassembly receiving section operable to receive a subassembly and having a cross member along the underside of the cover; and an adhesive layer configured to affix subassemblies to respective subassembly receiving sections. The torque elements are configured to transfer a downward clamping force generated at the fastening elements to a top surface of the subassemblies via the cross member of each of the one or more subassembly receiving sections.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: June 24, 2014
    Assignees: STMicroelectronics, Inc., RJR Polymers, Inc.
    Inventors: Craig J. Rotay, John Ni, David Lam, David Lee DeWire, John W. Roman, Richard J. Ross
  • Patent number: 8742547
    Abstract: A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between the first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including a lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: June 3, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazutaka Yoshizawa, Taiji Ema
  • Patent number: 8703539
    Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsiun Lee, Kai-Chiang Wu
  • Patent number: 8669661
    Abstract: A device includes a dielectric layer, a metal line in the dielectric layer, and a via underlying and connected to the metal line. Two dummy metal patterns are adjacent to the metal line, and are aligned to a straight line. A dummy metal line interconnects the two dummy metal patterns. A width of the dummy metal line is smaller than lengths and widths of the two dummy metal patterns, wherein the width is measure in a direction perpendicular to the straight line. Bottoms of the two dummy metal patterns and the dummy metal line are substantially level with a bottom surface of the metal line.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsiang Yao, Ying-Wen Huang
  • Patent number: 8664747
    Abstract: A substrate for a light emitting diode (LED) can have one or more trenches formed therein so as to mitigate stress build up within the substrate due to mismatched thermal coefficients of expansion between the substrate and layers of material, e.g., semiconductor material, formed thereon. In this manner, the likelihood of damage to the substrate, such as cracking thereof, is substantially mitigated.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: March 4, 2014
    Assignee: Toshiba Techno Center Inc.
    Inventor: Jie Cui
  • Patent number: 8648421
    Abstract: An electrostatic discharge (ESD) device is described, including a gate line, a source region at a first side of the gate line, a comb-shaped drain region disposed at a second side of the gate line and having comb-teeth parts, a salicide layer on the source region and the drain region, and contact plugs on the salicide layer on the source region and the drain region. Each comb-teeth part has thereon, at a tip portion thereof, at least one of the contact plugs.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yung-Ju Wen, Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20140021616
    Abstract: A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.
    Type: Application
    Filed: July 19, 2012
    Publication date: January 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diego Anzola, Evan G. Colgan, Kevin K. Dezfulian, Daniel C. Edelstein, Mark C. H. Lamorey, Sampath Purushothaman, Thomas M. Shaw, Roy R. Yu
  • Patent number: 8610256
    Abstract: An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: December 17, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 8604599
    Abstract: A semiconductor housing is provided that includes a metal support and a semiconductor body, a bottom side thereof being connected to the metal support. The semiconductor body has metal surfaces that are connected to pins by bond wires and a plastic compound, which completely surrounds the bond wires and partially surrounds the semiconductor body. The plastic compound has an opening on the top side of the semiconductor body, and a barrier is formed on the top side of the semiconductor body. The barrier has a top area and a base area spaced from the edges of the semiconductor body and an internal clearance of the barrier determines a size of the opening. Whereby, a portion of the plastic compound has a height greater than the barrier, and a fixing layer is formed between the base area of the barrier and the top side of the semiconductor body.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: December 10, 2013
    Assignee: Micronas GmbH
    Inventors: Tobias Kolleth, Pascal Stumpf, Christian Joos
  • Patent number: 8597964
    Abstract: A method for manufacturing a plurality of holders each being for an LED package structure includes steps: providing a base, pluralities of through holes being defined in the base to divide the base into a plurality of basic units; etching the base to form a dam at an upper surface of each of the basic units of the base; forming a first electrical portion and a second electrical portion on each basic unit of the base, the first electrical portion and the second electrical portion being separated and insulated from each other by the dam; providing a plurality of reflective cups each on a corresponding basic unit of the base, each of the reflective cups surrounding the corresponding dam; and cutting the base into the plurality of basic units along the through holes to form the plurality of holders.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: December 3, 2013
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Chih-Hsun Ke, Ming-Ta Tsai, Chao-Hsiung Chang
  • Patent number: 8575763
    Abstract: A semiconductor device includes a first wiring hoard, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: November 5, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Masanori Yoshida, Fumitomo Watanabe
  • Patent number: 8541260
    Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a apace between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surfaces, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: September 24, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Robert Francis Darveaux, Michael Barrow, Miguel Angel Jimarez, Jae Dong Kim, Dae Keun Park, Ki Wook Lee, Ju Hoon Yoon
  • Publication number: 20130241049
    Abstract: Methods and apparatuses are disclosed for forming a post-passivation interconnect (PPI) guard ring over a circuit in a wafer forming a wafer level package (WLP). A circuit device comprises a guard ring and an active area. A passivation layer is formed on top of the circuit device over the guard ring and the active area, wherein the passivation layer contains a passivation contact connected to the guard ring. A first polymer layer is formed over the passivation layer. A PPI opening is formed within the first polymer layer or within the passivation layer over the passivation contact. A PPI guard ring is formed filling the PPI opening in touch with the passivation contact and extending on top of the first polymer layer or the passivation layer.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 19, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen
  • Patent number: 8492876
    Abstract: A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: July 23, 2013
    Assignee: Palo Alto Research Center Incorporated
    Inventors: William S. Wong, Brent S. Krusor, Robert A. Street
  • Patent number: 8481367
    Abstract: Provided is a method of manufacturing a circuit device in which a circuit element is resin-sealed with sealing resins formed integrally with each other. In the present invention, a resin sheet and a circuit board are housed in a cavity of a mold, and thereafter a first sealing resin formed of a tablet in melted form is injected into the cavity. At the time of injecting the first sealing resin, a second sealing resin formed of the resin sheet in melted form is not yet cured and is maintained in liquid form. Accordingly, the injected first sealing resin and the second sealing resin are mixed at the boundary therebetween, preventing the generation of a gap in the boundary portion and therefore preventing the deterioration of the moisture resistance and withstand voltage at the boundary portion.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 9, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Katsuyoshi Mino, Akira Iwabuchi, Ko Nishimura
  • Patent number: 8476748
    Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 2, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Robert Francis Darveaux, Michael Barrow, Miguel Angel Jimarez, Jae Dong Kim, Dae Keun Park, Ki Wook Lee, Ju Hoon Yoon
  • Patent number: 8461021
    Abstract: The present disclosure provides a method of fabricating a semiconductor device, the method including providing a substrate having a seal ring region and a circuit region, forming a first seal ring structure over the seal ring region, forming a second seal ring structure over the seal ring region and adjacent to the first seal ring structure, and forming a first passivation layer disposed over the first and second seal ring structures. A semiconductor device fabricated by such a method is also provided.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 11, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dun-Nian Yaung, Jen-Cheng Liu, Jen-Shyan Lin, Wen-De Wang, Shu-Ting Tsai
  • Patent number: 8455990
    Abstract: A barrier layer can be attached in a semiconductor package to one or more sensitive devices. The barrier layer can be used to obstruct tampering by a malicious agent attempting to access sensitive information on the sensitive device. The barrier layer can cause the sensitive device to become inoperable if physically tampered. Additional other aspects of the protective packaging provide protection against x-ray and thermal probing as well as chemical and electrical tampering attempts.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: June 4, 2013
    Assignee: Conexant Systems, Inc.
    Inventors: Robert W Warren, Hyun Jung Lee, Nic Rossi
  • Patent number: 8445997
    Abstract: A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged integrated circuit device and a plurality of planar conductive members conductively coupling the first and second packaged integrated circuit devices to one another. A method is also disclosed which includes conductively coupling a plurality of extensions on a leadframe to each of a pair of stacked packaged integrated circuit devices and cutting the leadframe to singulate the extensions from one another.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: May 21, 2013
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Chin Hui Chong, Choon Kuan Lee
  • Publication number: 20130119520
    Abstract: A microelectronic element is disclosed that includes a semiconductor chip and a continuous monolithic metallic edge-reinforcement ring that covers each of the plurality of edge surfaces of the semiconductor chip and extending onto the front surface. The semiconductor chip may have front and rear opposed surfaces and a plurality of contacts at the front surface and edge surfaces extending between the front and rear surfaces. The semiconductor chip may also embody at least an active device or a passive device.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 16, 2013
    Applicant: INVENSAS CORP.
    Inventor: Ilyas Mohammed
  • Patent number: 8441104
    Abstract: A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: May 14, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Lejun Hu, Srivatsan Parthasarathy, Michael Coln, Javier Salcedo
  • Patent number: 8436352
    Abstract: Whether there is a defect such as chipping of a die or separation of a resin in a wafer level package is electrically detected. A peripheral wiring is disposed along four peripheries of a semiconductor substrate outside a circuit region and pad electrodes P1-P8. The peripheral wiring is formed on the semiconductor substrate and is made of a metal layer that is the same layer as or an upper layer of a metal layer forming the pad electrodes P1-P8, or a polysilicon layer. A power supply electric potential Vcc is applied to a first end of the peripheral wiring, while a ground electric potential Vss is applied to a second end of the peripheral wiring through a resistor R2. A detection circuit is connected to a connecting node N1 between the peripheral wiring and the resistor R2, and is structured to generate an anomaly detection signal ERRFLG based on an electric potential at the connecting node N1.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: May 7, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Yoshinobu Kaneda, Koji Ishida
  • Patent number: 8426234
    Abstract: An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 23, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 8421167
    Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: April 16, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Aaron Partridge, Markus Lutz, Silvia Kronmueller
  • Publication number: 20130075870
    Abstract: A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 28, 2013
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: STMicoelectronics (Crolles 2) SAS, STMicroelectronics SA,
  • Patent number: 8399977
    Abstract: A method of producing a resin-sealed package is provided with: providing an electronic component which has a plurality of terminals on one face, a first support member and a second support member; temporarily fixing said electronic component to a surface of said first support member by a first adhesive agent layer, to face said terminals with said first support member; fixing said second support member having a second adhesive agent layer to said electronic component while interposing said electronic component between said first support member and said second support member to face said second adhesive agent layer with a back face side of said electronic component; resin sealing said electronic component between said first support member and said second support member; peeling said first support member and said first adhesive agent layer from said electronic component and a sealing resin; and stacking an insulating resin layer and a wiring layer which is electrically connected to said terminals of said electr
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: March 19, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuji Kunimoto, Akihiko Tateiwa
  • Publication number: 20130062752
    Abstract: A ring structure for chip packaging comprises a frame portion adaptable to bond to a substrate and at least one corner portion. The frame portion surrounds a semiconductor chip and defines an inside opening, and the inside opening exposes a portion of a surface of the substrate. The at least one corner portion extends from a corner of the frame portion toward the chip, and the corner portion is free of a sharp corner.
    Type: Application
    Filed: September 8, 2011
    Publication date: March 14, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Yi LIN, Yu-Chih LIU, Ming-Chih YEW, Tsung-Shu LIN, Bor-Rung SU, Jing Ruei LU, Wei-Ting LIN
  • Patent number: 8373254
    Abstract: A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: February 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Yu-Wen Liu, Hao-Yi Tsai
  • Patent number: 8368194
    Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: February 5, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Robert Francis Darveaux, Michael Barrow, Miguel Angel Jimarez, Jae Dong Kim, Dae Keun Park, Ki Wook Lee, Ju Hoon Yoon
  • Patent number: 8357996
    Abstract: An apparatus that comprises a device on a substrate and a crack stop in the substrate. Methods of forming a device are also disclosed. The methods may include providing a device, such as a semiconductor device, on a substrate having a first thickness, reducing the thickness of the substrate to a second thickness, and providing a crack stop in the substrate. Reducing the thickness of the substrate may include mounting the substrate to a carrier substrate for support and then removing the carrier substrate. The crack stop may prevent a crack from reaching the device.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: January 22, 2013
    Assignee: Cree, Inc.
    Inventors: Van Allen Mieczkowski, Daniel James Namishia
  • Patent number: 8344493
    Abstract: A through substrate via (TSV) die includes a substrate including a topside semiconductor surface having active circuitry. The die includes a plurality of TSVs that each include an inner metal core that extend from the topside semiconductor surface to protruding TSV tips that extend out from the bottomside surface. A metal cap is on the protruding TSV tips that includes at least one metal layer that has a metal that is not in the inner metal core. A plurality of protruding warpage control features are on the bottomside surface lateral to the protruding TSV tips, wherein the plurality of protruding warpage control features do not have the protruding TSV tips thereunder. The plurality of protruding warpage control features can include the same metal layer(s) used for the metal cap.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: January 1, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey Alan West, Jeffrey E. Brighton, Margaret Simmons-Matthews
  • Patent number: 8338917
    Abstract: The present disclosure provides a method of fabricating a semiconductor device, the method including providing a substrate having a seal ring region and a circuit region, forming a first seal ring structure over the seal ring region, forming a second seal ring structure over the seal ring region and adjacent to the first seal ring structure, and forming a first passivation layer disposed over the first and second seal ring structures. A semiconductor device fabricated by such a method is also provided.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: December 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dun-Nian Yaung, Jen-Cheng Liu, Jeng-Shyan Lin, Wen-De Wang, Shu-Ting Tsai
  • Patent number: 8324714
    Abstract: A semiconductor device includes a semiconductor substrate having a main surface in which a semiconductor element region where a plurality of functional elements are formed is formed; a multilevel wiring layer disposed on the main surface of the semiconductor substrate; a first organic insulating material layer disposed on the multilevel wiring layer; a groove that penetrates the multilevel wiring layer on a scribe region that surrounds the semiconductor element region; and an organic insulating material that is spaced from the first organic insulating material layer and disposed in the groove.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: December 4, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Jun Tsukakoshi, Yoshitaka Aiba