Abstract: A photosensitive adhesive composition that comprises (A) a resin with a carboxyl and/or hydroxyl group, (B) a thermosetting resin, (C) a radiation-polymerizable compound and (D) a photoinitiator, wherein the 3% weight reduction temperature of the entire photoinitiator mixture in the composition is 200° C. or greater.

Abstract: A device, and method for manufacturing the same, including a semiconductor package which allows transmission therethrough of a radio signal, a chip which generates the radio signal and a coupler adjacent the chip and effective to radiate the radio signal to outside of the semiconductor package.

Abstract: A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.

Abstract: A semiconductor device having no voids and a semiconductor package using the same is described. The semiconductor device includes a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area defined around the first area, and an insulation layer covering the first and second areas and having at least one void removing part which extends from the first area to the second area to prevent a void from being formed.

Abstract: Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.

Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.

Abstract: The present invention relates to an AC light emitting diode. An object of the present invention is to provide an AC light emitting diode wherein various designs for enhancement of the intensity of light, prevention of flickering of light or the like become possible, while coming out of a unified method of always using only one metal wire with respect to one electrode when electrodes of adjacent light emitting cells are connected through metal wires. To this end, the present invention provides an AC light emitting diode comprising a substrate; bonding pads positioned on the substrate; a plurality of light emitting cells arranged in a matrix form on the substrate; and a wiring means electrically connecting the bonding pads and the plurality of light emitting cells, wherein the wiring means includes a plurality of metal wires connecting an electrode of one of the light emitting cells with electrodes of other electrodes adjacent to the one of the light emitting cells.

Abstract: A system is described that connects the surface of a first substrate to the edge of a second substrate. The surfaces of additional substrates can be placed on the remaining edges of the second substrate to form a 3-D structure. Rigid support substrates can be connected to the first substrate to provide support for the first and additional substrates. The second substrate can be used to carry heat, fluids, electrical power or signals between first and additional substrates besides providing a mechanical support.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an encapsulation surrounding an integrated circuit having an inactive side and an active side exposed; forming a hole through the encapsulation with the hole not exposing the integrated circuit; forming a through conductor in the hole; and mounting a substrate with the integrated circuit surrounded by the encapsulation with the active side facing the substrate.

Abstract: A semiconductor device in which size reduction is possible without functional devices below pads being damaged by stress. The semiconductor device has a plurality of pads above a semiconductor substrate as terminals for external connection. A plurality of dual use pads which are used in both a probing test and assembly are provided in a first area above a main surface of the semiconductor substrate, an application of pressure by a probe during the probing test being permitted in the first area, and a plurality of assembly pads which are not used in the probing test are provided in a second area above the main surface of the semiconductor substrate, the application of pressure by the probe during the probing test being not permitted in the second area.

Abstract: A sensor is implemented in an integrated circuit. The sensor includes one or more sensor pads that are provided at or near a surface of the integrated circuit. One or more integrated circuit components such as a sense amplifier are provided in the integrated circuit die adjacent the sensor pads. One or more other components are provided in the integrated circuit die adjacent the sensor pads.

Abstract: A semiconductor device has a first insulation layer formed over a sacrificial substrate. A first conductive layer is formed over the first insulating layer. Conductive pillars are formed over the first conductive layer. A pre-fabricated IPD is disposed between the conductive pillars. An encapsulant is formed around the IPD and conductive pillars. A second insulation layer is formed over the encapsulant. The conductive pillars are electrically connected to the first and second conductive layers. The first and second conductive layers each include an inductor. Semiconductor devices are mounted over the first and second insulating layer and electrically connected to the first and second conductive layers, respectively. An interconnect structure is formed over the first and second insulating layers, respectively, and electrically connected to the first and second conductive layers. The sacrificial substrate is removed.

Abstract: An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use.

Abstract: A solid-state imaging device includes a semiconductor substrate, one or more wiring interlayer films disposed on or above the semiconductor substrate, and one or more metal wires embedded in the wiring interlayer films. The one or more wiring interlayer films are composed of a diffusion preventing material that prevents the diffusion of the metal wire.

Abstract: A Micro ElectroMechanical Systems device according to an embodiment of the present invention is formed by dicing a MEMS wafer and attaching individual MEMS dies to a substrate. The MEMS die includes a MEMS component attached to a glass layer, which is attached to a patterned metallic layer, which in turn is attached to a number of bumps. Specifically, the MEMS component on the glass layer is aligned to one or more bumps using windows that are selectively created or formed in the metallic layer. One or more reference features are located on or in the glass layer and are optically detectable. The reference features may be seen from the front surface of the glass layer and used to align the MEMS components and may be seen through the windows and used to align the bumps. As an end result, the MEMS component may be precisely aligned with the bumps via optical detection of the reference features in the glass layer.

Abstract: A method of manufacturing a silicon optoelectronic device, a silicon optoelectronic device manufactured by the method, and an image input and/or output apparatus having the silicon optoelectronic device are provided. The method includes: preparing an n-type or p-type silicon-based substrate; forming a polysilicon in one or more regions of the surface of the substrate; oxidizing the surface of the substrate where the polysilicon is formed, to form a silicon oxidation layer on the substrate, and forming a microdefect flection pattern at the interface between the substrate and the silicon oxidation layer, wherein the microdefect flection pattern is formed by the oxidation accelerated by oxygen traveling through boundaries of the grains in the polysilicon; exposing the microdefect flection pattern by etching the silicon oxidation layer; and forming a doping region by doping the exposed microdefect flection pattern with a dopant of the opposite type to the substrate.

Abstract: An fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO2 film. Portions of the substrate side are selectively coated with a polymer film and etching of uncoated areas removes at least a substantial portion of the crystalline substrate. A plasma etch tool etches a crystalline substrate to within a pre-determined thickness. The silicon portions of the substrate side are etched by exposure to TMAH. After etching, the donor semiconductor wafer is supported by portions of the substrate that were not etched. The supporting structure allows flexing of the donor semiconductor wafer within the etched areas to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

Abstract: An apparatus including a semiconductor substrate is disclosed. A first semiconductor die is disposed on the semiconductor substrate. A first bond out pad is disposed on the semiconductor substrate adjacent to the first semiconductor die. A first sawn semiconductor die is disposed on the semiconductor substrate adjacent to the first semiconductor die and the first bond out pad.

Abstract: A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

Abstract: An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers of the integrated circuit provides a high voltage isolation link between the first group of functional circuitry and a second group of functional circuitry connected to the integrated circuit through the capacitive isolation circuitry. The capacitive isolation circuitry includes a differential transmitter for transmitting data in a differential signal to the second group of functional circuitry via the capacitive isolation circuitry. A differential receiver receives data within the differential signal from the second group of functional circuitry via the capacitive isolation circuitry.

Abstract: Thermally aware design improvement enables increasing performance, reliability, and other related metrics by performing a multi-dimensional thermal analysis of a design of an electronic component in an assumed operating environment. Results of the analysis are then used to drive optimizations and repairs to the design. The performance metrics include maximum and minimum operating frequency, leakage current, power consumption, temperature gradient, absolute temperature, and other related parameters. The reliability metrics include Mean Time Between Failure (MTBF), required burn-in time, and other related parameters. In a related aspect, thermally aware design improvement enables performance driven electronic component design optimization and repair, including improving aspects of the physical design of an included semiconductor die. Improvements include modifying design details such as placement and routing of individual elements of the die.

Abstract: A lithography apparatus includes a part having a photocatalytic coating. The lithography apparatus can be an extreme ultraviolet lithography apparatus or an immersion lithography apparatus.

Abstract: In a semiconductor device of the present invention, semiconductor chips are stacked in multi-layers. Each of the semiconductor chip includes: through vias extending through a top main surface thereof to a bottom surface opposite to the top main surface; a circuit element surface formed on the top main surface; pads arranged on the circuit element surface; bumps formed on the pads; and via pads, formed on the bottom surface thereof, to which the bumps of its upper semiconductor chip are joined, and positions at which the bumps of each of the semiconductor chips are respectively arranged are different from those at which the bumps of its upper semiconductor chip are arranged.

Abstract: A semiconductor device which can prevent the degradation of contact yield even when subjected to a high-temperature and long-time thermal process, and a manufacturing method thereof are provided. The semiconductor device includes: a first semiconductor circuit formed on a semiconductor substrate; a second semiconductor circuit formed above the first semiconductor circuit; an interlayer insulating film formed between the first semiconductor circuit and the second semiconductor circuit; and a contact plug formed in a state of penetrating the interlayer insulating film, the contact plug including a contact plug body made up of a conductor, and a contact plug coating which is insulating and which covers at least a portion of a side face of the contact plug body in contact with the interlayer insulating film.

Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Abstract: A method of manufacturing a silicon optoelectronic device, a silicon optoelectronic device manufactured by the method and an image input and/or output apparatus having the silicon optoelectronic device are provided.

Abstract: A semiconductor apparatus includes: a first chip including a MEMS device which has a structure supported in midair therein, and having first pads and a first joining region electrically connected to the MEMS device on a top face thereof; a second chip including a circuit having a semiconductor device electrically connected to the MEMS device therein, and having second pads and a second joining region electrically connected to the semiconductor device on a top face thereof, the second chip being disposed in opposition to the first chip so as to oppose the second pads and the second joining region respectively to the first pads and the first joining region; electrical connection parts which electrically connect the first pads to the second pads, respectively; and joining parts provided between the first joining region and the second joining region opposed to the first joining region to join the first chip and the second chip to each other.

Abstract: A surface-mountable light-emitting diode light source is described, in which the leadframe-bends toward the rear side of the package that are required for surface mounting lie within a transparent plastic molded body. Also described is a method of producing a mixed-light, preferably white-light source on the basis of a UV- or blue-emitting semiconductor LED. The LED is mounted on a leadframe, a transparent plastics molding composition is mixed with a conversion substance and possibly further fillers to form a molding composition. The leadframe is encapsulated, preferably by the injection-molding process, with the molding composition in such a way that the LED is surrounded on its light-exiting sides by the molding composition.

Abstract: This invention provides a new method of forming a self-assembling monolayer (SAM) of alcohol-terminated or thiol-terminated organic molecules (e.g. ferrocenes, porphyrins, etc.) on a silicon or other group IV element surface. The assembly is based on the formation of an E-O— or an E-S— bond where E is the group IV element (e.g. Si, Ge, etc.). The procedure has been successfully used on both P- and n-type group IV element surfaces. The assemblies are stable under ambient conditions and can be exposed to repeated electrochemical cycling.

Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.

Abstract: A element group includes a plurality of semiconductor elements stacked in a step-like shape on a wiring board. The semiconductor elements are electrically connect to connection pads of the wiring board through metal wires. Among the plural semiconductor elements stacked in a step-like shape, the uppermost semiconductor element has a thickness larger than that of the semiconductor element immediately below it.

Abstract: Providing a duplicate test signal of an output signal under test in an integrated circuit including selecting through a multiplexer an output signal under test, the output signal under test selected from a plurality of output signals of the integrated circuit; providing through the multiplexer a duplicate signal of the selected output signal under test; adding a high impedance load on the duplicate signal thereby reducing the amplitude of the duplicate signal; and amplifying the reduced duplicate signal thereby creating the duplicate test signal.

Abstract: An integrated circuit packaging system comprising: fabricating a system-in-package substrate; mounting a first integrated circuit die on the system-in-package substrate; mounting a second integrated circuit die on the system-in-package substrate; and coupling a passive component over and between the first integrated circuit die and the second integrated circuit die.

Abstract: The technology in which lowering of the manufacturing yield of the semiconductor products resulting from contamination impurities can be suppressed is offered. When reducing the thickness of a semiconductor wafer, so that a crushing layer which is relatively thin and has gettering function of, for example, less than 0.5 ?m, less than 0.3 ?m or less than 0.1 ?m in thickness may be formed at the back surface, and the die strength after making the semiconductor wafer into chips by dividing or almost dividing may be secured, the back surface of the semiconductor wafer is ground by the diamond wheel which held the diamond abrasive of, for example, fineness number #5000 to #20000 with vitrified cement B1 which has countless bubbles and impregnated synthetic-resin B2 which has viscosity in the countless bubbles.

Abstract: A method of a fabricating a multiple wavelength adapted photodiode and resulting photodiode includes the steps of providing a substrate having a first semiconductor type surface region on at least a portion thereof, implanting and forming a second semiconductor type shallow surface layer into the surface region, and forming a multi-layer anti-reflective coating (ARC) on the shallow surface layer. The forming step includes depositing or forming a thin oxide layer on the shallow surface layer and depositing a second dielectric layer different from the thin oxide layer on the thin oxide layer. An etch stop is formed on the second dielectric, wherein the etch stop includes at least one layer resistant to oxide etch. At least one oxide including layer (e.g. ILD) is then deposited on the etch stop. The oxide including layer and etch stop are then removed to expose at least a portion of the ARC to the ambient.

Abstract: A method of fabricating an integrated circuit including arranging a nanowire with a first end portion thereof at a first contact surface of a first electrical contact and with a second end portion sticking up from the first contact surface, and embedding at least part of the nanowire in dielectric material.

Abstract: A radiation image detection method including the steps of: detecting from a radiation image detector including multitudes of pixels disposed two-dimensionally, each having a TFT switch, an analog image signal of each pixel flowing out through each data line by sequentially switching ON the TFT switches connected to each scanning line on a scanning line-by-scanning line basis; detecting an analog leak level flowing out through each data line with the TFT switches connected to each of the scanning lines being switched OFF each time before switching ON the TFT switches on a scanning line-by-scanning line basis when converting the detected analog image signal to a digital image signal and outputting; and correcting the analog image signal before being converted to the digital image signal based on the leak level.

Abstract: An integrated circuit and a method for making an integrated circuit is disclosed. In one embodiment, at least one contact of an electrically conductive material is formed on a substrate. A layer is disposed on the substrate to a predetermined height of the contact. An electrically conductive via hole is provided in the layer by the contact.

Abstract: Provided is a semiconductor chip (1) including: at least one fuse element (21); a fuse opening (17) formed above the fuse element (21); and a discharge electrode (31) that is formed below a bottom portion (17a) of the fuse opening (17), and is formed in one of the same layer with the fuse element (21) and the above layer of the fuse element (21). Accordingly, the current caused to flow due to the electrostatic discharge generated at the time of assembling the semiconductor chip can be discharged through the discharge electrode (31). As a result, the current caused to flow due to the electrostatic discharge generated at the time of assembling the semiconductor chip can be prevented from being discharged through the fuse element, whereby a problem in that a functional failure occurs in the semiconductor chip can be solved.

Abstract: Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.

Abstract: A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the first insulation layers.

Abstract: A nitride compound semiconductor element according to the present invention is a nitride compound semiconductor element including a substrate 1 having an upper face and a lower face and a semiconductor multilayer structure 40 supported by the upper face of the substrate 1, such that the substrate 1 and the semiconductor multilayer structure 40 have at least two cleavage planes. At least one cleavage inducing member 3 which is in contact with either one of the two cleavage planes is provided, and a size of the cleavage inducing member 3 along a direction parallel to the cleavage plane is smaller than a size of the upper face of the substrate 1 along the direction parallel to the cleavage plane.

Abstract: An E-fuse and a method for fabricating an E-fuse integrating polysilicon resistor masks, and a design structure on which the subject E-fuse circuit resides are provided. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.

Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: A wiring board (20) includes a first wiring portion (10) having a plurality of wiring layers (1) and a plurality of external connecting bumps (5), and a second wiring portion (15) integrated with the first wiring portion in the direction of thickness. The thermal expansion coefficient of the second wiring portion is made smaller than that of the first wiring portion, and equal to that of a semiconductor chip (30) to be mounted on the wiring board. This suppresses the internal stress resulting from the thermal expansion coefficient difference between the semiconductor chip and wiring board, and increases the reliability of a semiconductor device (50) obtained by mounting the semiconductor chip on the wiring board. The sizes of the opposing surfaces of the first and second wiring portions are also made equal.

Abstract: The present invention provides a module with a built-in semiconductor that can suppress a reduction in yield caused by a crack or failure of a semiconductor device in the process of mounting a thin semiconductor device on a wiring board and a method for manufacturing the module. In the module with a built-in semiconductor, a semiconductor device (107) is contained in an interlayer connection member (105) located between a first wiring board (101) and a second wiring board (103). The back side of the semiconductor device (107) is die-bonded to the first wiring board (101) via an adhesive (108), and the semiconductor device (107) is connected electrically to the second wiring pattern (104) via a protruding electrode (109).