Devices Responsive Or Sensitive To Electromagnetic Radiation, E.g., Infrared Radiation, Adapted For Conversion Of Radiation Into Electrical Energy Or For Control Of Electrical Energy By Such Radiation (epo) Patents (Class 257/E25.004)
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Patent number: 8816484Abstract: A semiconductor device, in which an integrated circuit portion and an antenna are easily connected, can surely transmit and receive a signal to and from a communication device. The integrated circuit portion is formed of a thin film transistor over a surface of a substrate so that the area occupied by the integrated circuit portion is increased. The antenna is provided over the integrated circuit portion, and the thin film transistor and the antenna are connected. Further, the area over the substrate occupied by the integrated circuit portion is 0.5 to 1 times as large as the area of the surface of the substrate. Thus, the size of the integrated circuit portion can be close to the desired size of the antenna, so that the integrated circuit portion and the antenna are easily connected and the semiconductor device can surely transmit and receive a signal to and from the communication device.Type: GrantFiled: February 6, 2008Date of Patent: August 26, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Jun Koyama, Shunpei Yamazaki
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Patent number: 8809078Abstract: A self-powered circuit package includes a substrate and an integrated circuit (IC). The IC is mounted on a surface of the substrate. An electrical interconnector electrically couples the IC to the substrate. A solar cell is provided having opposing first and second main surfaces. A portion of the first main surface of the solar cell is configured to receive light from an external source. The solar cell converts energy of the received light into electrical power. The solar cell is disposed above the IC and electrically connected to the IC by way of the substrate to supply the generated power to the IC. A clear mold compound encapsulates a surface of the substrate, the IC, the electrical interconnector, and the solar cell.Type: GrantFiled: February 13, 2013Date of Patent: August 19, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Teck Beng Lau, Wai Yew Lo, Boon Yew Low, Chin Teck Siong
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Patent number: 8803164Abstract: To provide a solid-state image sensing device or a semiconductor display device, which can easily obtain the positional data of an object without contact. Included are a plurality of first photosensors on which light with a first incident angle is incident from a first incident direction and a plurality of second photosensors on which light with a second incident angle is incident from a second incident direction. The first incident angle of light incident on one of the plurality of first photosensors is larger than that of light incident on one of the other first photosensors. The second incident angle of light incident on one of the plurality of second photosensors is larger than that of light incident on one of the other second photosensors.Type: GrantFiled: July 29, 2011Date of Patent: August 12, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda
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Patent number: 8722453Abstract: The method includes: steps of forming an n-type diffusion layer having an n-type impurity diffused thereon at a first surface side of a p-type silicon substrate; forming a reflection prevention film on the n-type diffusion layer; forming a back-surface passivation film made of an SiONH film on a second surface of the silicon substrate; forming a paste material containing silver in a front-surface electrode shape on the reflection prevention film; forming a front surface electrode that is contacted to the n-type diffusion layer by sintering the silicon substrate; forming a paste material containing a metal in a back-surface electrode shape on the back-surface passivation film; and forming a back surface electrode by melting a metal in the paste material by irradiating laser light onto a forming position of the back surface electrode and by solidifying the molten metal.Type: GrantFiled: April 14, 2009Date of Patent: May 13, 2014Assignee: Mitsubishi Electric CorporationInventor: Mitsunori Nakatani
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Patent number: 8610048Abstract: A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers.Type: GrantFiled: September 22, 2011Date of Patent: December 17, 2013Assignee: STMicroelectronics S.A.Inventors: Jerome Alieu, Simon Guillaumet, Christophe Legendre, Hughes Leininger, Jean-Pierre Oddou, Marc Vincent
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Patent number: 8552519Abstract: In order to collect a plurality of semiconductor elements easily from a semiconductor module where a plurality of rod-like semiconductor elements for power generation or light emission are built in and to reuse or repair them, two split modules 61 are arranged in series in a containing case 62 in a semiconductor module 60. In each split module 61, power generating semiconductor elements 1 arranged in a matrix of a plurality of rows and columns, and a conductive connection mechanism for connecting the plurality of semiconductor elements 1 in each row in series and the plurality of semiconductor elements 1 in each column in parallel are molded with transparent synthetic resin, and a connection conductor 67 is allowed to project at the end. A conductive waved spring 70 and an external terminal 76 are provided on the end side of the containing case 62, and series connection of the two split modules 61 is ensured by mechanical pressing force of the conductive waved spring 70.Type: GrantFiled: August 7, 2006Date of Patent: October 8, 2013Assignee: Kyosemi CorporationInventor: Josuke Nakata
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Patent number: 8399287Abstract: A solar cell that is readily manufactured using processing techniques which are less expensive than microelectronic circuit processing. In preferred embodiments, printing techniques are utilized in selectively forming masks for use in etching of silicon oxide and diffusing dopants and in forming metal contacts to diffused regions. In a preferred embodiment, p-doped regions and n-doped regions are alternately formed in a surface of the wafer through use of masking and etching techniques. Metal contacts are made to the p-regions and n-regions by first forming a seed layer stack that comprises a first layer such as aluminum that contacts silicon and functions as an infrared reflector, second layer such titanium tungsten that acts as diffusion barrier, and a third layer functions as a plating base. A thick conductive layer such as copper is then plated over the seed layer, and the seed layer between plated lines is removed.Type: GrantFiled: January 25, 2011Date of Patent: March 19, 2013Assignee: SunPower CorporationInventors: William P. Mulligan, Michael J. Cudzinovic, Thomas Pass, David D. Smith, Neil Kaminar, Keith McIntosh, Richard M. Swanson
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Patent number: 8253143Abstract: There is provided a light emitting module. The light emitting module includes: a semiconductor light emitting element that emits light; and a plate-like optical wavelength conversion member that converts a wavelength of light emitted from the semiconductor light emitting element and emits light having the converted wavelength. The semiconductor light emitting element and the optical wavelength conversion member are directly bonded to each other.Type: GrantFiled: June 8, 2010Date of Patent: August 28, 2012Assignee: Koito Manufacturing Co., Ltd.Inventor: Shogo Sugimori
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Patent number: 8242527Abstract: A light emitting device for generating infrared light includes a substrate, a first metal layer, a dielectric layer and a second metal layer. The substrate has a first surface. The first metal layer is formed on the first surface of the substrate. The dielectric layer is formed on the first metal layer. A thickness of the dielectric layer is greater than a particular value. The second metal layer is formed on the dielectric layer. When the light emitting device is heated, the dielectric layer has a waveguide mode such that the infrared light generated by the light emitting device can be transmitted in the dielectric layer. A wavelength of the infrared light generated in the waveguide mode relates to the thickness of the dielectric layer.Type: GrantFiled: March 22, 2010Date of Patent: August 14, 2012Assignee: National Taiwan UniversityInventors: Si-Chen Lee, Yu-Wei Jiang, Yi-Ting Wu, Ming-Wei Tsai, Pei-En Chang
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Patent number: 8212264Abstract: A module and method of its production in which areal electronic components are formed. The module includes (a) a cover electrode covering the electronic components; (b) a flexibly deformable substrate; (c) a base electrode formed on the substrate; and (d) an optically active layer formed on the base electrode. The electronic components are formed on the flexibly deformable substrate by the optically active layer, the cover electrode; and the base electrode. The cover electrode projects over the optically active layer at a first side and the base electrode extends beyond the optically active layer at a second side which is oppositely disposed with regards to the first side.Type: GrantFiled: July 17, 2008Date of Patent: July 3, 2012Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.Inventor: Olaf Ruediger Hild
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Patent number: 8193041Abstract: The yield of a semiconductor device is improved. Inside the resin sealing body which forms a semiconductor device, the semiconductor chip is sealed in the state where it has arranged aslant to the upper and lower sides of a resin sealing body. In the suspension lead which supports the die pad carrying this semiconductor chip, the small recess is formed in the fifth surface of the opposite side with the surface on which the semiconductor chip was mounted. This recess is a portion used as the starting point when making die pad 2a slanting. The side surface of the side near a die pad between two side surfaces of this recess is formed in the state where it inclined rather than the side surface of the side near the periphery of a resin sealing body.Type: GrantFiled: October 31, 2007Date of Patent: June 5, 2012Assignee: Renesas Electronics CorporationInventor: Shigeki Tanaka
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Patent number: 8058656Abstract: The invention relates to a method for producing a matrix of electronic components, comprising a step of producing an active layer on a substrate, and a step of individualizing the components by forming trenches in the active layer at least until the substrate emerges. The method comprises steps of depositing a layer of functional material on the active layer, depositing a photosensitive resin on the layer of material in such a way as to fill said trenches and to form a thin film on the upper face of the components, at least partially exposing the resin to radiation while underexposing the portion of resin in the trenches, developing the resin in such a way as to remove the properly exposed portion thereof, removing the functional material layer portion that shows through after the development step, and removing the remaining portion of resin.Type: GrantFiled: December 9, 2008Date of Patent: November 15, 2011Assignee: Commissariat a l'Energie AtomiqueInventors: Francois Marion, Olivier Gravrand
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Patent number: 7986021Abstract: The invention provides a semiconductor device that solves a problem of reflection of a pattern of a wiring formed on a back surface of a semiconductor substrate on an output image. A reflection layer is formed between a light receiving element and a wiring layer, that reflects an infrared ray toward a light receiving element the without transmitting it to the wiring layer, the infrared ray entering from a light transparent substrate toward the wiring layer through a semiconductor substrate. The reflection layer is formed at least in a region under the light receiving element uniformly or only under the light receiving element. Alternatively, an anti-reflection layer having a function of absorbing the entering infrared ray to prevent transmission thereof may be formed instead of the reflection layer.Type: GrantFiled: December 15, 2006Date of Patent: July 26, 2011Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Kazuo Okada, Katsuhiko Kitagawa, Takashi Noma, Shigeki Otsuka, Hiroshi Yamada, Shinzo Ishibe, Yuichi Morita, Noboru Okubo, Hiroyuki Shinogi, Mitsuru Okigawa
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Patent number: 7919779Abstract: The manufacturing method of a semiconductor device according to the present invention comprises steps of forming a metal film, an insulating film, and an amorphous semiconductor film in sequence over a first substrate; crystallizing the metal film and the amorphous semiconductor film; forming a first semiconductor element by using the crystallized semiconductor film as an active region; attaching a support to the first semiconductor element by using an adhesive; causing separation between the metal film and the insulating film; attaching a second substrate to the separated insulating film; separating the support by removing the adhesive; forming an amorphous semiconductor film over the first semiconductor element; and forming a second semiconductor element using the amorphous semiconductor film as an active region.Type: GrantFiled: February 12, 2009Date of Patent: April 5, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuo Nishi, Toru Takayama, Yuugo Goto
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Patent number: 7883343Abstract: A solar cell that is readily manufactured using processing techniques which are less expensive than microelectronic circuit processing. In preferred embodiments, printing techniques are utilized in selectively forming masks for use in etching of silicon oxide and diffusing dopants and in forming metal contacts to diffused regions. In a preferred embodiment, p-doped regions and n-doped regions are alternately formed in a surface of the wafer through use of masking and etching techniques. Metal contacts are made to the p-regions and n-regions by first forming a seed layer stack that comprises a first layer such as aluminum that contacts silicon and functions as an infrared reflector, second layer such titanium tungsten that acts as diffusion barrier, and a third layer functions as a plating base. A thick conductive layer such as copper is then plated over the seed layer, and the seed layer between plated lines is removed.Type: GrantFiled: March 28, 2007Date of Patent: February 8, 2011Assignee: SunPower CorporationInventors: William P. Mulligan, Michael J. Cudzinovic, Thomas Pass, David Smith, Neil Kaminar, Keith McIntosh, Richard M. Swanson
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Patent number: 7824947Abstract: A thin film solar cell including a Group IBIIIAVIA absorber layer on a defect free base including a stainless steel substrate is provided. The stainless steel substrate of the base is surface treated to remove the surface roughness such as protrusions that cause shunts. Before removing the protrusions, a thin protective ruthenium film is first deposited on the recessed surface portions of the substrate to protect these portions during the following protrusion removal. The protrusions on the surface receives very little or no ruthenium during the deposition. After the ruthenium film is formed, the protrusions are etched and removed by an etchant which only attacks the stainless steel but neutral to the ruthenium film. A contact layer is formed over the ruthenium layer and the exposed portions of the substrate to complete the base.Type: GrantFiled: September 18, 2008Date of Patent: November 2, 2010Assignee: SoloPower, Inc.Inventors: Mustafa Pinarbasi, Serdar Aksu, Bulent M. Basol
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Patent number: 7741139Abstract: A method of manufacturing a solar cell includes forming a diffusion layer on a crystal-type silicon substrate. The diffusion layer has a conductivity opposite to that of the substrate. Furthermore, the method includes etching and removing a part of the diffusion layer by using sodium silicate, and forming a first electrode that makes an electric contact with the diffusion layer and forming a second electrode that makes an electric contact with the substrate.Type: GrantFiled: December 15, 2005Date of Patent: June 22, 2010Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yoichiro Nishimoto
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Patent number: 7732882Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.Type: GrantFiled: January 8, 2008Date of Patent: June 8, 2010Assignee: Micron Technology, Inc.Inventors: Tim Murphy, Lee Gotcher
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Patent number: 7714224Abstract: A photovoltaic power generation module that can make use of arcuate cells and a photovoltaic power generation system employing such a module are disclosed. The photovoltaic power generation module may include arcuate cells divided from a disk-shaped single crystal silicon photovoltaic power generation cell. The arcuate cells may have a circular arc with a central angle of 90°. The arcuate cells may have a grid-perpendicular to the chord and at least one busbar perpendicular to the grid. The arcuate cells may be arrayed in a lattice pattern, the arcuate cells having an area of 28 to 65 cm2 and 14 to 42 thereof being arrayed.Type: GrantFiled: July 15, 2005Date of Patent: May 11, 2010Assignees: Shin - ETSU Chemical Co., Ltd., Shin - ETSU Handotai Co., Ltd.Inventors: Takao Abe, Naoki Ishikawa
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Patent number: 7649235Abstract: The electronic component package includes a mounting board, an electronic component and a molding resin. An external electrode is disposed on a surface of the mounting board. The electronic component connected to the mounting board via the external electrode includes a component-substrate, a device, a component-cover and a protector made of resin. The component-substrate comprising a piezoelectric body includes a first surface on which the device is disposed and a second surface opposing the first surface. The component-cover covers the first surface of the substrate and the device. The protector provided on the second surface contains filler. The molding resin covers the electronic component on the mounting board.Type: GrantFiled: December 27, 2006Date of Patent: January 19, 2010Assignee: Panasonic CorporationInventor: Atsushi Takano
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Patent number: 7642620Abstract: It is an object of the present invention to provide a semiconductor apparatus for solving a trade-off between the area, power consumption, noise and accuracy of correction of a variation correction circuit that corrects variations in resistance and threshold voltage, etc. The present invention comprises a multi-value voltage generation circuit shared by a plurality of reading circuits, a multi-value voltage bus that supplies multi-value voltages to the reading circuits and switches that select a voltage suited to variation correction from multi-value voltages, wherein the multi-value voltages are distributed from the multi-value voltage generation circuit to the plurality of reading circuits, the switches select an optimum voltage for correction in the respective reading circuits to thereby correct variations in the elements.Type: GrantFiled: June 12, 2003Date of Patent: January 5, 2010Assignee: NEC CorporationInventor: Akio Tanaka
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Patent number: 7638352Abstract: The present invention is a method of manufacturing a photoelectric conversion device having a multilayered interconnection (wiring) structure disposed on a semiconductor substrate, including steps of forming a hole in a region of the interlayer insulation film corresponding to an electrode of the transistor; burying an electroconductive substance in the hole; forming a hydrogen supplying film; conducting a thermal processing at a first temperature to supply a hydrogen from the hydrogen supplying film to the semiconductor substrate; forming the multilayered interconnection structure using Cu in a wiring material; and forming a protective film covering the multilayered interconnection structure, wherein the step of forming the multilayered interconnection structure, and the step of forming the protective film are conducted at a temperature not higher than the first temperature.Type: GrantFiled: February 19, 2008Date of Patent: December 29, 2009Assignee: Canon Kabushiki KaishaInventors: Tadashi Sawayama, Takeshi Kojima
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Publication number: 20090085045Abstract: The invention relates to a method for producing a matrix of electronic components, comprising a step of producing an active layer on a substrate, and a step of individualizing the components by forming trenches in the active layer at least until the substrate emerges. The method comprises steps of depositing a layer of functional material on the active layer, depositing a photosensitive resin on the layer of material in such a way as to fill said trenches and to form a thin film on the upper face of the components, at least partially exposing the resin to radiation while underexposing the portion of resin in the trenches, developing the resin in such a way as to remove the properly exposed portion thereof, removing the functional material layer portion that shows through after the development step, and removing the remaining portion of resin.Type: ApplicationFiled: December 9, 2008Publication date: April 2, 2009Applicant: Commissariat A L'Energie AtomiqueInventors: Francois Marion, Olivier Gravrand
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Patent number: 7449718Abstract: The manufacturing method of a semiconductor device according to the present invention comprises steps of forming a metal film, an insulating film, and an amorphous semiconductor film in sequence over a first substrate; crystallizing the metal film and the amorphous semiconductor film; forming a first semiconductor element by using the crystallized semiconductor film as an active region; attaching a support to the first semiconductor element by using an adhesive; causing separation between the metal film and the insulating film; attaching a second substrate to the separated insulating film; separating the support by removing the adhesive; forming an amorphous semiconductor film over the first semiconductor element; and forming a second semiconductor element using the amorphous semiconductor film as an active region.Type: GrantFiled: January 2, 2004Date of Patent: November 11, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuo Nishi, Toru Takayama, Yuugo Goto
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Publication number: 20080124830Abstract: A method of manufacturing a CMOS image sensor in which a photodiode region and a floating diffusion region can be formed without using a hard mask. Such a method can prevent misalignment between the photodiode region and a gate pattern region without using a hard maska and also prevent the passing of ions when performing an ion implantation process through a gate region.Type: ApplicationFiled: November 13, 2007Publication date: May 29, 2008Inventor: Sang-Gi Lee
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Publication number: 20060145196Abstract: A method of fabricating a high-sensitivity image sensor is disclosed. The disclosed method comprises: etching a predetermined region of active silicon and a buried oxide layer by using a mask over an SOI substrate to expose an N-type silicon substrate; implanting P-type ions into the exposed N-type silicon substrate to form a P-type region; forming crossed active silicon by patterning the rest of the active silicon not etched while the active silicon is etched to expose the N-type silicon substrate; implanting P-type ions into first two predetermined regions facing each other of the crossed active silicon to form P-type regions; implanting N-type ions into second two predetermined regions facing each other except for the P-type regions of the crossed active silicon to form N-type regions; forming a gate oxide layer and a gate electrode on the crossed active silicon; and forming a connection part to connect the P-type region of the crossed active silicon to the P-type region of the silicon substrate.Type: ApplicationFiled: December 30, 2004Publication date: July 6, 2006Applicant: Korea Electronics Technology InstituteInventor: Hoon Kim