Devices Being Solar Cells (epo) Patents (Class 257/E25.007)
  • Patent number: 8993366
    Abstract: The method of the invention includes the sequential steps of providing a plurality of solar cells, interconnecting the solar cells using one or more interconnect tabs, attaching the interconnect tabs to a top side of the solar cell to interconnect the plurality of solar cells by coupling an exposed top surface of a first solar cell to a top surface of an adjacent second solar cell, attaching one or more bypass diodes to a top side of the solar cell, then next applying an adhesive to a first film layer, placing the plurality of solar cells onto the first film layer, then next applying an adhesive to a second film layer, placing the plurality of solar cells and first film layer onto the second film layer to form a sheet assembly, and then forming the solar sheet from the sheet assembly.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 31, 2015
    Assignee: MicroLink Devices, Inc.
    Inventors: Raymond Chan, Haruki Miyamoto
  • Patent number: 8945978
    Abstract: A metal contact of a solar cell is formed by electroplating copper using an electroplating seed that is formed on a dielectric layer. The electroplating seed includes an aluminum layer that connects to a diffusion region of the solar cell through a contact hole in the dielectric layer. A nickel layer is formed on the aluminum layer, with the nickel layer-aluminum layer stack forming the electroplating seed. The copper is electroplated in a copper plating bath that has methanesulfonic acid instead of sulfuric acid as the supporting electrolyte.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 3, 2015
    Assignee: SunPower Corporation
    Inventor: Joseph Frederick Behnke
  • Patent number: 8916905
    Abstract: It is an object to provide a photoelectric conversion device with high photoelectric conversion efficiency that improves reliability by increasing contact force between a light absorbing layer and an electrode layer. The photoelectric conversion device includes an electrode layer, and a light absorbing layer located on the electrode layer. The light absorbing layer contains a compound semiconductor. The light absorbing layer comprises a first layer close to the electrode layer and a second layer located on the first layer. The first layer has a void ratio lower than that of the second layer.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: December 23, 2014
    Assignee: KYOCERA Corporation
    Inventors: Shintaro Kubo, Shuji Nakazawa, Rui Kamada, Seiji Oguri, Shinnosuke Ushio, Shuichi Kasai, Seiichiro Inai
  • Patent number: 8900908
    Abstract: The invention relates to a method for local high-doping and contacting of a semiconductor structure which is a solar cell or a precursor of a solar cell and has a silicon semiconductor substrate (1) of a base doping type. The high-doping and contacting is effected by producing a plurality of local high-doping regions of the base doping type in the semiconductor substrate (1) on a contacting side (1a) of the semiconductor substrate and applying a metal contacting layer (7) to the contacting side (1a) or, if applicable, one or more intermediate layers wholly or partially covering the contacting side (1a), to form electrically conductive connections between the metal contacting layer (7) and the semiconductor substrate (1) at the high doping regions.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: December 2, 2014
    Assignees: Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung E.V., Albert-Ludwigs-Universität Freiburg
    Inventors: Dominik Suwito, Jan Benick, Ulrich Jager
  • Patent number: 8883543
    Abstract: Provided is a method of producing a wafer for a solar cell that can produce the solar cell with high conversion efficiency. A method of producing a wafer for a solar cell according to the present invention comprises a first step of contacting lower alcohol to at least one surface of the semiconductor wafer and a second step, after the first step, of contacting hydrofluoric acid containing metal ion to the at least one surface of the semiconductor wafer, and a third step that is, after the second step, a step of contacting alkali solution to the at least one surface of the semiconductor wafer, a step of contacting acid solution containing hydrofluoric acid and nitric acid to the at least one surface of the semiconductor wafer, or a step of carrying out an oxidation treatment to the at least one surface of the semiconductor wafer.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: November 11, 2014
    Assignee: SUMCO Corporation
    Inventor: Shigeru Okuuchi
  • Patent number: 8883545
    Abstract: The invention relates to the production of solar panels which comprise solar cells connected to one another. In this case, various layers are stacked onto one another, such as a film layer, bonding agent, insulating film, solar cells and a support layer. Combining all these layers to form the final panel is carried out on a carrier which stabilizes and supports the stack while it is conveyed past the various treatment stations. The turning over of the stack can also be carried out in a reliable manner by means of such a carrier without shifts between the various components with respect to one another occurring.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: November 11, 2014
    Assignee: Eurotron B.V.
    Inventors: Jan Bakker, Abraham Jan Verschoor, Simon Den Hartigh
  • Patent number: 8828787
    Abstract: Processes for making a thin film solar cell on a substrate by providing a substrate coated with an electrical contact layer, depositing an ink onto the contact layer of the substrate, wherein the ink contains an alkali ion source compound suspended or dissolved in a carrier along with photovoltaic absorber precursor compounds, and heating the substrate. The alkali ion source compound can be MalkMB(ER)4 or Malk(ER). The processes can be used for CIS or CIGS.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 9, 2014
    Assignee: Precursor Energetics, Inc.
    Inventors: Kyle L. Fujdala, Zhongliang Zhu, David Padowitz, Paul R. Markoff Johnson, Wayne A. Chomitz, Matthew C. Kuchta
  • Patent number: 8778787
    Abstract: Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: July 15, 2014
    Assignee: SunPower Corporation
    Inventor: Jane Manning
  • Patent number: 8753915
    Abstract: The invention relates to the production of solar panels which comprise solar cells connected to one another. In this case, various layers are stacked onto one another, such as a film layer, bonding agent, insulating film, solar cells and a support layer. Combining all these layers to form the final panel is carried out on a carrier which stabilizes and supports the stack while it is conveyed past the various treatment stations. The turning over of the stack can also be carried out in a reliable manner by means of such a carrier without shifts between the various components with respect to one another occurring.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: June 17, 2014
    Assignee: Eurotron B.V.
    Inventors: Jan Bakker, Abraham Jan Verschoor, Simon Den Hartigh
  • Patent number: 8748310
    Abstract: A method for producing a metal contact structure of a photovoltaic solar cell, including: applying an electrically non-conductive insulating layer to a semiconductor substrate, applying a metal contact layer to the insulating layer, and generating a plurality of local electrically conductive connections between the semiconductor substrate and the contact layer right through the insulating layer. The metal contact layer is formed using two pastes containing metal particles: the first paste containing metal particles is applied to local regions, and the second paste containing metal particles is applied covering at least the regions covered with the first paste and partial regions located therebetween.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: June 10, 2014
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung E.V.
    Inventors: Daniel Biro, Benjamin Thaidigsmann, Florian Clement, Robert Woehl, Edgar-Allan Wotke
  • Patent number: 8728922
    Abstract: A method for producing monocrystalline n-silicon solar cells having a rear-side passivated p+ emitter and rear-side, spatially separate heavily doped n++-base regions near the surface, as well as an interdigitated rear-side contact finger structure, which is in conductive connection with the p+-emitter regions and the n++-base regions. An aluminum thin layer or an aluminum-containing thin layer is first deposited on the rear side of the n-silicon wafer, and the thin layer is subsequently structured so that openings are obtained in the region of the future base contacts. In a further process step, the aluminum is then diffused into the n-silicon wafer in order to form a structured emitter layer.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: May 20, 2014
    Assignee: SolarWorld Industries-Thueringen GmbH
    Inventors: Hans-Joachim Krokoszinski, Jan Lossen
  • Patent number: 8722453
    Abstract: The method includes: steps of forming an n-type diffusion layer having an n-type impurity diffused thereon at a first surface side of a p-type silicon substrate; forming a reflection prevention film on the n-type diffusion layer; forming a back-surface passivation film made of an SiONH film on a second surface of the silicon substrate; forming a paste material containing silver in a front-surface electrode shape on the reflection prevention film; forming a front surface electrode that is contacted to the n-type diffusion layer by sintering the silicon substrate; forming a paste material containing a metal in a back-surface electrode shape on the back-surface passivation film; and forming a back surface electrode by melting a metal in the paste material by irradiating laser light onto a forming position of the back surface electrode and by solidifying the molten metal.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: May 13, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Mitsunori Nakatani
  • Patent number: 8703521
    Abstract: A method for fabrication of a multijunction photovoltaic (PV) cell includes providing a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack; forming a top metal layer, the top metal layer having a tensile stress, on top of the junction having the largest bandgap; adhering a top flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the top metal layer.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Norma Sosa Cortes, Keith E. Fogel, Devendra Sadana, Davood Shahrjerdi
  • Patent number: 8697559
    Abstract: One method of implanting a workpiece involves implanting the workpiece with an n-type dopant in a first region with center and a periphery. The workpiece also is implanted with a p-type dopant in a second region complementary to the first region. This second region also has a center and a periphery. The periphery of the first region and the periphery of the second region at least partially overlap. A dose at the periphery of the first region or second region is less than a dose at the center of the first region or second region. The region of overlap may function as a junction where charge carriers cannot pass.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: April 15, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, Peter L. Kurunczi, Benjamin B. Riordon, John W. Graff
  • Patent number: 8691694
    Abstract: In order to better and more efficiently assemble back contact solar cells into modules, the cell to cell soldering and other soldered connections are replaced by electro and/or electroless plating. Back contact solar cells, diodes and external leads can be first laminated to the module front glass for support and stability. Conductive materials are deposited selectively to create a plating seed pattern for the entire module circuit. Subsequent plating steps create an integrated cell and module metallization. This avoids stringing and tabbing and the associated soldering steps. This process is easier for mass manufacturing and is advantageous for handling fragile silicon solar cells. Additionally, since highly corrosion resistant metals can be plated, the moisture barrier requirements of the back side materials can be greatly relaxed. This can simplify and reduce the cost of the back side of the module.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: April 8, 2014
    Inventor: Henry Hieslmair
  • Patent number: 8685781
    Abstract: A method of forming an optoelectronic device. The method includes providing a deposition surface and contacting the deposition surface with a ligand exchange chemical and contacting the deposition surface with a quantum dot (QD) colloid. This initial process is repeated over one or more cycles to form an initial QD film on the deposition surface. The method further includes subsequently contacting the QD film with a secondary treatment chemical and optionally contacting the surface with additional QDs to form an enhanced QD layer exhibiting multiple exciton generation (MEG) upon absorption of high energy photons by the QD active layer. Devices having an enhanced QD active layer as described above are also disclosed.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: April 1, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Octavi Escala Semonin, Joseph M. Luther, Matthew C. Beard, Hsiang-Yu Chen
  • Patent number: 8610048
    Abstract: A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 17, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Jerome Alieu, Simon Guillaumet, Christophe Legendre, Hughes Leininger, Jean-Pierre Oddou, Marc Vincent
  • Patent number: 8569098
    Abstract: A method for manufacturing a photoelectric conversion device including a first-conductivity-type crystalline semiconductor region, an intrinsic crystalline semiconductor region, and a second-conductivity-type semiconductor region that are stacked over an electrode is provided for a new anti-reflection structure. An interface between the electrode and the first-conductivity-type crystalline semiconductor region is flat. The intrinsic crystalline semiconductor region includes a crystalline semiconductor region, and a plurality of whiskers that are provided over the crystalline semiconductor region and include a crystalline semiconductor. The first-conductivity-type crystalline semiconductor region and the intrinsic crystalline semiconductor region are formed by a low pressure chemical vapor deposition method at a temperature higher than 550° C. and lower than 650° C.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8519435
    Abstract: A photovoltaic cell is fabricated onto a polyimide film using an unbalanced RF magnetron sputtering process. The sputtering process includes the addition of 0.05% to 0.5% oxygen to an inert gas stream. Portions of the photovoltaic cell are exposed to an elevated temperature CdCl2 treatment which is at or below the glass transition temperature of the polyimide film.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: August 27, 2013
    Assignee: The University of Toledo
    Inventors: Anthony Vasko, Kristopher Wieland, James Walker, Alvin Compaan
  • Patent number: 8513104
    Abstract: A method of forming a floating junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front surface and a rear surface. The method also includes depositing a set of masking particles on the rear surface in a set of patterns; and heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a particle masking layer. The method further includes exposing the substrate to a phosphorous deposition ambient at a second temperature and for a second time period, wherein a front surface PSG layer, a front surface phosphorous diffusion, a rear surface PSG layer, and a rear surface phosphorous diffusion are formed, and wherein a first phosphorous dopant surface concentration in the substrate proximate to the set of patterns is less than a second dopant surface concentration in the substrate not proximate to the set of patterns.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: August 20, 2013
    Assignee: Innovalight, Inc.
    Inventors: Malcolm Abbott, Maxim Kelman, Eric Rosenfeld, Elena Rogojina, Giuseppe Scardera
  • Patent number: 8492253
    Abstract: Methods of forming contacts for back-contact solar cells are described. In one embodiment, a method includes forming a thin dielectric layer on a substrate, forming a polysilicon layer on the thin dielectric layer, forming and patterning a solid-state p-type dopant source on the polysilicon layer, forming an n-type dopant source layer over exposed regions of the polysilicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped polysilicon regions among a plurality of p-type doped polysilicon regions.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: July 23, 2013
    Assignee: SunPower Corporation
    Inventor: Jane Manning
  • Patent number: 8461282
    Abstract: The present invention discloses an iridium complex containing a (pentaphenyl)phenyl ligand, having the following general equation: in which G is primary ligand, R? and R? are auxiliary ligands. On the other hand, the present invention discloses a compound with a 9-[(pentaphenyl)phenyl]carbazole structure and its polymeric derivative.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: June 11, 2013
    Assignee: National Taiwan University
    Inventors: Kuo-Huang Hsieh, Man-Kit Leung, Wen-Chang Chen, Chao-Hui Kuo, Hong-Jun Chen, Hsin-Chung Ke, Cheng-Hsiu Ku
  • Patent number: 8420517
    Abstract: A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front substrate surface. The method further includes depositing an ink on the front substrate surface in a ink pattern, the ink comprising a set of silicon-containing particles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified film ink pattern.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: April 16, 2013
    Assignee: Innovalight, Inc.
    Inventors: Giuseppe Scardera, Shihai Kan, Maxim Kelman, Dmitry Poplavskyy
  • Patent number: 8410563
    Abstract: Electrical energy generation apparatuses, in which a solar battery device and a piezoelectric device are combined in a single body by using a plurality of nano wires formed of a semiconductor material having piezoelectric properties.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jun Park, Seung-nam Cha
  • Patent number: 8357556
    Abstract: A method and apparatus are provided for protecting a semiconductor device from damage. The method may include the steps of providing an active semiconductor device on a surface of a semiconductor substrate where the active device is surrounded by an inactive semiconductor area, and providing a soft metallic guard element in the inactive semiconductor area around at least a portion of the periphery of the active device wherein the metallic guard element is connected to ground potential and not to the active device.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: January 22, 2013
    Assignee: Emcore Corporation
    Inventors: Richard Carson, Elaine Taylor, Douglas Collins
  • Patent number: 8324012
    Abstract: A tandem solar cell and fabricating method thereof are disclosed. The steps of the fabricating method comprises: a top inverted solar cell having a plurality of inverted solar sub-cells is provided; a bottom normal solar cell having a plurality of normal solar sub-cells accompanying with the inverted solar sub-cells is provided; and processing fit process of the top inverted solar cell and the bottom normal solar cell is executed, wherein an interlayer is disposed between the bottom normal solar cell and the top inverted solar cell, and the interlayer includes a plurality of conductive dots. The plurality of inverted solar sub-cells and normal solar sub-cells are placed with an offset distance from each other, and a plurality of solar sub-cells are formed after the pressing fit process, and the plurality of solar sub-cells are series/parallel connection each other by electrically connecting the plurality of conductive dots.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: December 4, 2012
    Assignee: National Tsing Hua University
    Inventors: Sheng-Fu Horng, Hsin-Fe Meng, Ming-Kun Lee, Jen-Chun Wang, Tsung-Te Chen
  • Patent number: 8318528
    Abstract: Implementations and techniques for solar arrays of transparent nanoantennas are generally disclosed.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: November 27, 2012
    Assignee: Empire Technology Development LLC
    Inventor: Ezekiel Kruglick
  • Patent number: 8283739
    Abstract: Electrical energy generation apparatuses, in which a solar battery device and a piezoelectric device are combined in a single body by using a plurality of nano wires formed of a semiconductor material having piezoelectric properties.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 9, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jun Park, Seung-nam Cha
  • Patent number: 8263428
    Abstract: This disclosure provides polymer electrolytes for dye-sensitized solar cells that can not only prevent electrolytes from leaking, but also exhibit a higher solar conversion efficiency when compared with conventional polymer electrolytes, whereby the polymer electrolytes are applicable to a process for manufacturing dye-sensitized solar cells with a large surface area or flexible dye-sensitized solar cells, and methods for manufacturing modules of dye-sensitized solar cells using the same.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: September 11, 2012
    Assignee: Toray Advanced Materials Korea Inc.
    Inventors: Chang-Hoon Sim, Sang-Pil Kim, Ki-Jeong Moon
  • Patent number: 8247261
    Abstract: A method for manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. In one embodiment the stress layer comprises a flexible material.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra Sadana
  • Patent number: 8227881
    Abstract: A solar cell having improved efficiency and its method of manufacture includes: forming a porous layer on a surface of a semiconductor substrate; spraying a compound containing a dopant on the porous layer; and forming an emitter layer on the surface of the semiconductor substrate by diffusing the dopant.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: July 24, 2012
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Sang-Wook Park
  • Patent number: 8222129
    Abstract: A method for manufacturing a solar cell according to an exemplary embodiment includes: forming a first doping film on a substrate; patterning the first doping film so as to form a first doping film pattern and so as to expose a portion of the substrate; forming a diffusion prevention film on the first doping film pattern so as to cover the exposed portion of the substrate; etching the diffusion prevention film so as to form spacers on lateral surfaces of the first doping film pattern; forming a second doping film on the first doping film pattern so as to cover the spacer and exposed substrate; forming a first doping region on the substrate surface by diffusing an impurity from the first doping film pattern into the substrate; and forming a second doping region on the substrate surface by diffusing an impurity from the second doping film pattern into the substrate.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: July 17, 2012
    Assignees: Samsung Electronics Co., Ltd., Samsung SDI Co., Ltd.
    Inventors: Young Su Kim, Doo-Youl Lee
  • Patent number: 8217403
    Abstract: An electronic device includes a substrate and an electronic component. The substrate has a metallized trace. The metallized trace has a metallized layer and an insulation layer. The metallized layer has a high melting point metal component and a low melting point metal component, the high melting point metal component and the low melting point metal component being diffusion bonded together. The insulation layer is formed simultaneously with the metallized layer to cover an outer surface of the metallized layer. The electronic component is electrically connected to the metallized layer.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: July 10, 2012
    Assignee: Napra Co., Ltd.
    Inventors: Shigenobu Sekine, Yurina Sekine
  • Patent number: 8187907
    Abstract: A method of manufacturing a solar cell by providing a first substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell including a top subcell and a bottom subcell; forming a metal back contact over the bottom subcell; forming a group of discrete, spaced-apart first bonding elements over the surface of the back metal contact; attaching a surrogate substrate on top of the back metal contact using the bonding elements; and removing the first substrate to expose the surface of the top subcell.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: May 29, 2012
    Assignee: Emcore Solar Power, Inc.
    Inventor: Fred Newman
  • Patent number: 8148795
    Abstract: A functional device includes plural substrates, an encapsulant arranged between the plurality of substrates, and a functional material arranged between the plural of substrates and encapsulated with the encapsulant. The functional device further includes an insulating spacer arranged in an entire region where the encapsulant lies, wherein the insulating spacer bonds with the plural substrates through the encapsulant. The encapsulant and the insulating spacer of the functional device allow avoiding a short circuit by providing a constant separation distance between the plural substrates of the functional device and electrodes adjacent to the plural substrates. The insulating spacer is made of a material that is inert to the functional material.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: April 3, 2012
    Assignee: Sony Corporation
    Inventors: Masahiro Morooka, Yusuke Suzuki, Reiko Ogura
  • Patent number: 8129822
    Abstract: A template 100 for three-dimensional thin-film solar cell substrate formation for use in three-dimensional thin-film solar cells. The template 100 comprises a substrate which comprises a plurality of posts 102 and a plurality of trenches 104 between said plurality of posts 102. The template 100 forms an environment for three-dimensional thin-film solar cell substrate formation.
    Type: Grant
    Filed: October 6, 2007
    Date of Patent: March 6, 2012
    Assignee: Solexel, Inc.
    Inventor: Mehrdad Moslehi
  • Patent number: 8119438
    Abstract: A method of manufacturing a solar cell having a texture on a surface of a silicon substrate includes first forming a porous layer on the surface of the silicon substrate by dipping the silicon substrate into a mixed aqueous solution of oxidizing reagent containing metal ions and hydrofluoric acid. Second, a texture is formed by etching the surface of the silicon substrate after the porous layer is formed, by dipping the silicon substrate into a mixed acid mainly containing hydrofluoric acid and nitric acid.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: February 21, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoichiro Nishimoto
  • Patent number: 7955890
    Abstract: Embodiments of the present invention relate to methods for depositing an amorphous film that may be suitable for using in a NIP photodiode in display applications. In one embodiment, the method includes providing a substrate into a deposition chamber, supplying a gas mixture having a hydrogen gas to silane gas ratio by volume greater than 4 into the deposition chamber, maintaining a pressure of the gas mixture at greater than about 1 Torr in the deposition chamber, and forming an amorphous silicon film on the substrate in the presence of the gas mixture, wherein the amorphous silicon film is configured to be an intrinsic-type layer in a photodiode sensor.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: June 7, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Soo Young Choi, Jriyan Jerry Chen, Tae Kyung Won, Dong-Kil Yim
  • Patent number: 7888160
    Abstract: A process of manufacturing a solar cell is disclosed. The process comprises steps of (a) providing a semiconductor substrate, (b) forming a dielectric layer with amorphous silicon structure on the semiconductor substrate, (c) partially removing the dielectric layer with amorphous silicon structure to expose parts of the semiconductor substrate, (d) simultaneously forming a heavily doped region on a surface of the exposed semiconductor substrate and a lightly doped region on a surface of the unexposed semiconductor substrate using the dielectric layer with amorphous silicon structure as a translucent barrier layer, (e) removing the dielectric layer with amorphous silicon structure, (f) forming an anti-reflection coating on the semiconductor substrate, and (g) forming a first electrode on the anti-reflection coating and coupled with the heavily doped region.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: February 15, 2011
    Assignee: Mosel Vitelic Inc.
    Inventors: Chang Hong Shen, Pei Ting Lo
  • Patent number: 7883343
    Abstract: A solar cell that is readily manufactured using processing techniques which are less expensive than microelectronic circuit processing. In preferred embodiments, printing techniques are utilized in selectively forming masks for use in etching of silicon oxide and diffusing dopants and in forming metal contacts to diffused regions. In a preferred embodiment, p-doped regions and n-doped regions are alternately formed in a surface of the wafer through use of masking and etching techniques. Metal contacts are made to the p-regions and n-regions by first forming a seed layer stack that comprises a first layer such as aluminum that contacts silicon and functions as an infrared reflector, second layer such titanium tungsten that acts as diffusion barrier, and a third layer functions as a plating base. A thick conductive layer such as copper is then plated over the seed layer, and the seed layer between plated lines is removed.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: February 8, 2011
    Assignee: SunPower Corporation
    Inventors: William P. Mulligan, Michael J. Cudzinovic, Thomas Pass, David Smith, Neil Kaminar, Keith McIntosh, Richard M. Swanson
  • Patent number: 7868438
    Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: January 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Se So, Dong-Ho Lee, Hyun-Soon Jang
  • Patent number: 7785989
    Abstract: A method of manufacturing a solar cell by providing a gallium arsenide carrier with a prepared bonding surface; providing a sapphire substrate; bonding the gallium arsenide carrier and the sapphire substrate to produce a composite structure; detaching the bulk of the gallium arsenide carrier from the composite structure, leaving a gallium arsenide growth substrate on the sapphire substrate; and depositing a sequence of layers of semiconductor material forming a solar cell on the growth substrate. For some solar cells, the method further includes mounting a surrogate second substrate on top of the sequence of layers of semiconductor material forming a solar cell; and removing the growth substrate.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: August 31, 2010
    Assignee: Emcore Solar Power, Inc.
    Inventors: Paul R. Sharps, Arthur Cornfeld, Tansen Varghese, Fred Newman, Jacqueline Diaz
  • Patent number: 7741139
    Abstract: A method of manufacturing a solar cell includes forming a diffusion layer on a crystal-type silicon substrate. The diffusion layer has a conductivity opposite to that of the substrate. Furthermore, the method includes etching and removing a part of the diffusion layer by using sodium silicate, and forming a first electrode that makes an electric contact with the diffusion layer and forming a second electrode that makes an electric contact with the substrate.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: June 22, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoichiro Nishimoto
  • Patent number: 7741144
    Abstract: Embodiments of the present invention include an improved method of forming a thin film solar cell device using a plasma processing treatment between two or more deposition steps. Embodiments of the invention also generally provide a method and apparatus for forming the same. The present invention may be used to advantage to form other single junction, tandem junction, or multi-junction solar cell devices.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: June 22, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Soo Young Choi, Yong-Kee Chae, Shuran Sheng, Liwei Li
  • Patent number: 7736928
    Abstract: Embodiments of the invention contemplate the formation of a low cost solar cell using a novel electroplating apparatus and method to form a metal contact structure having metal lines formed using an electrochemical plating process. The apparatus and methods described herein remove the need to perform the often costly processing steps of performing a mask preparation and formation steps, such as screen printing, lithographic steps and inkjet printing steps, to form a contact structure. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connection that is reliable and cost effective. Therefore, one or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing a common metal, such as copper.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: June 15, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Sergey Lopatin, John O. Dukovic, David Eaglesham, Nicolay Y. Kovarsky, Robert Bachrach, John Busch, Charles Gay
  • Patent number: 7709288
    Abstract: The present invention provides a method for manufacturing a multi-junction solar cell which makes it possible to implement a 4-junction solar cell and to increase the area of a device. A nucleus generation site is disposed on a substrate 2 made of a first semiconductor. A first material gas is fed to the nucleus generation site to form a wire-like semiconductor 3 in the nucleus generation site. A third material gas and a fourth material gas are fed to form a wire-like semiconductor 4 on the semiconductor 3 and a wire-like semiconductor 5 on the semiconductor 4. A nucleus generation site is disposed on a substrate 6. The first material gas is fed to the nucleus generation site to form a wire-like semiconductor 2a in the nucleus generation site. A second material gas to the fourth material gas are fed to form the wire-like semiconductor 3 on the semiconductor 2a, the wire-like semiconductor 4 on the semiconductor 3, and the wire-like semiconductor 5 on the semiconductor 4.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: May 4, 2010
    Assignee: Honda Motor Co., Ltd.
    Inventor: Hajime Goto
  • Patent number: 7504284
    Abstract: A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: March 17, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Seng Kim Dalson Ye, Chin Hui Chong
  • Patent number: 7141834
    Abstract: Ge/Si and other nonsilicon film heterostructures are formed by hydrogen-induced exfoliation of the Ge film which is wafer bonded to a cheaper substrate, such as Si. A thin, single-crystal layer of Ge is transferred to Si substrate. The bond at the interface of the Ge/Si heterostructures is covalent to ensure good thermal contact, mechanical strength, and to enable the formation of an ohmic contact between the Si substrate and Ge layers. To accomplish this type of bond, hydrophobic wafer bonding is used, because as the invention demonstrates the hydrogen-surface-terminating species that facilitate van der Waals bonding evolves at temperatures above 600° C. into covalent bonding in hydrophobically bound Ge/Si layer transferred systems.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: November 28, 2006
    Assignee: California Institute of Technology
    Inventors: Harry A. Atwater, Jr., James M. Zahler