Including Solid State Component For Rectifying, Amplifying, Or Switching Without A Potential Barrier Or Surface Barrier (epo) Patents (Class 257/E27.004)
  • Patent number: 10559624
    Abstract: The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element, which has a low resistance state and a high resistance state, and a two-terminal selector coupled to the MTJ memory element in series. The MTJ memory element includes a magnetic free layer and a magnetic reference layer with an insulating tunnel junction layer interposed therebetween. The two-terminal selector has an insulative state and a conductive state. The two-terminal selector in the conductive state has substantially lower resistance when switching the MTJ memory element from the low to high resistance state than from the high to low resistance state. The voltages applied to the memory cell to respectively switch the MTJ memory element from the low to high resistance state and from the high to low resistance state may be substantially same.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: February 11, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Hongxin Yang, Xiaojie Hao, Jing Zhang, Xiaobin Wang, Bing K. Yen
  • Patent number: 10522757
    Abstract: In various examples, dual resistive-material regions for a phase change material region are fabricated by initially forming a resistive material. Prior to forming the phase change material region over the resistive material, at least an upper portion of the resistive material is exposed to an implantation or plasma that increases the resistance of an upper portion of the resistive material relative to the remainder, or bulk, of the resistive material. As a result, in certain embodiments, the portion of the resistive material proximate to the phase change material region may be used as a heater because of a relatively, high resistance value of the resistive material, but the bulk of the resistive material has a relatively lower resistance value and, thus, does not increase the voltage drop and current usage of the device. Other methods and devices are disclosed.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 31, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yudong Kim, Ilya V Karpov, Charles C. Kuo, Maria Santina Marangon, Tyler A. Lowrey, Greg Atwood
  • Patent number: 10332934
    Abstract: Some embodiments include a memory array which has a first series of access/sense lines extending along a first direction, and a second series of access/sense lines over the first series of access/sense lines and extending along a second direction which crosses the first direction. Memory cells are vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. Resistance-increasing material is adjacent to and coextensive with the access/sense lines of one of the first and second series, and is between the adjacent access/sense lines and programmable material of the memory cells. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Lindenberg
  • Patent number: 10311929
    Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 4, 2019
    Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.
    Inventors: Hisanori Aikawa, Tatsuya Kishi, Keisuke Nakatsuka, Satoshi Inaba, Masaru Toko, Keiji Hosotani, Jae Yun Yi, Hong Ju Suh, Se Dong Kim
  • Patent number: 10236061
    Abstract: A resistive random access memory (RRAM) including a first electrode, a second electrode, and a charge trapping layer is provided. The second electrode is located on the first electrode. The charge trapping layer is located between the first electrode and the second electrode. The charge trapping includes a first region and a second region. The first region has a first dopant and is close to the first electrode. The second region has a second dopant and is close to the second electrode.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 19, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Tuo-Hung Hou, Boris Hudec, Che-Chia Chang
  • Patent number: 10192974
    Abstract: A method for forming a semiconductor device includes incorporating chalcogen dopant atoms into a semiconductor doping region of a semiconductor substrate of a semiconductor device. The method further includes incorporating heavy metal atoms into the semiconductor doping region.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: January 29, 2019
    Assignee: Infineon Technologies AG
    Inventor: Gerhard Schmidt
  • Patent number: 10148279
    Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices ces.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 4, 2018
    Assignee: ARM Ltd.
    Inventors: Akshay Kumar, Piyush Agarwal, Bal S. Sandhu, Glen Arnold Rosendale
  • Patent number: 10134982
    Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: November 20, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni
  • Patent number: 10103326
    Abstract: Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 16, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Michael Bernhardt, Tony Lindenberg, Wenzhe Zhang, Douglas Capson
  • Patent number: 10026895
    Abstract: According to one embodiment, a memory device includes a superlattice structure portion containing first chalcogen-compound layers and second chalcogen-compound layers differing in composition from the first chalcogen-compound layers are alternately deposited, a first layer provided on one of main surfaces of the superlattice structure portion in a deposition direction thereof, which has a larger energy gap than that of the superlattice structure portion, and a second layer provided on the other main surface of the superlattice structure portion in the deposition direction, which has a larger energy gap than that of the superlattice structure portion.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: July 17, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshiki Kamata
  • Patent number: 10026780
    Abstract: According to one embodiment, a memory includes a resistance change layer includes a first chalcogenide layer, and a second chalcogenide layer having a composition different from that of the first chalcogenide layer which are stacked alternately, and the resistance change layer having a superlattice structure, and a semiconductor layer of a first conductivity type provided on a one of main surfaces of the resistance change layer.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: July 17, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshiki Kamata
  • Patent number: 10008665
    Abstract: Doping a storage element, a selector element, or both, of a memory cell with a dopant including one or more of aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si), can minimize volume or density changes in a phase change memory as well as minimize electromigration, in accordance with embodiments. In one embodiment, a memory cell includes a first electrode and a second electrode, and a storage element comprising a layer of doped phase change material between the first and second electrodes, wherein the doped phase change material includes one or more of aluminum, zirconium, hafnium, and silicon. The storage element, a selector element, or both can be doped using techniques such as cosputtering or deposition of alternating layers of a dopant layer and a storage (or selector) material.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: June 26, 2018
    Inventors: Daniel Gealy, Andrea Gotti, Dale W. Collins, Swapnil A. Lengade
  • Patent number: 10002865
    Abstract: A 3D structure, the structure including: a first stratum overlaid by a second stratum, the second stratum is less than two microns thick, where the first stratum includes an array of memory cells including at least four rows of memory cells, each of the rows is controlled by a bit-line, where the array of memory cells includes a plurality of columns of memory cells, each of the columns is controlled by a word-line, and where the second stratum includes memory control circuits directly connected to the bit-lines and the word-lines, where the second stratum includes a first layer including first transistors and a second layer including second transistors, where the first layer includes a first bus, the first bus interconnecting a plurality of first logic units, where the second layer includes a second bus, the second bus interconnecting a plurality of second logic units.
    Type: Grant
    Filed: April 8, 2017
    Date of Patent: June 19, 2018
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 9923139
    Abstract: Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 20, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Michael Bernhardt, Tony Lindenberg, Wenzhe Zhang, Douglas Capson
  • Patent number: 9871528
    Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices ces.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: January 16, 2018
    Assignee: ARM Ltd.
    Inventors: Akshay Kumar, Piyush Agarwal, Bal S. Sandhu, Glen Arnold Rosendale
  • Patent number: 9799662
    Abstract: An antifuse-type OTP memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers the surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The second gate is connected with an antifuse control line. A third gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The third gate is connected with an isolation control line.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: October 24, 2017
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wei-Zhe Wong, Meng-Yi Wu
  • Patent number: 9691760
    Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the device includes a Phase Lock Loop (“PLL”) circuit, where the second clock distribution structure is connected to the Phase Lock Loop (“PLL”) circuit, and where the second transistors are aligned to the first transistors with less than 200 nm alignment error.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: June 27, 2017
    Assignee: MONOLITHIC 3D INC
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 9525130
    Abstract: A phase change memory (“PCM”) cell is provided in accordance with some embodiments. The PCM includes a spacer defining a reaction area; a phase change material layer disposed within the reaction area; a protection layer disposed over the phase change material layer and within the reaction area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: December 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsun-Kai Tsao, Ming-Huei Shen, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 9490315
    Abstract: The invention provides a power semiconductor device and a method of fabricating the same and a cutoff ring. A cutoff ring located at a periphery of an active area of the power semiconductor device is etched forming at least one trench below which an implant area is formed by implanting ions into the trench, and a silicon dioxide dielectric layer covering the trench and a surface of the active area, are formed. Since the ions are implanted into the trench formed by etching the cutoff ring to thereby increase a depth of the implanted ions and a density of the cutoff ring, a width of the cutoff ring can be shortened to thereby address the technical problem of a considerable area of a chip occupied by the cutoff ring and improve a utilization ratio of the area of the chip so as to lower a cost of fabricating the chip.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: November 8, 2016
    Assignees: Peking University Founder Group Co., Ltd., Founder Microelectronics International Co., Ltd.
    Inventors: Li Li, Wanli Ma, Shengzhe Zhao
  • Patent number: 9418754
    Abstract: An anti-fuse type OTP memory cell includes a first anti-fuse transistor having a first channel width, a first selection transistor sharing a first active region with the first anti-fuse transistor and having a second channel width that is greater than the first channel width, a second anti-fuse transistor sharing a program gate with the first anti-fuse transistor and having a third channel width, and a second selection transistor sharing a second active region with the second anti-fuse transistor and having a fourth channel width that is greater than the third channel width.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 16, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sung Kun Park
  • Patent number: 9406380
    Abstract: Provided is an electronic device including a semiconductor memory unit. The semiconductor memory unit may include: a storage cell comprising a variable resistance element; a first selecting element coupled to one end of the storage cell and having a threshold voltage set to a first voltage; and a second selecting element coupled to the other end of the storage cell and having a threshold voltage set to a second voltage higher than the first voltage.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: August 2, 2016
    Assignee: SK hynix Inc.
    Inventors: Jae-Yun Yi, Sung-Woong Chung, Seok-Pyo Song
  • Patent number: 9349878
    Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: May 24, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
  • Patent number: 9318408
    Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the second clock distribution structure is connected to the first clock distribution structure with a plurality of through layer vias, and where the second transistors are aligned to the first transistors with less than 100 nm alignment error.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: April 19, 2016
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 9318181
    Abstract: A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-Young Seo, Yong-Kyu Lee, Choong-Jae Lee, Kee-Moon Chun, Hee-Seog Jeon
  • Patent number: 9218868
    Abstract: A magnetic memory according to an embodiment includes: a plurality of memory cells, each memory cell including a first MTJ element and a first selection unit; a pair of a first and second bit lines provided to each column of the memory cells; a word line provided to each row of the memory cells; an equalizer circuit provided to each column of the memory cells, and to connect between the first and second bit lines; and a control circuit that sets the first and second bit lines connected to a selected memory cell to be a first and second potentials to conduct a write operation, and after the write operation, transmits a control signal to the equalizer circuit between the first and second bit lines to activate the equalizer circuit to equalize potentials of the first bit line and the second bit line, thereby bringing into floating states.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: December 22, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroki Noguchi, Keiko Abe, Shinobu Fujita
  • Patent number: 9196377
    Abstract: An anti-fuse type OTP memory cell includes a first active region having a first program region with a first width and a first selection region with a second width that is greater than the first width, a second active region spaced apart from the first active region and having a second program region with a third width and a second selection region with a fourth width that is greater than the third width, a program gate intersecting the first program region and the second program region, a first selection gate intersecting the first selection region, and a second selection gate intersecting the second selection region.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: November 24, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sung Kun Park
  • Patent number: 9041084
    Abstract: Embodiments relate to a method of forming a memory array, comprising: forming a collector layer; forming a plurality of collector regions in the collector layer; forming a plurality of base regions over the collector region; forming a plurality of emitter regions over the base regions; forming a plurality of memory elements over the emitter regions, wherein the collector regions, base regions and emitter regions form heterojunction bipolar transistors.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventor: Armin Tilke
  • Patent number: 9029827
    Abstract: In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Unity Semiconductor Corporation
    Inventors: Lidia Vereen, Bruce Lynn Bateman, Louis Parrillo, Elizabeth Friend, David Eggleston
  • Patent number: 9029829
    Abstract: A memory cell includes a first resistive switching device having a first terminal and a second terminal, a switching device having a first terminal and a second terminal, and an access device having a first access terminal and a second access terminal. The first access terminal is coupled to the first terminal of the first resistive switching device and the first terminal of the switching device.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: May 12, 2015
    Assignee: Adesto Technologies Corporation
    Inventors: Juan Pablo Saenz Echeverry, Deepak Kamalanathan
  • Patent number: 9006793
    Abstract: A stacking structure in which a stacked body (21) including a first conductive layer (13), a semiconductor layer (17), and a second conductive layer (18) and an interlayer insulating film (16) are alternately stacked in parallel to a substrate, a plurality of columnar electrodes (12) arranged so as to penetrated through the stacking structure in a stacking direction, a variable resistance layer (14) which is disposed between the columnar electrode (12) and the first conductive layer (13) and which has a resistance value that reversibly changes according to an application of an electric signal are included. The variable resistance layer (14) is formed by oxidizing part of the first conductive layer (13). The variable resistance layer (14) and an insulating film for electrically separating the semiconductor layer (17) and the second conductive layer (18) from the columnar electrode (12) are simultaneously formed in a single oxidation process.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 14, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Zhiqiang Wei, Takeshi Takagi, Mitsuteru Iijima
  • Patent number: 9000411
    Abstract: Various embodiments of the present invention are direct to nanoscale, reconfigurable, two-terminal memristor devices. In one aspect, a device (400) includes an active region (402) for controlling the flow of charge carriers between a first electrode (104) and a second electrode (106). The active region is disposed between the first electrode and the second electrode and includes a storage material. Excess mobile oxygen ions formed within the active region are stored in the storage material by applying a first voltage.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: April 7, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhiyong Li, Alexandre M. Bratkovski, Jianhua Yang
  • Patent number: 8987695
    Abstract: A method for fabricating a variable resistance device includes: providing a first insulating layer having a first electrode; forming a first oxide layer including a variable resistance material over the first electrode and the first insulating layer; forming a sacrifice pattern over the first oxide layer; forming a second oxide layer by reacting the first oxide layer exposed by the sacrifice pattern with oxygen; removing the sacrifice pattern; and forming a second electrode over the second oxide layer and the first oxide layer so as to be coupled to the first oxide layer.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 24, 2015
    Assignee: SK hynix Inc.
    Inventor: Hye-Jung Choi
  • Patent number: 8952349
    Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 10, 2015
    Assignee: Crossbar, Inc.
    Inventors: Wei Lu, Sung Hyun Jo
  • Patent number: 8932900
    Abstract: A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsun-Kai Tsao, Ming-Huei Shen, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 8912515
    Abstract: A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: December 16, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8885381
    Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: November 11, 2014
    Assignee: Sandisk 3D LLC
    Inventor: Roy E. Scheuerlein
  • Patent number: 8860223
    Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Cristina Casellato, Carmela Cupeta, Michele Magistretti, Fabio Pellizzer, Roberto Somaschini
  • Patent number: 8847196
    Abstract: Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Matthew N. Rocklein, D. V. Nirmal Ramaswamy
  • Patent number: 8848415
    Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: September 30, 2014
    Assignee: Sandisk 3D LLC
    Inventors: Roy E. Scheuerlein, Tianhong Yan
  • Patent number: 8841646
    Abstract: Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.
    Type: Grant
    Filed: October 6, 2013
    Date of Patent: September 23, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Akio Shima, Satoru Hanzawa, Takashi Kobayashi, Masaharu Kinoshita, Norikatsu Takaura
  • Patent number: 8835897
    Abstract: A nonvolatile memory device according to an embodiment of the present invention includes: a first wire embedded in a first wiring groove extending in an X direction formed in a first interlayer insulating film; a second interlayer insulating film formed above the first interlayer insulating film; a second wire embedded in a second wiring groove extending in a Y direction formed in the second interlayer insulating film; and a variable resistance memory cell including a variable resistive layer and a rectifying layer arranged to be held between the first wire and the second wire in a position where the first wire and the second wire intersect. A dimension in a plane perpendicular to a thickness direction of the variable resistance memory cell is specified by widths of the first and second wires.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mutsumi Okajima
  • Patent number: 8816497
    Abstract: An electronic component includes a III-N transistor and a III-N rectifying device both encased in a single package. A gate electrode of the III-N transistor is electrically connected to a first lead of the single package or to a conductive structural portion of the single package, a drain electrode of the III-N transistor is electrically connected to a second lead of the single package and to a first electrode of the III-N rectifying device, and a second electrode of the III-N rectifying device is electrically connected to a third lead of the single package.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: August 26, 2014
    Assignee: Transphorm Inc.
    Inventor: Yifeng Wu
  • Patent number: 8809831
    Abstract: A switching device includes a first dielectric material formed overlying a substrate. A bottom wiring material and a switching material are sequentially formed overlying the first dielectric material. The bottom wiring material and the switching material are patterned and etched to form a first structure having a top surface region and a side region. The first structure includes a bottom wiring structure and a switching element having the top surface region including an exposed region. A second dielectric material is formed overlying the first structure. A first opening region is formed in a portion of the second dielectric layer to expose a portion of the top surface region. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying the top surface region to be directly contact with the switching element.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: August 19, 2014
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Patent number: 8802453
    Abstract: A phase change random access memory includes a semiconductor substrate having a bottom electrode formed over the semiconductor substrate; and a phase change layer formed over the bottom electrode. The phase change layer a first phase change layer formed over the bottom electrode and including at least one of a first element, a second element, and a third element; and a second phase change layer formed over a surface of the first phase change layer and formed of the first element to prevent an area of the first phase change layer from increasing through diffusion.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: August 12, 2014
    Assignee: SK Hynix Inc.
    Inventor: Keun Lee
  • Patent number: 8796658
    Abstract: A resistive memory device includes a first metallic layer comprising a source of positive metallic ions, a switching media having an upper surface and a lower surface, wherein the upper surface is adjacent to the first metallic layer, wherein the switching media comprises conductive filaments comprising positive metallic ions from the source of positive metallic ions formed from the upper surface towards the lower surface, a semiconductor substrate, a second metallic layer disposed above the semiconductor substrate, a non-metallic conductive layer disposed above the second metallic layer, and an interface region between the non-metallic conductive layer and the switching media having a negative ionic charge.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 5, 2014
    Assignee: Crossbar, Inc.
    Inventors: Hagop Nazarian, Sung Hyun Jo
  • Patent number: 8785901
    Abstract: Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junho Jeong, Sukhun Choi, Jangeun Lee, Kyunghyun Kim, Sechung Oh, Kyungtae Nam
  • Patent number: 8779555
    Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Po-Tao Chu
  • Patent number: 8772754
    Abstract: A method of manufacturing a semiconductor storage device according to an embodiment includes: stacking a first wiring layer; stacking a memory cell layer on the first wiring layer; and stacking a stopper film on the memory cell layer. The method of manufacturing a semiconductor storage device also includes: etching the stopper film, the memory cell layer, and the first wiring layer; polishing an interlayer insulating film to the stopper film after burying the stopper film, the memory cell layer, and the first wiring layer with the interlayer insulating film; performing a nitridation process to the stopper film and the interlayer insulating film to form an adjustment film and a block film on surfaces of the stopper film and the interlayer insulating film, respectively; and forming a second wiring layer on the adjustment film, the second wiring layer being electrically connected to the adjustment film.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Murato Kawai
  • Patent number: 8711613
    Abstract: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: April 29, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Mahmud Assar
  • Patent number: RE47506
    Abstract: A variable resistance memory device includes a plurality of column selection switches, a plurality of variable resistance memory cells configured to be stacked and selected by the plurality of column selection switches, and a bit line connected to the plurality of variable resistance memory cells. Each of the plurality of variable resistance memory cells includes an ovonic threshold switch (OTS) element selectively driven by a plurality of word lines arranged to be stacked and a variable resistor connected in parallel to the OTS element.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventor: Nam Kyun Park