Including Only Passive Thin-film Or Thick-film Elements On A Common Insulating Substrate (epo) Patents (Class 257/E27.114)
  • Patent number: 10860906
    Abstract: A method for manufacturing a portable data carrier by means of a continuous manufacturing method, comprises the steps: providing at least one foil as a rolled good, unrolling at least one first foil, with at least a first foil being coated at least partly with an adhesive on at least one side, with at least the first foil being scored on at least one side along at least one creasing edge, with at least the first foil being folded up in precise fit along at least one creasing edge and bonded, with the foil being folded up in the direction of the side which is coated with adhesive, with the side coated with adhesive being arranged on the opposite side of the foil which has at least one scored creasing edge along which it is folded.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: December 8, 2020
    Assignee: GIESECKE+DEVRIENT MOBILE SECURITY GMBH
    Inventors: Stefan Bannert, Peter Kaufmann, Lucas Perlitz, Thomas Tarantino, Robert Griesmeier, Tatjana Mosthof, Cordula Regensburger
  • Patent number: 10818424
    Abstract: A coil component includes: a body in which a support member is disposed; and first and second coil conductors formed on first and second surfaces of the support member, respectively, the second surface of the support member opposing the first surface thereof, and including first and second lead portions extended to be exposed to the outside of the body, respectively. The first and second lead portions are formed in corner regions of the body.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chan Yoon, Young Ghyu Ahn, Dong Hwan Lee, Jin Ho Ku
  • Patent number: 10817763
    Abstract: A method for manufacturing a portable data carrier by means of a continuous manufacturing method, comprises the steps: providing at least one foil as a rolled good, unrolling at least one first foil, with at least a first foil being coated at least partly with an adhesive on at least one side, with at least the first foil being scored on at least one side along at least one creasing edge, with at least the first foil being folded up in precise fit along at least one creasing edge and bonded, with the foil being folded up in the direction of the side which is coated with adhesive, with the side coated with adhesive being arranged on the opposite side of the foil which has at least one scored creasing edge along which it is folded.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: October 27, 2020
    Assignee: GIESECKE+DEVRIENT MOBILE SECURITY GMBH
    Inventors: Stefan Bannert, Peter Kaufmann, Lucas Perlitz, Thomas Tarantino, Robert Griesmeier, Tatjana Mosthof, Cordula Regensburger
  • Patent number: 10783415
    Abstract: A method for manufacturing a portable data carrier by means of a continuous manufacturing method, comprises the steps: providing at least one foil as a rolled good, unrolling at least one first foil, with at least a first foil being coated at least partly with an adhesive on at least one side, with at least the first foil being scored on at least one side along at least one creasing edge, with at least the first foil being folded up in precise fit along at least one creasing edge and bonded, with the foil being folded up in the direction of the side which is coated with adhesive, with the side coated with adhesive being arranged on the opposite side of the foil which has at least one scored creasing edge along which it is folded.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 22, 2020
    Assignee: GIESECKE+DEVRIENT MOBILE SECURITY GMBH
    Inventors: Stefan Bannert, Peter Kaufmann, Lucas Perlitz, Thomas Tarantino, Robert Griesmeier, Tatjana Mosthof, Cordula Regensburger
  • Patent number: 10770439
    Abstract: An electronic module comprising a first electronic unit 51 which has a first insulating substrate 61 and a first electronic element 41 provided on the first insulating substrate 61 via a first conductor layer 21, a second electronic unit 52 which has a second insulating substrate 62 and a second electronic element 42 provided on the second insulating substrate 62 via a second conductor layer 22, a connecting body 29 provided between the first electronic unit 51 and the second electronic unit 52 and a coil 70 wound around the connecting body 29.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: September 8, 2020
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Junya Yuguchi, Kousuke Ikeda, Kenichi Suzuki
  • Patent number: 10640879
    Abstract: Devices including high-aspect ratio electroplated structures and methods of forming high-aspect ratio electroplated structures are described. A method for manufacturing metal structures includes providing a substrate having a metal base characterized by a height to width aspect ratio A/B and electroplating a metal crown on the base to form the metal structure with a height to width aspect ratio A/S greater than the aspect ratio A/B of the base.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: May 5, 2020
    Assignee: Hutchinson Technology Incorporated
    Inventors: Douglas P. Riemer, Kurt C. Swanson, Peter F. Ladwig
  • Patent number: 10547098
    Abstract: A double loop antenna includes a source loop comprising: a spiral-shaped conductive source coil pattern disposed on a top surface of a board, and a source capacitor pattern comprising symmetrical conductive patterns disposed on the top surface and a bottom surface of the board; and a resonance loop comprising: a spiral-shaped conductive resonance coil pattern disposed on the bottom surface of the board, and a resonance capacitor pattern comprising symmetrical conductive patterns disposed on the top surface and the bottom surface of the board, wherein the source coil pattern and the resonance coil pattern are formed on different surfaces of the board.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 28, 2020
    Assignee: WITS Co., Ltd.
    Inventors: Sang Beom Lee, Hyung Wook Cho, Jun Seung Yi, Yu Jin Lee, Jae Suk Sung, Dae Ki Lim, Seung Hun Ryu, Ki Won Chang, Jae Hyoung Cho, Si Hyung Kim
  • Patent number: 10447229
    Abstract: A matching module includes an inductor pattern including a first inductor pattern and a second inductor pattern, each respectively provided in a spiral shape, and a connection pattern connecting the first inductor pattern and the second inductor pattern and provided in a central region of a dielectric sheet, and a capacitor pattern provided in an edge region of the dielectric sheet and configured to form mutual capacitance with the inductor pattern, wherein rotational directions of the first inductor pattern and the second inductor pattern that are provided in the spiral shape are the same.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 15, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jung Woo Sung, Dong Hoe Kim
  • Patent number: 10278287
    Abstract: There is provided a smart package and monitoring system having a status indicator and a method of making the same. The smart package includes an electronic sensor monitoring tag having re-usable electronic circuitry and power source along with a conductive grid printed on a thin flexible substrate and connected to the tag so the tag and grid are in electrical continuity to form a monitoring device. The conductive grid is aligned with an opening of the smart package. The smart package can also include an optical ink indicator configured to display the status of the package. A multiplexer can be used to connect the tag to the conductive grid. The conductive grid can include capacitive sensors formed on a thin plastic layer and positioned so as to form a capacitive element with the conductive side of the blister.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: April 30, 2019
    Assignee: Intelligent Devices Sezc Inc.
    Inventors: Allan Wilson, Michael Petersen, Dean Brotzel
  • Patent number: 10263467
    Abstract: Provided is a wireless power antenna for wirelessly transmitting, receiving, or relaying power, the wireless power antenna comprising an insulating sheet and a wireless power coil including a split pattern unit including a plurality of patterns spaced from each other in at least a region thereof in a widthwise direction, wherein the split pattern unit is disposed on both a top surface and a bottom surface of the insulating sheet.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: April 16, 2019
    Assignee: LS CABLE & SYSTEM LTD.
    Inventors: Sung-Hoon Moon, Heung-kyu Lee, Ji-Hyung Lee, Min-Seok Han, Lae-Hyuk Park, Young-Sun Kim, Un-Kyu Park, Sung-Han You
  • Patent number: 10111330
    Abstract: A printed circuit board according to an embodiment of the present invention includes a base film having an insulating property, and a conductive pattern formed on at least one of surfaces of the base film, wherein at least a portion of the conductive pattern includes a core body, and a shrink layer formed by plating on an outer surface of the core body. The portion of the conductive pattern preferably has a striped configuration or a spiral configuration. The portion of the conductive pattern preferably has an average circuit gap width of 30 ?m or less. The portion of the conductive pattern preferably has an average aspect ratio of 0.5 or more. The plating is preferably electroplating or electroless plating.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: October 23, 2018
    Assignee: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Hiroshi Ueda, Kousuke Miura
  • Patent number: 9887583
    Abstract: When a portable electronic appliance is provided with two systems, a wireless power-feeding system and a wireless communication system, each system requires two power-receiving devices, a coil and an antenna, leading to a problem of increased electronic appliance size and cost. Wireless power feeding employs the resonance method and uses a resonance coil using the resonance method and a power-receiving coil that receives power from the resonance coil. At least one of the resonance coil and the power-receiving coil can also be used as an antenna for wireless communication. Thus, a power-receiving device that can be used for two systems, wireless power feeding and wireless communication, can be provided.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: February 6, 2018
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Koichiro Kamata
  • Patent number: 9740976
    Abstract: An RFID tag includes a core formed by a first elastic material and having a first surface, a second surface on an opposite side of the first surface, and a pair of end parts provided on mutually opposite sides and connecting to the first surface and the second surface. The RFID tag further includes a metal layer provided on the first surface, a semiconductor chip provided on the second surface, and a dipole antenna provided on the second surface and electrically connected to the semiconductor chip. One of the metal layer and the dipole antenna is folded at folded parts at the pair of end parts, and the metal layer and the dipole antenna overlap at the folded parts.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: August 22, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Noritsugu Ozaki, Shunji Baba, Takayoshi Matsumura
  • Patent number: 9647346
    Abstract: An omnidirectional antenna is provided. The omnidirectional antenna includes a spiral antenna including a substrate, at least one upper antenna pattern formed on the substrate, and at least one lower antenna pattern formed under the substrate and connected to the upper antenna pattern; and a monopole antenna that supports the spiral antenna and that is connected to the spiral antenna. Therefore, by forming an omnidirectional antenna in a spiral antenna having an upper antenna pattern and a lower antenna pattern at an upper surface and a lower surface, respectively, of a substrate, three-dimensional current flow is available and thus omnidirectional radiation characteristics may be exhibited.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: May 9, 2017
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Juderk Park, Nae-soo Kim, Cheol Sig Pyo
  • Patent number: 9633947
    Abstract: A method includes forming a folding template in a first dielectric layer. The folding template has a plurality of surfaces that are positioned in different planes. A ballistic conductor line is formed on the plurality of surfaces of the folding template. A device includes a first dielectric layer and a vertically folded line disposed in the first dielectric layer, the vertically folded line including a ballistic conductor material.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 9380698
    Abstract: An electronic patch includes a foldable circuit layer that includes a foldable network that includes comprising: a plurality of electronic modules comprising a plurality of electronic components, and flexible straps that connect the plurality of electronic modules, wherein the flexible straps comprise conductive circuit that are conductively connected with the plurality of electronic components in the plurality of electronic modules. Neighboring electronic modules can undulate in opposite directions normal to the foldable circuit layer. The electronic patch also includes an elastic layer that encloses the foldable circuit layer.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: June 28, 2016
    Assignee: VivaLnk, Inc.
    Inventors: Jiang Li, Junfeng Mei
  • Patent number: 9378450
    Abstract: An electronic patch includes a first circuit layer comprising a substantially flat first substrate and a first conductive circuit, a second circuit layer comprising a substantially flat second substrate and a second conductive circuit, and an undulated ribbon that connects the first circuit layer and the second circuit layer. The undulated ribbon includes a third conductive circuit that connects the first conductive circuit and the second conductive circuit. An elastic layer encloses the first circuit layer, the second circuit layer, and the undulated ribbons.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: June 28, 2016
    Assignee: VivaLnk, Inc
    Inventors: Junfeng Mei, Jiang Li
  • Patent number: 9029951
    Abstract: A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.
    Type: Grant
    Filed: July 22, 2012
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuyuki Horita, Toshiaki Iwamatsu, Hideki Makiyama
  • Patent number: 8872248
    Abstract: An integrated circuit includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. An Inter-Layer Dielectric (ILD) is overlying the insulation region. A capacitor includes a first capacitor plate including a first slot contact plug, and a second capacitor plate including a second slot contact plug. The first and the second contact plugs include portions in the ILD. A portion of the ILD between vertical surfaces of the first slot contact plug and the second slot contact plug acts as a capacitor insulator of the capacitor.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hong Pan, Jen-Pan Wang
  • Patent number: 8816443
    Abstract: An epitaxial device module monolithically integrated with a CMOS structure in a bulk or thick-film SOI substrate, comprising an active area on which epitaxial layers are formed by selective or non-selective epitaxial growth and a separate active area in which the CMOS structure is formed. A hard mask for epitaxy having an opening therein provides self-alignment for optional ion implants into the substrate. The ion-implanted region overlaps the active region underneath the epitaxial layer, a portion of the source/drain region of the CMOS structure and the isolation region separating the two active areas, thereby establishing a conductive path underneath the isolation region between the two active areas.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: August 26, 2014
    Assignee: Quantum Semiconductor LLC
    Inventors: Carlos J. R. P. Augusto, Lynn Forester
  • Patent number: 8796679
    Abstract: A method of manufacturing an IGZO active layer includes depositing ions including In, Ga, and Zn from a first target, and depositing ions including In from a second target having a different atomic composition from the first target. The deposition of ions from the second target may be controlled to adjust an atomic % of In in the IGZO layer to be about 45 atomic % to about 80 atomic %.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-han Jeong, Jae-kyeong Jeong, Jin-seong Park, Yeon-gon Mo, Hui-won Yang, Min-kyu Kim, Tae-kyung Ahn, Hyun-soo Shin, Hun jung Lee
  • Patent number: 8735188
    Abstract: An atomic layer deposition apparatus and a sealing method of an organic light emitting device using the same are disclosed. In one embodiment, the atomic layer deposition apparatus improves a structure of the purge gas injection nozzle so as to increase the exhaust efficiency of the purge gas in an atomic layer deposition process, which increases a speed of a purge process. As a result, it is possible to improve a deposition speed and a quality of a sealing film when a sealing process for sealing the organic light emitting device is implemented by using the atomic layer deposition.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Hun Kim, Sang-Joon Seo, Jin-Kwang Kim, Jun-Hyuk Cheon
  • Patent number: 8669637
    Abstract: An integrated passive device system is disclosed including forming a first dielectric layer over a semiconductor substrate, depositing a metal capacitor layer on the first dielectric layer, forming a second dielectric layer over the metal capacitor layer, and depositing a metal layer over the second dielectric layer for forming the integrated capacitor, an integrated resistor, an integrated inductor, or a combination thereof.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: March 11, 2014
    Assignee: Stats ChipPac Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Robert Charles Frye, Pandi Chelvam Marimuthu
  • Patent number: 8643144
    Abstract: A current sense resistor integrated with an integrated circuit die housed in a chip-scale semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer having an array of metal pillars extending therefrom. The metal pillars are to be electrically connected to a first conductive electrode and a second conductive electrode external to the chip-scale semiconductor package where the first conductive electrode and the second conductive electrode are physically separated from each other by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second conductive electrodes. In some embodiments, a semiconductor device including an integrated circuit die housed in a chip-scale semiconductor package includes a current sense resistor formed in a metal layer formed over a passivation layer of the integrated circuit die.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: February 4, 2014
    Assignee: Micrel, Inc.
    Inventor: Cameron Jackson
  • Patent number: 8531004
    Abstract: A current sense resistor integrated with an integrated circuit die where the integrated circuit die is housed in a chip-scale semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer has an array of metal pillars extending therefrom. The metal pillars are to be electrically connected to a first conductive trace portion and a second conductive trace portion formed on a printed circuit board where the first conductive trace portion and the second conductive trace portion are electrically isolated from each other and physically separated by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second metal trace portions, the first and second conductive trace portions forming terminals of the current sense resistor.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: September 10, 2013
    Assignee: Micrel, Inc.
    Inventor: Cameron Jackson
  • Patent number: 8486796
    Abstract: A method of forming a semiconductor structure includes: forming a resistor over a substrate; forming at least one first contact in contact with the resistor; and forming at least one second contact in contact with the resistor. The resistor is structured and arranged such that current flows from the at least one first contact to the at least one second contact through a central portion of the resistor. The resistor includes at least one extension extending laterally outward from the central portion in a direction parallel to the current flow. The method includes sizing the at least one extension based on a thermal diffusion length of the resistor.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: David L. Harmon, Joseph M. Lukaitis, Stewart E. Rauch, III, Robert R. Robison, Dustin K. Slisher, Jeffrey H. Sloan, Timothy D. Sullivan, Kimball M. Watson
  • Publication number: 20120319241
    Abstract: The resistor segments may be placed in a spatial region of an integrated circuit. Junctions formed between the resistor segments and conductors may be placed at locations such that each junction has a paired counterpart of the same type that is spaced to form respective same junction type centroids (i.e., geometric centers). The different type centroids may be substantially coincident, meaning that the centroids substantially overlap. In this manner, junction voltages (or offset voltages) generated by one pair of junctions may cancel out the junction voltages generated by another pair of junctions in the resistor circuit.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 20, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventors: Yijing LIN, Damien MCCARTNEY
  • Patent number: 8299574
    Abstract: Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: October 30, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Todd Jackson Plum
  • Patent number: 8263437
    Abstract: A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: September 11, 2012
    Assignee: STATS ChiPAC, Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 8227877
    Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: July 24, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Tung Lee, Shih-Chin Lien, Chia-Huan Chang
  • Patent number: 8174085
    Abstract: A method of manufacturing an MEMS sensor according to the present invention includes the steps of: forming a first sacrificial layer on one surface of a substrate; forming a lower electrode on the first sacrificial layer; forming a second sacrificial layer made of a metallic material on the first sacrificial layer to cover the lower electrode; forming an upper electrode made of a metallic material on the second sacrificial layer; forming a protective film made of a nonmetallic material on the substrate to collectively cover the first sacrificial layer, the second sacrificial layer and the upper electrode; and removing at least the second sacrificial layer by forming a through-hole in the protective film and supplying an etchant to the inner side of the protective film through the through-hole.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: May 8, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Goro Nakatani
  • Patent number: 8039377
    Abstract: Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: October 18, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Todd Jackson Plum
  • Patent number: 8017513
    Abstract: A method of manufacturing an IGZO active layer includes depositing ions including In, Ga, and Zn from a first target, and depositing ions including In from a second target having a different atomic composition from the first target. The deposition of ions from the second target may be controlled to adjust an atomic % of In in the IGZO layer to be about 45 atomic % to about 80 atomic %.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: September 13, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Jong-han Jeong, Jae-kyeong Jeong, Jin-seong Park, Yeon-gon Mo, Hui-won Yang, Min-kyu Kim, Tae-kyung Ahn, Hyun-soo Shin, Hun Jung Lee
  • Patent number: 7902615
    Abstract: A micromechanical structure and a method for producing a micromechanical structure are provided, the micromechanical structure being configured for receiving and/or generating acoustic signals in a medium at least partially surrounding the structure. The structure includes a first counterelement that has first openings and essentially forms a first side of the structure, a second counterelement that has second openings and essentially forms a second side of the structure, and an essentially closed diaphragm disposed between the first counterelement and the second counterelement.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: March 8, 2011
    Assignee: Robert Bosch GmbH
    Inventors: Roman Schlosser, Stefan Weiss, Frank Fischer, Christoph Schelling
  • Publication number: 20110018098
    Abstract: Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.
    Type: Application
    Filed: October 6, 2010
    Publication date: January 27, 2011
    Applicant: Micron Technology, Inc.
    Inventor: Todd Jackson Plum
  • Publication number: 20100140714
    Abstract: Electronic elements (44, 44?, 44?) having an active device region (46) and integrated passive device (IPD) region (60) on a common substrate (45) preferably include a composite dielectric region (62, 62?, 62?) in the IPD region underlying the IPD (35) to reduce electromagnetic (E-M) (33) coupling to the substrate (45). Mechanical stress created by plain dielectric regions (36?) and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (65, 65?, 65?) in the composite dielectric region (62, 62?, 62?) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78?, 78?) in the composite dielectric region (62, 62?, 62?). For silicon substrates (45), non-single crystal silicon is suitable for the inclusions (65, 65?, 65?) and silicon oxide for the dielectric material (78, 78?, 78?).
    Type: Application
    Filed: December 4, 2008
    Publication date: June 10, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xiaowei Ren, Wayne R. Burger, Colin Kerr, Mark A. Bennett
  • Patent number: 7679084
    Abstract: A TFT array panel and a method for fabricating the same is disclosed, wherein an adhesion force between an elongated wire and a TFT array panel pad is improved by increasing the contact area of a bonding pad. The TFT array panel pad includes a first conductive layer formed in a pad region on an insulating substrate. The first conductive layer includes a plurality of conductive islands and holes. A second conductive layer is formed over and covers the first conductive layer.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: March 16, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Kyo Seop Choo, June Ho Park
  • Publication number: 20100059854
    Abstract: A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant.
    Type: Application
    Filed: September 5, 2008
    Publication date: March 11, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 7655497
    Abstract: A method for growth of an alloy for use in a nanostructure, to provide a resulting nanostructure compound including at least one of GexTey, InxSby, InxSey, SbxTey, GaxSby, GexSby,Tez, InxSbyTez, GaxSeyTez, SnxSbyTez, InxSbyGez, GewSnxSbyTez, GewSbxSeyTez, and TewGexSbySz, where w, x, y and z are numbers consistent with oxidization states (2, 3, 4, 5, 6) of the corresponding elements. The melt temperatures for some of the resulting compounds are in a range 330-420° C., or even lower with some compounds.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: February 2, 2010
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Bin Yu, Xuhui Sun, Meyya Meyyappan
  • Patent number: 7598159
    Abstract: A method of fabricating a thin film transistor substrate includes forming a gate wiring on an insulating substrate and forming a gate insulating layer on the gate wiring; performing a first hydrogen plasma treatment with respect to the gate insulating layer; forming a first active layer with a first thickness at a first deposition rate on the gate insulating layer; performing a second hydrogen plasma treatment with respect to the first active layer; and forming a second active layer with a second thickness greater than the first thickness at a second deposition rate greater than the first deposition rate, on the first active layer.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: October 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwa-yeul Oh, Byoung-june Kim, Sung-hoon Yang, Jae-ho Choi, Yong-mo Choi, Girotra Kunal
  • Publication number: 20090129142
    Abstract: A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.
    Type: Application
    Filed: January 22, 2009
    Publication date: May 21, 2009
    Inventors: Masanao Yamaoka, Kenichi Osada, Kiyoo Itoh, Takayuki Kawahara
  • Patent number: 7525140
    Abstract: In an embodiment, a substrate includes a thin film capacitor embedded within. In an embodiment, a plurality of adhesion holes extend through the thin film capacitor. These adhesion holes may improve the adhesion of the capacitor to other portions of the substrate.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: April 28, 2009
    Assignee: Intel Corporation
    Inventors: Yongki Min, John Guzek
  • Patent number: 7521770
    Abstract: An image capturing device includes an image sensor package and a lens module aligned with the image sensor package. The image sensor package includes a substrate, at least one passive component, an insulative layer, and an image sensor. The substrate has a surface facing an object side of the image capturing device, the surface defines a cavity therein. The at least one passive component is disposed within the cavity and electrically connected to the substrate. The insulative layer is received in the cavity and encases the at least one passive component. The image sensor is disposed on the insulative layer and electrically connected to the substrate. The holder has an end connecting with the barrel and an opposite end secured on the substrate.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: April 21, 2009
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Ying-Cheng Wu, Kun-Hsiao Liu
  • Publication number: 20090078997
    Abstract: A first high-k gate dielectric layer and a first metal gate layer are formed on first and second semiconductor fins. A first metal gate ring is formed on the first semiconductor fin. In one embodiment, the first high-k gate dielectric layer remains on the second semiconductor fin. A second metal gate layer and a silicon containing layer are deposited and patterned to form gate electrodes. In another embodiment, a second high-k dielectric layer replaces the first high-k dielectric layer over the second semiconductor fin, followed by formation of a second metal gate layer. A first electrode comprising a first gate dielectric and a first metal gate is formed on the first semiconductor fin, while a second electrode comprising a second gate dielectric and a second metal gate is formed on the second semiconductor fin. Absence of high-k gate dielectric materials on a gate wiring prevents increase in parasitic resistance.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian J. Greene, Mahender Kumar
  • Publication number: 20090020753
    Abstract: A method of manufacturing an IGZO active layer includes depositing ions including In, Ga, and Zn from a first target, and depositing ions including In from a second target having a different atomic composition from the first target. The deposition of ions from the second target may be controlled to adjust an atomic % of In in the IGZO layer to be about 45 atomic % to about 80 atomic %.
    Type: Application
    Filed: July 15, 2008
    Publication date: January 22, 2009
    Inventors: Jong-han Jeong, Jae-kyeong Jeong, Jin-seong Park, Yeon-gon Mo, Hui-won Yang, Min-kyu Kim, Tae-kyung Ahn, Hyun-soo Shin, Hun jung Lee
  • Publication number: 20090001509
    Abstract: A circuit system includes: forming a first electrode over a substrate; applying a dielectric layer over the first electrode and the substrate; forming a second electrode over the dielectric layer; and forming a dielectric structure from the dielectric layer with the dielectric structure within a first horizontal boundary of the first electrode.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventor: Yaojian Lin
  • Publication number: 20080290414
    Abstract: A semiconductor device comprising a first transistor device and second transistor device both on a semiconductor substrate. The first transistor device has a first n-channel and a first p-channel and the second transistor device has a second n-channel and a second p-channel. Each of the p-channels and the n-channels have a long lateral axis that is aligned with a orientation plane of a silicon layer of the semiconductor substrate. The second p-channel and the first and second n-channels include the silicon layer configured as strained silicon. The first p-channel includes the silicon layer configured as relaxed silicon. Each of the n-channels contact gate structures that impart a tensile stress in the n-channels.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 27, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Weize Xiong, Cloves Rinn Cleavelin
  • Publication number: 20080277726
    Abstract: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. As a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. The FET device structures further contain stressed device channels, and gates with effective workfunctions of n+ Si and p+ Si values.
    Type: Application
    Filed: May 8, 2007
    Publication date: November 13, 2008
    Inventors: Bruce B. Doris, Eduard Albert Cartier, Barry Paul Linder, Vijay Narayanan, Vamsi Paruchuri, Mark Todhunter Robson, Michelle L. Steen, Ying Zhang
  • Publication number: 20080277724
    Abstract: An electronic device, such as a thin film transistor, is disclosed having a dielectric layer formed from a composition comprising a compound having at least one phenol group and at least one group containing comprising silicon. The resulting dielectric layer has good electrical properties.
    Type: Application
    Filed: May 7, 2007
    Publication date: November 13, 2008
    Inventors: Yu Qi, Yiliang Wu, Yuning Li, Beng S. Ong
  • Publication number: 20080268588
    Abstract: A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak