Abstract: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. As a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. The FET device structures further contain stressed device channels, and gates with effective workfunctions of n+ Si and p+ Si values.

Abstract: An electronic device, such as a thin film transistor, is disclosed having a dielectric layer formed from a composition comprising a compound having at least one phenol group and at least one group containing comprising silicon. The resulting dielectric layer has good electrical properties.

Abstract: A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region.

Abstract: A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.

Abstract: There is a FinFET device. The device has a silicon substrate, an oxide layer, and a polysilicone gate. The silicon substrate defines a planar body, a medial body, and a fin. The planar body, the medial body, and the fin are integrally connected. The medial body connects the planar body and the fine. The planar body extends generally around the medial body. The fin is situated to extend substantially from a first side of the substrate to an opposing second side of the substrate. The fin is substantially perpendicularly disposed with respect to the planar body. The first oxide layer is situated on the planar body between the planar body and the fine. The oxide layer extends substantially around the medial body. The polysilicone gate is situated on the oxide layer to extend substantially from a third side to an opposing fourth side of the substrate. The gate is situated to extend across the fin proximal to a medial portion of an upper surface of the fine. There is also a process for making a FinFET device.

Abstract: A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.

Abstract: A thin film transistor array panel is provided, which includes a substrate including a display region, a chip region, and a pad region; a plurality of signal lines formed on the substrate for electrically connecting the pad region to the chip region and the display region, wherein the signal lines have pads as an end portion and the pads are formed in the pad region; an insulating layer covering the signal lines and having a plurality of contact holes exposing the portions of the signal lines; a plurality of contact assistants formed on the insulating layer and connected to the pads through the contact holes; and a plurality of connection member respectively connected to the contact assistants and formed on the insulating layer for selectively electrically connecting the signal lines, wherein the insulating layer has a boundary line formed by etching, and the boundary line is crenellated.

Abstract: In a photoelectric converting film stack type solid-state image pickup device, a plurality of photoelectric converting film are stacked on a semiconductor substrate in which a signal readout circuit is formed, each of the photoelectric converting films is sandwiched between a common electrode film and pixel electrode films corresponding to respective pixels, and photo-charges generated in the photoelectric converting films are taken out through the pixel electrode films. In the solid-state image pickup device, a common electrode film for a first photoelectric converting film is used also as a common electrode film for a second photoelectric converting film, the first photoelectric converting film is stacked below the common electrode film, and the second photoelectric converting film is stacked above the common electrode film.

Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.

Abstract: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode.

Abstract: A semiconductor device having an SOI structure including a semiconductor substrate, a buried insulating layer and an SOI layer including, first and second element formation regions provided in said SOI layer, a partial isolation region including a partial insulating film provided in an upper layer portion of said SOI layer and a semiconductor region to be a part of said SOI layer which is provided under said partial insulating film and serving to isolate said first and second element formation regions from each other, and first and second MOS transistors formed in said first and second element formation regions, respectively, wherein at least one of a structure of a body region, a structure of a gate electrode and presence/absence of body potential fixation in said first and second MOS transistors is varied to make transistor characteristics of said first and second MOS transistors different from each other.

Abstract: Methods of forming thin-film transistor display devices including forming a gate line and a gate electrode on a face of a substrate and forming a semiconductor layer that is insulated from the gate line. A data line and a source/drain electrode are formed on the semiconductor layer. The data line and the source/drain electrode are formed as composites of at least two different metal conductive layers. A transparent pixel electrode is formed that is electrically coupled to the drain electrode.

Abstract: A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.

Abstract: A semiconductor device formed in a silicon-on-insulator substrate includes a silicon channel region located between silicon source and drain regions, and a low-carrier-concentration layer that underlies the channel region. The low-carrier-concentration layer makes contact with both the channel region and the source region. The channel region and the low-carrier-concentration layer are of the same conductive type, but the low-carrier-concentration layer is doped to have a lower carrier concentration than the channel region. The low-carrier-concentration layer eliminates the floating substrate effect, because carriers that would otherwise accumulate in the channel region can escape through the low-carrier-concentration layer into the source region.

Abstract: A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In the case of an electrically conductive hard mask, parts of the hard mask may remain in the circuit arrangement.

Abstract: An epitaxial device module monolithically integrated with a CMOS structure in a bulk or thick-film SOI substrate, comprising an active area on which epitaxial layers are formed by selective or non-selective epitaxial growth and a separate active area in which the CMOS structure is formed. A hard mask for epitaxy having an opening therein provides self-alignment for optional ion implants into the substrate. The ion-implanted region overlaps the active region underneath the epitaxial layer, a portion of the source/drain region of the CMOS structure and the isolation region separating the two active areas, thereby establishing a conductive path underneath the isolation region between the two active areas.

Abstract: A transistor having a gate electrode, a source electrode, a drain electrode, a dielectric material and a channel region disposed between the source electrode and drain electrode. The channel region includes a portion doped with an impurity to change the fixed charge density within the portion relative to a remainder of the channel region.

Abstract: A structure of semiconductor device including an insulation substrate is provided. A channel layer is disposed on the insulation substrate. A plurality of doped layers is disposed on the insulation substrate, and protrudes from the channel layer. The doped layers form at least two source/drain electrode (S/D electrode) pairs, and each of the S/D electrode pairs has a different extension direction with respect to the channel layer. A gate dielectric layer is disposed on the channel layer. A gate layer is disposed on the gate dielectric layer. Preferably, for example, the extension direction of at least one of the S/D electrode pairs is a first direction, and the extension direction of at least another one of the S/D electrode pairs is a second direction.

Abstract: A micromechanical cap structure and a corresponding manufacturing method are described. The micromechanical cap structure includes a first wafer with a micromechanical functional structure, and a second wafer to form a cap over the micromechanical functional structure. The first and second wafers have in their interior a support structure with a metal-semiconductor contact, and in their edge zone a bonding structure. The edge zone of the second wafer, when in the capped state, is arched in relation to the interior of the second wafer.

Abstract: The present invention provides a method for manufacturing massively and efficiently a minute device which can receive or send data in contact, preferably, out of contact by forming an integrated circuit which is formed by a thin film over a large glass substrate and by peeling the integrated circuit from the substrate. Especially, an integrated circuit which is formed by a thin film is extremely thin, and so there is a threat that the integrated circuit is flied when transporting, and so handling thereof is difficult. In accordance with the present invention, a separating layer (also referred to as a peeling layer) is damaged at a plurality of times by at least two different kinds of methods (a damage due to laser light irradiation, a damage due to etching, or a damage due to a physical means), subsequently, the layer to be peeled can be efficiently peeled from a substrate. Further, handling of individual devices becomes easy by arching the peeled device.

Abstract: An electroluminescent display device includes first and second substrates facing each other, data and gate lines crossing each other on the first substrate to define a plurality of pixel regions, a switching transistor connected to the gate and data lines, a driving transistor connected to the switching transistor, a dummy pattern on the first substrate, a connection electrode on the dummy pattern and connected to the driving transistor, a power line connected to the driving transistor, and an emitting diode on the second substrate and connected to the connection electrode.

Abstract: A flexible printed circuit board includes a substrate layer composed of insulating material, a protection circuit of a thin-film capacitor element, the protection circuit including a first wiring layer on the substrate layer, a dielectric layer, and a counter electrode layer. At least a portion of each of the first wiring layer and the counter electrode layer serves as a terminal. The front surface of each of the first wiring layer and the counter electrode layer, except the terminal portion, is covered with an insulating coating.

Abstract: A thin film transistor array including a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, an etch barrier layer and a plurality of pixel electrodes is provided. The scan lines and the data lines are disposed over the substrate to define a plurality of pixel areas. Each thin film transistor is disposed in one of the pixel areas and driven by the corresponding scan line and data line. The etch barrier layer including a plurality openings is disposed over the scan line or a common line. Each pixel electrode electrically connected to the corresponding thin film transistor is disposed in one of the pixel areas, wherein a portion of each pixel electrode is coupled to the corresponding scan line through one of the openings to form a storage capacitor. Furthermore, a fabricating method of the thin film array is also provided.