Imperfections Within Semiconductor Body (epo) Patents (Class 257/E29.107)
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Patent number: 12107123Abstract: A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.Type: GrantFiled: March 13, 2023Date of Patent: October 1, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takumi Fujimoto
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Patent number: 11990335Abstract: A process for fabricating a single-crystal semiconductor material of group 13 nitride, in particular GaN, including the steps of: deposition of at least one single-crystal layer by three-dimensional epitaxial growth on a starting substrate, the layer including areas resulting from the growth of basal facets, and areas resulting from the growth of facets of different orientations, called non-basal facets; supply of an n-dopant gas including a first chemical element selected from the chemical elements of group 16 of the periodic table, and at least one second chemical element selected from the chemical elements of group 14 of the periodic table, such that the concentration of the second element in the areas resulting from the growth of the basal facets is higher than 1.0×1017/cm3, and the concentration of the first element in the areas resulting from the growth of the non-basal facets is lower than 2.0×1018/cm3.Type: GrantFiled: December 18, 2019Date of Patent: May 21, 2024Assignee: IVWORKS CO., LTD.Inventors: Bernard Beaumont, Jean-Pierre Faurie, Vincent Gelly, Nabil Nahas, Florian Tendille
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Patent number: 11973147Abstract: A power semiconductor component for voltage limiting includes a rear-side base zone electrically contacted with a rear-side electrode and a front-side base zone electrically contacted with a front-side electrode. At least one switch-on structure is embedded at least into one of the rear-side base zone and the front-side base zone and is electrically contacted by the electrode contacting the embedding base zone. At least one triggering structure is provided as a breakdown structure of a first type, present between the front-side and rear-side electrodes. At least one further triggering structure is provided as a breakdown structure of a second type, present between the front-side and rear-side electrodes. The front-side and rear-side electrodes are each electrically conductively pressure-contacted by an electrically conductive contact plate at least one of which functions as a heat sink for dissipating heat generated in the semiconductor body.Type: GrantFiled: February 8, 2022Date of Patent: April 30, 2024Assignee: Infineon Technologies Bipolar GmbH & Co. KGInventors: Juergen Schiele, Reiner Barthelmess, Uwe Kellner-Werdehausen, Sebastian Paul Sommer
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Patent number: 8911518Abstract: The present disclosure relates generally to semiconductor techniques. More specifically, embodiments of the present disclosure provide methods for efficiently dicing substrates containing gallium and nitrogen material. Additionally, the present disclosure provides techniques resulting in an optical device comprising a substrate having a dislocation bundle center being used as a conductive region for a contact.Type: GrantFiled: June 7, 2012Date of Patent: December 16, 2014Assignee: Soraa, Inc.Inventors: Arpan Chakraborty, Michael R. Krames, Tal Margalith, Rafael Aldaz
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Patent number: 8854614Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.Type: GrantFiled: December 14, 2012Date of Patent: October 7, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hoon Kang, Taegon Kim, Hanmei Choi, Eunyoung Jo, Gonsu Kang, Sungho Kang, Sungho Heo
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Patent number: 8779552Abstract: An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 ?m from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 1017 and 1018 atoms/cm3.Type: GrantFiled: October 4, 2010Date of Patent: July 15, 2014Assignee: STMicroelectronics (Rousset) SASInventors: Pascal Fornara, Fabrice Marinet
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Patent number: 8754444Abstract: A semiconductor device includes a first device and a second device, which are implemented laterally next to each other in a substrate. A recombination zone is implemented in the substrate between the first device and the second device, so that diffusing charge carriers recombine between the first device and the second device.Type: GrantFiled: November 3, 2010Date of Patent: June 17, 2014Assignee: Infineon Technologies AGInventors: Rudolf Buchberger, Hans-Joachim Schulze
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Patent number: 8748298Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.Type: GrantFiled: January 31, 2008Date of Patent: June 10, 2014Assignee: International Rectifier CorporationInventors: Edwin L. Piner, John C. Roberts, Pradeep Rajagopal
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Patent number: 8664746Abstract: A silicon on insulater (SOI) wafer is provided. A dielectric layer is formed on an active silicon substrate of the wafer. The dielectric layer is patterned and etched to expose selected portions of the silicon substrate. Impurities are then introduced into the exposed portions of the silicon substrate to act as gettering regions. The dielectric layer is then removed and an epitaxial layer of silicon is grown on the silicon substrate. Trenches are etched in the epitaxial layer of silicon through the gettering regions, partially removing the gettering regions and any contaminants contained therein. Remaining portions of the gettering regions still act as gettering regions during subsequent process steps.Type: GrantFiled: September 20, 2011Date of Patent: March 4, 2014Assignee: STMicroelectronics Pte. Ltd.Inventors: Janusz Karol Korycinski, Wanliang Wen
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Patent number: 8597967Abstract: The present disclosure relates generally to semiconductor techniques. More specifically, embodiments of the present disclosure provide methods for efficiently dicing substrates containing gallium and nitrogen material. Additionally the present disclosure provide techniques resulting in a optical device comprising a substrate having three or more corners, where at least one of the corners is defined by a dislocation bundle characterized by a diameter of less than 100 microns, the gallium and nitrogen containing substrate having a predefined portion free from dislocation bundle centers, an active region containing one or more active layers, the active region being positioned within the predefined region; and a conductive region formed within the predefined region.Type: GrantFiled: November 17, 2011Date of Patent: December 3, 2013Assignee: Soraa, Inc.Inventors: Michael R. Krames, Tai Margalith, Rafael Aldaz
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Publication number: 20130069203Abstract: A silicon on insulater (SOI) wafer is provided. A dielectric layer is formed on an active silicon substrate of the wafer. The dielectric layer is patterned and etched to expose selected portions of the silicon substrate. Impurities are then introduced into the exposed portions of the silicon substrate to act as gettering regions. The dielectric layer is then removed and an epitaxial layer of silicon is grown on the silicon substrate. Trenches are etched in the epitaxial layer of silicon through the gettering regions, partially removing the gettering regions and any contaminants contained therein. Remaining portions of the gettering regions still act as gettering regions during subsequent process steps.Type: ApplicationFiled: September 20, 2011Publication date: March 21, 2013Applicant: STMICROELECTRONICS PTE. LTD.Inventors: Janusz Karol Korycinski, Wanliang Wen
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Publication number: 20120313139Abstract: In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N?-type drift region near the N-type buffer region remain to improve the switching speed, however the leak current increases by bringing a depletion layer into contact with the crystal defects at the off time. To avoid this, an IGBT is provided which includes an N-type buffer region having a higher concentration than that of an N?-type drift region and being in contact with a P-type on its backside, and a defect remaining region provided near the boundary between the N-type buffer region and the N?-type drift region. The N?-type drift region located on the front surface side with respect to the defect remaining region is provided with an N-type field stopping region having a higher concentration than that of the N?-type drift region.Type: ApplicationFiled: May 14, 2012Publication date: December 13, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hitoshi MATSUURA, Makoto KOSHIMIZU, Yoshito NAKAZAWA
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Publication number: 20120126371Abstract: A method for producing a conductive nitride semiconductor substrate circuit includes the steps of forming, on an underlying substrate, a mask including dot or stripe masking portions having a width or diameter of 10 to 100 ?m and arranged at a spacing of 250 to 10,000 ?m; growing a nitride semiconductor crystal on the underlying substrate by hydride vapor phase epitaxy (HVPE) at a growth temperature of 1,040° C. to 1,150° C. by supplying a group III source gas, a group V source gas, and a silicon-containing gas in a V/III ratio of 1 to 10; and removing the underlying substrate, thus forming a free-standing conductive nitride semiconductor crystal substrate having a resistivity r of 0.0015 ?cm?r?0.01 ?cm, a thickness of 100 ?m or more, and a radius of bow curvature U of 3.5 m?U?8 m.Type: ApplicationFiled: November 14, 2011Publication date: May 24, 2012Inventors: Fumitaka Sato, Seiji Nakahata, Makoto Kiyama
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Publication number: 20120119332Abstract: A process for producing a semiconductor-on-sapphire article, including: forming a barrier layer and a semiconductor layer on a sapphire substrate, the barrier layer being disposed between the sapphire substrate and the semiconductor layer to inhibit at least one of aluminium from the sapphire and extended defects arising from the sapphire-semiconductor interface from entering the semiconductor layer; wherein the semiconductor is at least one of silicon and a silicon-germanium alloy.Type: ApplicationFiled: June 11, 2010Publication date: May 17, 2012Inventor: Petar Branko Atanackovic
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Publication number: 20120049329Abstract: An aspect of the present invention relates to a method of analyzing an iron concentration of a boron-doped p-type silicon wafer by a SPV method, which comprises subjecting the wafer to Fe—B pair separation processing by irradiation with light and determining the iron concentration based on a change in a minority carrier diffusion length following the separation processing. The iron concentration is calculated with a calculation equation comprising a minority carrier diffusion length LAF1 measured after the separation processing, a minority carrier diffusion length LAF2 measured after a prescribed time has elapsed following measurement of LAF1, and dependence on time of recombination of Fe—B pairs separated by the separation processing. The calculation equation is derived by assuming that the irradiation with light causes boron atoms and oxygen atoms in the wafer to form a bonded product, and by assuming that the bonded product has identical influences on LAF1 and LAF2.Type: ApplicationFiled: July 27, 2011Publication date: March 1, 2012Applicant: SUMCO CORPORATIONInventors: Ryuji OHNO, Hisao IGA, Fumio Iga
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Publication number: 20120043644Abstract: A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process.Type: ApplicationFiled: March 25, 2010Publication date: February 23, 2012Applicant: SUMCO CORPORATIONInventors: Toshiaki Ono, Wataru Ito, Jun Fujise
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Patent number: 8043942Abstract: Disclosed is a method for producing core-shell nanowires in which an insulating film is previously patterned to block the contacts between nanowire cores and nanowire shells. According to the method, core-shell nanowires whose density and position is controllable can be produced in a simple manner. Further disclosed are nanowires produced by the method and a nanowire device comprising the nanowires. The use of the nanowires leads to an increase in the light emitting/receiving area of the device. Therefore, the device exhibits high luminance/efficiency characteristics.Type: GrantFiled: October 31, 2007Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Eun Kyung Lee, Jai Yong Han, Byoung Lyong Choi, Kyung Sang Cho
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Publication number: 20110233731Abstract: A semiconductor device, in which a plurality of crystal defects for controlling the life time of carries are distributed in a silicon substrate, is characterized in that the total number of the crystal defects that cause a trap level that differs from the energy level of the center of the band gap by less than 0.2 eV, is less than the number of the crystal defects that cause the trap level that is the closest to the energy level of the center of the band gap among trap levels that differ from the energy level of the center of the band gap by 0.2 eV or more.Type: ApplicationFiled: November 9, 2009Publication date: September 29, 2011Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Shinya Yamazaki
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SEMICONDUCTOR WAFERS WITH REDUCED ROLL-OFF AND BONDED AND UNBONDED SOI STRUCTURES PRODUCED FROM SAME
Publication number: 20110204471Abstract: The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided.Type: ApplicationFiled: February 4, 2011Publication date: August 25, 2011Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: John A. Pitney, Ichiro Yoshimura, Lu Fei -
Patent number: 7993990Abstract: A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device.Type: GrantFiled: April 9, 2010Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Shreesh Narasimha, Paul David Agnello, Xiaomeng Chen, Judson R. Holt, Mukesh Vijay Khare, Byeong Y. Kim, Devendra K. Sadana
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Publication number: 20110175203Abstract: An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×105-3.38×109/cm3 through first and second annealing steps. The first annealing step is performed at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. The second annealing step is performed at a second temperature higher than the first temperature in the atmosphere.Type: ApplicationFiled: March 29, 2011Publication date: July 21, 2011Applicant: MACRONIX International Co. Ltd.Inventors: CHUN-LING CHIANG, JUNG-YU HSIEH, LING-WU YANG
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Publication number: 20110156215Abstract: A silicon wafer includes BMDs with a diagonal length of from 10 nm to 50 nm, and has a density of BMD which exists at a depth of 50 ?m and deeper from the surface of the silicon wafer which is greater than or equal to 1×1011/cm3, and a ratio of the {111} plane of the BMD to the total planes surrounding the BMD, as an indication of the morphology of the BMD, is less than or equal to 0.3.Type: ApplicationFiled: November 30, 2010Publication date: June 30, 2011Applicant: SILTRONIC AGInventor: Katsuhiko Nakai
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Publication number: 20110115056Abstract: The structure comprises a closed cavity under a controlled atmosphere in which a monoblock getter with a first getter layer is arranged. The first getter layer presents at least first and second getter areas which have different activation temperatures. The second getter area is formed on an adjustment sub-layer of the getter material activation temperature.Type: ApplicationFiled: November 2, 2010Publication date: May 19, 2011Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Xavier Baillin
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Publication number: 20110079881Abstract: An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 ?m from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 1017 and 1018 atoms/cm3.Type: ApplicationFiled: October 4, 2010Publication date: April 7, 2011Applicant: STMicroelectronics (Rousset) SASInventors: Pascal Fornara, Fabrice Marinet
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Publication number: 20110049528Abstract: Reconditioned donor substrates that include a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and an additional layer deposited upon the opposite surface of the remainder substrate to increase its thickness and to form the reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers and is typically made from gallium nitride donor substrates.Type: ApplicationFiled: November 4, 2010Publication date: March 3, 2011Inventor: Frederic Dupont
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Publication number: 20100283126Abstract: A semiconductor device includes a semiconductor substrate that is made of either of silicon carbide (SiC) and gallium nitride (GaN), and has a defect region containing a crystal defect; a first insulating film that coats the defect region and is arranged on the semiconductor substrate; and a conductor film that electrically connects to a principal surface of the semiconductor substrate, the principal surface being exposed to a region that is not coated with the first insulating film.Type: ApplicationFiled: January 9, 2009Publication date: November 11, 2010Applicant: ROHM CO., LTDInventors: Tatsuya Kiriyama, Noriaki Kawamoto
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Publication number: 20100200956Abstract: A method for manufacturing the compound semiconductor substrate having a reduced dislocation density at an interface between a Si substrate. Contaminants, such as organic matter and metal, on a surface of a Si substrate are removed whereby a flat oxide film is formed. The oxide film on the surface is removed by using an aqueous hydrogen fluoride solution, whereby hydrogen termination treatment is performed. Immediately after being subjected to the hydrogen termination treatment the temperature of the Si substrate is raised in a vacuum apparatus. If the substrate temperature is raised without any operation, the termination hydrogen is released. Before the hydrogen is released, pre-irradiation with As is performed. Thus, an interface between the Si substrate and the compound semiconductor layer is prepared. Several minutes later, irradiation with Ga and As is performed. Thereby, the compound semiconductor is formed.Type: ApplicationFiled: September 12, 2008Publication date: August 12, 2010Inventors: Yoshihiko Shibata, Masatoshi Miyahara, Takashi Ikeda, Yoshihisa Kunimi
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Patent number: 7759711Abstract: Disclosed is a semiconductor device including: an N-type RESURF region formed in a P-type semiconductor substrate; a P-type base region formed in an upper portion of the semiconductor substrate so as to be adjacent to the RESURF region; an N-type emitter/source region formed in the base region so as to be apart from the RESURF region; a P-type base connection region formed in the base region so as to be adjacent to the emitter/source region; a gate insulating film and a gate electrode overlying the emitter/source region, the base region, and the RESURF region; and a P-type collector region formed in the RESURF region so as to be apart from the base region. Lattice defect is generated in the semiconductor substrate such that a resistance value of the semiconductor substrate is twice or more the resistance value of the semiconductor substrate that depends on the concentration of an impurity implanted in the semiconductor substrate.Type: GrantFiled: October 22, 2008Date of Patent: July 20, 2010Assignee: Panasonic CorporationInventors: Kazuyuki Sawada, Yuji Harada, Masahiko Niwayama, Saichirou Kaneko, Yoshimi Shimizu
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Patent number: 7759205Abstract: Methods for producing a semiconductor device are provided. In one embodiment, a method includes the steps of: (i) fabricating a partially-completed semiconductor device including a substrate, a source/drain region in the substrate, a gate stack overlaying the substrate, and a sidewall spacer adjacent the gate stack; (ii) utilizing an anisotropic etch to remove an upper portion of the sidewall spacer while leaving intact a lower portion of the sidewall spacer overlaying the substrate; (iii) implanting ions in the source/drain region; and (iv) annealing the semiconductor device to activate the implanted ions. The step of annealing is performed with the lower portion of the sidewall spacer intact to deter the ingress of oxygen into the substrate and minimize under-oxide regrowth proximate the gate stack.Type: GrantFiled: January 16, 2009Date of Patent: July 20, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Kingsuk Maitra, John Iacoponi
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Manufacturing Method of Nitride Substrate, Nitride Substrate, and Nitride-Based Semiconductor Device
Publication number: 20100155902Abstract: A manufacturing method of a nitride substrate includes the steps of: preparing a ground substrate; forming a mask on the ground substrate; placing the ground substrate in a reactor, and heating the ground substrate to a temperature of 850° C. to 1100° C. In the step of heating the ground substrate, HCl and NH3 are supplied into the reactor so that partial pressure PHCl satisfies (1.5+0.0005p) kPa?PHCl?(4+0.0005p) kPa and partial pressure PNH3 satisfies (15?0.0009p) kPa?PNH3?(26?0.0017p) kPa, whereby an AlxGayIn1-x-yN crystal (0?x<1, 0<y?1) is grown, and whereby a ridge-volley structure including a plurality of ridges and valleys parallel to one another is formed. The AlxGayIn1-x-yN crystal is grown so that the ridge-valley structure is not buried while a height of the volleys from the ground substrate is allowed to exceed 2.5 (p?s).Type: ApplicationFiled: February 24, 2010Publication date: June 24, 2010Inventors: Takuji Okahisa, Hideaki Nakahata, Koji Uematsu -
Publication number: 20100155903Abstract: An annealed wafer having enhanced gettering effects for Cu is produced by heating a silicon substrate containing a nitrogen concentration of 5×1014 to 1×1016/cm3, a carbon concentration of 1×1015 to 5×1016/cm3, and an oxygen concentration of 6×1017 to 11×1017/cm3 at a temperature of 650 to 800° C. for a time ?4 hours, and subjecting the heated substrate to argon annealing at a temperature of 1100 to 1250° C., wherein internal stacking fault density after annealing is ?5×108/cm3.Type: ApplicationFiled: December 9, 2009Publication date: June 24, 2010Applicant: Siltronic AGInventors: Kazunori Ishisaka, Katsuhiko Nakai, Masayuki Fukuda
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Publication number: 20100148310Abstract: A method of processing a semiconductor wafer includes preheating the wafer to a preheating temperature that is less than a peak temperature, heating the wafer from the preheating temperature to the peak temperature at a first ramp rate that averages about 100° C. per second or more, and, immediately after heating the wafer from the preheating temperature to the peak temperature, cooling the wafer at a second ramp rate that averages about ?70° C. per second or more from the peak temperature to the preheating temperature, wherein the peak temperature is about 1,100° C. or more.Type: ApplicationFiled: October 1, 2009Publication date: June 17, 2010Inventors: Tae-Hyoung Koo, Sam-jong Choi, Yeonsook Kim, Taesung Kim, Heesung Kim, KyooChul Cho, Joonyoung Choi
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Publication number: 20090321883Abstract: This method for manufacturing a silicon substrate for a solid-state imaging device, includes: a carbon compound layer forming step of forming a carbon compound layer on the surface of a silicon substrate; an epitaxial step of forming a silicon epitaxial layer on the carbon compound layer; and a heat treatment step of subjecting the silicon substrate having the epitaxial layer formed thereon to a heat treatment at a temperature of 600 and 800° C. for 0.25 to 3 hours so as to form gettering sinks that are complexes of carbon and oxygen below the epitaxial layer. This silicon substrate for a solid-state imaging device is manufactured by the above-mentioned method and includes: n epitaxial layer positioned on the surface of a silicon substrate; and a gettering layer which is positioned below the epitaxial layer and includes BMDs having a size of 10 to 100 nm at a concentration of 1.0×106 to 1.0×109 atoms/cm3.Type: ApplicationFiled: June 25, 2009Publication date: December 31, 2009Applicant: SUMCO CORPORATIONInventor: Kazunari KURITA
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Publication number: 20090315152Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.Type: ApplicationFiled: June 24, 2008Publication date: December 24, 2009Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Shyue Seng TAN, Lee Wee TEO, Yung Fu CHONG, Elgin QUEK, Sanford CHU
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Patent number: 7615471Abstract: The invention relates to a method for producing a tensioned layer on a substrate involving the following steps: producing a defect area in a layer adjacent to the layer to be tensioned, and; relaxing at least one layer adjacent to the layer to be tensioned. Additional layers can be epitaxially deposited. Layer structures formed in this manner are advantageously suited for components of all types.Type: GrantFiled: April 8, 2004Date of Patent: November 10, 2009Assignee: Forschungszentrum Julich GmbHInventor: Siegfried Mantl
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Publication number: 20090108408Abstract: A method for minimizing the effects of defects produced in a implantated area of a crystal lattice during dopant implantation in the lattice. The method begins with the step of implanting a trap layer of trap atoms, the trap atoms having a size less than that of the lattice member atoms. After implantation, the lattice is annealed for a time sufficient for interstitial defect atoms to be emitted from the defect area. In that manner, energetically stable pairs are formed between trap atoms and emitted interstitial atoms.Type: ApplicationFiled: October 29, 2007Publication date: April 30, 2009Applicant: SYNOPSYS, INC.Inventors: Victor Moroz, Dipankar Pramanik
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Publication number: 20080224269Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation.Type: ApplicationFiled: March 11, 2008Publication date: September 18, 2008Inventors: Young-Soo Park, Young-Nam Kim, Young-Sam Lim, Gi-Jung Kim, Pil-Kyu Kang
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Publication number: 20080211004Abstract: A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.Type: ApplicationFiled: February 29, 2008Publication date: September 4, 2008Inventors: Yoshio OZAWA, Ichiro Mizushima, Takashi Suzuki, Hirokazu Ishida, Yoshitaka Tsunashima
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Publication number: 20080135988Abstract: Various embodiments of the present invention relate to systems, devices, and methods for treating a semiconductor substrate, such as a silicon wafer, in order to reduce current leakage therein. A semiconductor substrate is provided a plurality of heating treatments that create a denuded zone adjacent to a surface of the substrate and a core zone below the denuded zone. Oxygen impurities within the denuded zone are removed through an oxygen out-diffusion heat treatment. A plurality of macroscopic bulk micro defects is generated within the core zone through the combination of an agglomeration heat treatment and a macroscopic growth heat treatment. This plurality of macroscopic bulk micro defects inhibits migration of metallic contaminants that are located within the substrate. For exemplary purposes, certain embodiments are described relating to a semiconductor wafer heated in a sequence of three treatments.Type: ApplicationFiled: December 7, 2006Publication date: June 12, 2008Inventors: Amit Subhash Kelkar, Joshua Li, Danh John C. Nguyen, Vijay Ullal
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Publication number: 20080023795Abstract: With conventional device, the quantity of complex defects differs with each semiconductor device because the concentration of impurities intrinsically contained differs for each silicon wafer. Consequently, there is an undesirable variation in characteristics among the semiconductor devices. The invention provides a method for manufacturing PIN type diode which comprises an intermediate semiconductor region in which complex defects are formed. The method comprises introducing impurities (for example, carbon), which are the same kind of impurities intrinsically contained in the intermediate semiconductor region, into the intermediate semiconductor region, and irradiating the intermediate semiconductor region with helium ions to form point defects.Type: ApplicationFiled: September 27, 2007Publication date: January 31, 2008Inventors: Shinya YAMAZAKI, Tomoyoshi KUSHIDA, Takahide SUGIYAMA
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Patent number: 7323391Abstract: A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portion of the doped silicon region on the substrate. The silicon germanium layer and stressed silicon nitride layer induce a stress in the doped silicon region of the substrate. In one version, the semiconductor device has a transistor with source and drain regions having the silicon germanium material, and the doped silicon region forms a channel that is configured to conduct charge between the source and drain regions. The stressed silicon nitride layer is formed over at least a portion of the channel, and can be a tensile or compressively stressed layer according the desired device characteristics.Type: GrantFiled: January 15, 2005Date of Patent: January 29, 2008Assignee: Applied Materials, Inc.Inventor: Reza Arghavani
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Publication number: 20070075401Abstract: One aspect of this disclosure relates to a memory device, comprising at least one gettering region, a memory array, a plurality of word lines and bit lines, and control circuitry. The gettering region is formed in a semiconductor substrate. The gettering region includes a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate. The memory array is formed in the crystalline semiconductor region, and includes a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells. Each word line is connected to a row of memory cells, and each bit line is connected to a column of memory cells. The control circuitry includes word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations.Type: ApplicationFiled: November 30, 2006Publication date: April 5, 2007Inventors: Leonard Forbes, Joseph Geusic
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Patent number: 7199404Abstract: A semiconductor substrate used for fabricating vertical devices, such as vertical MOSFET, capable of maintaining low ON-stage resistance and of ensuring a necessary level of OFF-stage breakdown voltage is provided. A heavily-doped arsenic layer of 0.5 to 3.0 ?m thick is inserted between a heavily-doped phosphorus layer 11 composing the drain of a vertical MOSFET and an n?-type drift layer. The heavily-doped arsenic layer functions as a barrier layer which prevents phosphorus from diffusing from the heavily-doped phosphorus layer into the n?-type drift layer. This is successful in maintaining spreading of the depletion layer during OFF time of the vertical MOSFET to thereby improve the OFF-stage breakdown voltage, and in maintaining the low ON-stage resistance.Type: GrantFiled: November 30, 2004Date of Patent: April 3, 2007Assignee: NEC Electronics CorporationInventor: Kinya Ohtani
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Publication number: 20060267152Abstract: A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A thermal oxidation completes the vertical isolation by use of a minifield oxidation process. The recess is filled to form a shallow trench isolation structure. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.Type: ApplicationFiled: July 27, 2006Publication date: November 30, 2006Inventor: Leonard Forbes