Electrical Characteristics Due To Properties Of Entire Semiconductor Body Rather Than Just Surface Region (epo) Patents (Class 257/E29.002)

  • Patent number: 9041165
    Abstract: A method for the formation of an at least partially relaxed strained material layer, comprises providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: May 26, 2015
    Assignee: SOITEC
    Inventors: Fabrice Letertre, Bruce Faure, Pascal Guenard
  • Patent number: 9024283
    Abstract: Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: May 5, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Timothy A. Quick, Eugene P. Marsh
  • Patent number: 9018684
    Abstract: Methods for fabricating silicon nanowire chemical sensing devices, devices thus obtained, and methods for utilizing devices for sensing and measuring chemical concentration of selected species in a fluid are described. Devices may comprise a metal-oxide-semiconductor field-effect transistor (MOSFET) structure.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: April 28, 2015
    Assignee: California Institute of Technology
    Inventors: Andrew P. Homyk, Michael D. Henry, Axel Scherer, Sameer Walavalkar
  • Patent number: 9018037
    Abstract: Forming a resistive switching layer having a vertical interface can generate defects confined along the interface between two electrodes. The confined defects can form a pre-determined region for filament formation and dissolution, leading to low power resistive switching and low program voltage or current variability. In addition, the filament forming process of the resistive memory device can be omitted due to the existence of the confined defects.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 28, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Federico Nardi, Randall J. Higuchi, Robert A. Huertas, Yun Wang
  • Patent number: 9018612
    Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Young Ho Lee, Keum Bum Lee, Min Young Lee, Hyung Suk Lee, Seung Beom Baek
  • Patent number: 9018613
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; and a memory cell block formed on the semiconductor substrate and configured having a plurality of memory cell arrays, each of the memory cell arrays including a plurality of column lines, a plurality of row lines, and a plurality of memory cells disposed at each of intersections of the plurality of column lines and the plurality of row lines, each of the memory cells including a variable resistance element having a transition metal oxide as a material, at least one of the plurality of column lines and the plurality of row lines being a polysilicon wiring line having polysilicon as a material, and the memory cell block including a block film between the variable resistance element of the memory cell and the polysilicon wiring line.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Nojiri, Hiroyuki Fukumizu, Shigeki Kobayashi, Masaki Yamato
  • Patent number: 9012877
    Abstract: A semiconductor device includes a first semiconductor layer extending in a first direction on a substrate, a plurality of second semiconductor layers spaced apart in the first direction on the first semiconductor layer, and an insulation layer structure surrounding side walls of the first semiconductor layer and the plurality of second semiconductor layers. The first semiconductor layer may have a first conductivity type, and the plurality of second semiconductor layers may have a second conductivity type.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-kyu Lee, Seung-pil Ko, Yong-jun Kim, Eun-jung Kim
  • Patent number: 9012876
    Abstract: Germanium antimony telluride materials are described, e.g., material of the formula GexSbyTezCmNn, wherein x is about 0.1-0.6, y is about 0-0.7, z is about 0.2-0.9, m is about 0.02-0.20, and n is about 0.2-0.20. One specific composition includes from 0 to 50% Sb, from 50 to 80% Te, from 20 to 50% Ge, from 3 to 20% N and from 2 to 15% carbon, wherein all atomic percentages of all components of the film total to 100 atomic %. Another specific composition includes from 10 to 50% Sb, from 50 to 80% Te, from 10 to 50% Ge, from 3 to 20% N and from 3 to 20% carbon, and wherein all atomic percentages of all components of the film total to 100 atomic %. Material of such composition is useful to form phase change films, e.g., as conformally coated on a phase change memory device substrate to fabricate a phase change random access memory cell.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: April 21, 2015
    Assignee: Entegris, Inc.
    Inventor: Jun-Fei Zheng
  • Patent number: 9012879
    Abstract: A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and life and methods for forming the same. The nonvolatile memory device has a first layer on a substrate, a resistive switching layer on the first layer, and a second layer. The resistive switching layer is disposed between the first layer and the second layer and the resistive switching layer comprises a material having the same morphology as the top surface of the first layer. A method of forming a nonvolatile memory element in a ReRAM device includes forming a resistive switching layer on a first layer and forming a second layer, so that the resistive switching layer is disposed between the first layer and the second layer. The resistive switching layer comprises a material formed with the same morphology as the top surface of the first layer.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: April 21, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Federico Nardi, Yun Wang
  • Patent number: 9012260
    Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Charlene Chen, Dipankar Pramanik
  • Patent number: 9006023
    Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: April 14, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Yun Wang, Imran Hashim
  • Patent number: 9006859
    Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Gurtej S. Sandhu
  • Patent number: 8995172
    Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: March 31, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Imran Hashim
  • Patent number: 8987694
    Abstract: Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Jong Han, Kong-Soo Lee, Yoon-Goo Kang, Ho-Kyun An, Seong-Hoon Jeong
  • Patent number: 8987698
    Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Agostino Pirovano
  • Patent number: 8987697
    Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 ? and about 100 ?, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 24, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Hieu Pham, Vidyut Gopal, Imran Hashim, Tim Minvielle, Yun Wang, Takeshi Yamaguchi, Hong Sheng Yang
  • Patent number: 8981329
    Abstract: Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: March 17, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Mihir Tendulkar, David Chi
  • Patent number: 8981326
    Abstract: A phase change memory cell, an array of the phase change memory cells, and a method for fabricating the phase change memory cells. The phase change memory cell includes a bottom electrode, a heating element, and a heat shield. During programming of the phase change memory cell, the bottom electrode passes current to the phase change memory cell. The heating element is electrically coupled to the bottom electrode and generates heat during the programming of the phase change memory cell. The heat shield is thermally conductive and surrounds at least a portion of the heating element. The heat shield conducts heat generated during programming of the phase change memory cell to the bottom electrode.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Chung H. Lam, Alejandro G. Schrott
  • Patent number: 8975610
    Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on multilayer dielectric stacks. The control element can include a titanium oxide-silicon-titanium oxide multilayer stack. Electrode materials may include one of ruthenium, titanium nitride, or carbon. The control element can include a silicon nitride-silicon-silicon nitride multilayer stack. Electrode materials may include titanium nitride.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Monica Sawkar Mathur, Prashant B. Phatak
  • Patent number: 8970014
    Abstract: Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-jin Lim, Hyung-Suk Jung, Yun-Ki Choi
  • Patent number: 8969129
    Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and a resistive switching layer connected in series with this resistor. The resistor is configured to prevent over-programming of the cell by limiting electrical currents through the resistive switching layer. Unlike the resistive switching layer, which changes its resistance in order to store data, the embedded resistor maintains a substantially constant resistance during operation of the cell. The embedded resistor is formed from tantalum nitride and silicon nitride. The atomic ratio of tantalum and silicon may be specifically selected to yield resistors with desired densities and resistivities as well as ability to remain amorphous when subjected to various annealing conditions. The embedded resistor may also function as a diffusion barrier layer and prevent migration of components between one of the electrodes and the resistive switching layer.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: March 3, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Chien-Lan Hsueh, Randall J. Higuchi, Mihir Tendulkar
  • Patent number: 8951915
    Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Hess, Katharina Umminger, Gabriel Maier, Markus Menath, Gunther Mackh, Hannes Eder, Alexander Heinrich
  • Patent number: 8928114
    Abstract: A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Patent number: 8921154
    Abstract: Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: December 30, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Mihir Tendulkar, David Chi
  • Patent number: 8921946
    Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu
  • Patent number: 8907313
    Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 9, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Charlene Chen, Dipankar Pramanik
  • Patent number: 8906736
    Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 ?cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: December 9, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Hieu Pham, Vidyut Gopal, Imran Hashim, Tim Minvielle, Dipankar Pramanik, Yun Wang, Takeshi Yamaguchi, Hong Sheng Yang
  • Patent number: 8907314
    Abstract: Molybdenum oxide can be used to form switching elements in a resistive memory device. The atomic ratio of oxygen to molybdenum can be between 2 and 3. The molybdenum oxide exists in various Magneli phases, such as Mo13O33, Mo4O11, Mo17O47, Mo8O23, or Mo9O26. An electric field can be established across the switching layers, for example, by applying a set or reset voltage. The electric field can cause movement of the oxygen charges, e.g., O2? ions, changing the composition profile of the switching layers, forming bistable states, including a high resistance state with MoO3 and a low resistance state with MoOx (x<3).
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 9, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Tony P. Chiang, Dipankar Pramanik
  • Patent number: 8900917
    Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. A metal oxide layer having higher carrier concentration than the semiconductor layer is provided intentionally as the buffer layer between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: December 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 8901528
    Abstract: A PCRAM device and a method of manufacturing the same are provided. The PCRAM device includes a semiconductor substrate, and a PN diode formed on the semiconductor substrate and including a layer interposed therein to suppress thermal diffusion of ions.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jin Ku Lee, Min Yong Lee, Jong Chul Lee
  • Patent number: 8901531
    Abstract: A magnetic memory with a memory layer having magnetization, the direction of magnetization of which changes according to information recorded therein; a reference layer having a fixed magnetization against which magnetization of the memory layer can be compared; a nonmagnetization layer between the memory layer and the reference layer; and an electrode on one side of the memory layer facing away from the reference layer, wherein, the memory device memorizes the information by reversal of the magnetization of the memory layer by a spin torque generated when a current flows between the memory layer, the nonmagnetization layer and the reference layer, and a heat conductivity of a center portion of the electrode is lower than a heat conductivity of surroundings thereof. The memory and reference preferably have vertical magnetizations.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: December 2, 2014
    Assignee: Sony Corporation
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 8901569
    Abstract: Provided is a power semiconductor device comprising a bonding joint that, even under a temperature environment of 150° C. or greater enabling operation of a wide bandgap semiconductor, reduces cracking-destruction occurring owing to thermal cycle while conductively connecting an electrode, connection terminal, and semiconductor device substrate. It is a power semiconductor device capable of operating under a temperature of 150° C. or greater having an electrode laminated on a wide bandgap semiconductor substrate and a connection terminal joined to the electrode for connection to external wiring, which power semiconductor device is characterized in that difference among the three coefficients of linear expansion of the electrode, a core of the connection terminal, and the semiconductor device substrate is 5.2×10?6/K at maximum, and that it comprises a joint that directly joins the connection terminal and the electrode.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: December 2, 2014
    Assignee: Nippon Steel & Sumitomo Metal Corporation
    Inventor: Hosei Hirano
  • Patent number: 8890105
    Abstract: A nonvolatile memory according to an embodiment includes a first wiring line; a second wiring line arranged above the first wiring line and extending in a direction crossing the first wiring line; and a resistance change layer arranged in an intersection region of the first wiring line the second wiring line, the second wiring line including a first member extending in the direction in which the second wiring line extends, and an electrode layer containing a metal element arranged on a side surface of the first member along the direction in which the second wiring line extends, a lower surface of the electrode layer being in contact with an upper surface of the resistance change layer.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: November 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyohito Nishihara
  • Patent number: 8890106
    Abstract: A hybrid circuit comprises a nitride-based transistor portion and a memristor portion. The transistor includes a source and a drain and a gate for controlling conductance of a channel region between the source and the drain. The memristor includes a first electrode and a second electrode separated by an active switching region. The source or drain of the transistor forms one of the electrodes of the memristor.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: November 18, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Gilberto Medeiros Ribeiro, Byung-Joon Choi, Stanley Williams
  • Patent number: 8890289
    Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: November 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kenzo Manabe, Naoya Inoue, Kenichiro Hijioka, Yoshihiro Hayashi
  • Patent number: 8890288
    Abstract: According to one exemplary embodiment, a metal-oxide-metal (MOM) capacitor in a semiconductor die comprises a first plurality of capacitor plates and a second plurality of capacitor plates sharing a plane parallel to and below a plane of a first metallization layer of the semiconductor die. The MOM capacitor further comprises a local interlayer dielectric between the first plurality of capacitor plates and the second plurality of capacitor plates. The first and second plurality of capacitor plates are made from a local interconnect metal for connecting devices formed in a device layer of the semiconductor die situated below the first metallization layer.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: November 18, 2014
    Assignee: Broadcom Corporation
    Inventors: Xiangdong Chen, Henry Kuo-Shun Chen
  • Patent number: 8890103
    Abstract: A semiconductive substrate that is suitable for realising electronic and/or optoelectronic devices that include at least one substrate, in particular of single crystal silicon, and an overlying layer of single crystal silicon. Advantageously, the semiconductive substrate comprises at least one functional coupling layer suitable for reducing the defects linked to the differences in the materials used. The functional coupling layer can comprise a corrugated portion made in the layer of single crystal silicon and suitable for reducing the defects linked to the differences in lattice constant of such materials used. Alternatively, the functional coupling layer can comprise a porous layer arranged between the substrate of single crystal silicon and the layer of single crystal silicon, and suitable for reducing the stress caused by the differences between the thermal expansion coefficients of the materials used. A manufacturing process of such a semiconductive substrate is also described.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: November 18, 2014
    Assignee: Consiglio Nazionale Delle Ricerche
    Inventors: Giuseppe Alessio Maria D'Arrigo, Francesco La Via
  • Patent number: 8884260
    Abstract: A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: November 11, 2014
    Assignee: Higgs Opl. Capital LLC
    Inventors: Frederick T. Chen, Ming-Jinn Tsai
  • Patent number: 8878154
    Abstract: A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: November 4, 2014
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
  • Patent number: 8871564
    Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: October 28, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Yun Wang, Imran Hashim
  • Patent number: 8872250
    Abstract: The present invention relates to a semiconductor device including nanodots and a capacitor. A semiconductor device includes a channel layer, a tunnel insulating layer formed on the channel layer, a memory layer formed on the tunnel insulating layer and including first nanodots, a charge blocking layer formed on the memory layer, a gate electrode conductive layer formed on the charge blocking layer, and a buffer layer located, at least one of, inside the tunnel insulating layer, inside the charge blocking layer, at an interface between the tunnel insulating layer and the memory layer and at the interface between the charge blocking layer and the memory layer, wherein the buffer layer includes second nanodots.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Kyoung Rok Han
  • Patent number: 8872150
    Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Agostino Pirovano
  • Patent number: 8866118
    Abstract: A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and life and methods for forming the same. The nonvolatile memory device has a first layer on a substrate, a resistive switching layer on the first layer, and a second layer. The resistive switching layer is disposed between the first layer and the second layer and the resistive switching layer comprises a material having the same morphology as the top surface of the first layer. A method of forming a nonvolatile memory element in a ReRAM device includes forming a resistive switching layer on a first layer and forming a second layer, so that the resistive switching layer is disposed between the first layer and the second layer. The resistive switching layer comprises a material formed with the same morphology as the top surface of the first layer.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 21, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Federico Nardi, Yun Wang
  • Patent number: 8866271
    Abstract: A semiconductor device manufacturing method includes loading a substrate, on which a high-k film is formed, into a processing chamber, performing a reforming process by heating the high-k film through irradiation of a microwave on the substrate, and unloading the substrate from the processing chamber.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: October 21, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Katsuhiko Yamamoto, Yuji Takebayashi, Tatsuyuki Saito, Masahisa Okuno
  • Patent number: 8859329
    Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein
  • Patent number: 8859328
    Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 ?cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: October 14, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Hieu Pham, Vidyut Gopal, Imran Hashim, Tim Minvielle, Dipankar Pramanik, Yun Wang, Takeshi Yamaguchi, Hong Sheng Yang
  • Patent number: 8853819
    Abstract: The present invention relates to a semiconductor structure having an integrated passive network and a method for making the same. The semiconductor structure includes a substrate which can be an interposer. The substrate can include a plurality of conductive vias. In various embodiments, the substrate includes a dielectric layer disposed thereon, the dielectric layer having an opening forming a straight hole allowing electrical connection between the passive network and the conductive via. The passive network includes a series of patterned dielectric and conductive layers, forming passive electronic components. In an embodiment, the passive device includes a common resistor coupled to a pair of inductors, each of the inductors coupled to a capacitor. In another embodiment, the passive device includes a resistor and an inductor electrically connected to each other, a bottom surface of the inductor coplanar with a bottom surface of the resistor.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: October 7, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua Chen, Teck-Chong Lee, Hsu-Chiang Shih, Meng-Wei Hsieh
  • Patent number: 8853660
    Abstract: Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: JaeJong Han, Sungun Kwon, Jinhye Bae, Kongsoo Lee, Seong Hoon Jeong, Yoongoo Kang, Ho-Kyun An
  • Patent number: 8853782
    Abstract: A semiconductor device has a so-called SOI structure in which an element is constituted by a semiconductor layer on an insulating surface, and the semiconductor layer is extremely thin as 5 nm to 30 nm. The semiconductor device is provided with a field effect transistor that includes in addition to such a semiconductor layer, a gate insulating layer with a thickness of 2 nm to 20 nm and a gate electrode, and a channel length is ten times or more and less than 40 times the thickness of the semiconductor layer. When the semiconductor layer is formed to be thin, the semiconductor device operates so as not to be easily influenced by a concentration of impurity imparting one conductivity type added to a channel formation region.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: October 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Patent number: 8847187
    Abstract: Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: September 30, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Mihir Tendulkar, David Chi