Abstract: A semiconductor light-emitting element includes: an n-type semiconductor layer; an active layer; a p-side contact electrode made of Rh; a p-side electrode covering layer made of Ti or TiN that covers the p-side contact electrode; a first protective layer made of SiO2 or SiON that covers an upper surface and a side surface of the p-side electrode covering layer in a portion different from that of a first p-side pad opening; a second protective layer made of Al2O3 that covers the first protective layer, a side surface of a p-side semiconductor layer, and a side surface of the active layer in a portion different from that of a second p-side pad opening; and a p-side pad electrode that is in contact with the p-side electrode covering layer in the first p-side pad opening and the second p-side pad opening.

Abstract: A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer.

Abstract: Passivation of group III-nitride heterojunction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract: A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior art Ti/Al-based contacts.

Abstract: An electrical contact is formed on a III-V semiconductor comprising gallium. The contact is formed by depositing a first layer comprising In, Au, and a dopant on the surface of a III-V semiconductor and a second layer comprising a conductive oxide on the first layer. The deposited layers are annealed in an inert atmosphere. The annealing causes the formation of a Ga—Au compound at the interface between the III-V semiconductor and the first layer. At least a portion of the dopant migrates into the III-V semiconductor such that the dopant provides n-type or p-type conductivity to the III-V semiconductor. The specific contact resistivity between the III-V semiconductor and the second layer is less than about 10?5 ?cm2. The layers are further annealed in an oxidizing atmosphere such that the indium in the first layer is oxidized to form indium oxide.

Abstract: Provided are a light emitting device, a method of manufacturing the same, a light emitting device package, and a lighting system. The light emitting device includes: a light emitting structure layer including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; an oxide protrusion disposed on at least a portion of the second conducive semiconductor layer; and a current spreading layer on the second conductive semiconductor layer and the oxide protrusion.

Abstract: In an n-type semiconductor layer that contains gallium (Ga), contact resistance is to be suppressed at a low level. An n-side electrode is provided on a surface of the n-type semiconductor layer containing Ga. The electrode includes a metal layer having a Ga content of equal to or more than 1 at % and equal to or less than 25 at %. The metal layer is disposed in contact with the n-type semiconductor layer.

Abstract: One embodiment of the present invention provides a method for fabricating a group III-V nitride structure with an ohmic-contact layer. The method involves fabricating a group III-V nitride structure with a p-type layer. The method further involves depositing an ohmic-contact layer on the p-type layer without first annealing the p-type layer. The method also involves subsequently annealing the p-type layer and the ohmic-contact layer in an annealing chamber at a predetermined temperature for a predetermined period of time, thereby reducing the resistivity of the p-type layer and the ohmic contact in a single annealing process.

Abstract: A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device includes a group III nitride semiconductor supporting base, a GaN based semiconductor region, an active layer, and a GaN semiconductor region. The primary surface of the group III nitride semiconductor supporting base is not any polar plane, and forms a finite angle with a reference plane that is orthogonal to a reference axis extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region, grown on the semipolar primary surface, includes a semiconductor layer of, for example, an n-type GaN based semiconductor doped with silicon. A GaN based semiconductor layer of an oxygen concentration of 5×1016 cm?3 or more provides an active layer, grown on the primary surface, with an excellent crystal quality.

Abstract: A method for fabricating an electrode by (i) depositing a palladium film on a p-type semiconductor layer; (ii) introducing an oxygen gas onto the palladium film to provide an oxygen ambient; (iii) oxidizing the palladium film adjacent to the semiconductor layer by annealing the palladium film in the oxygen ambient; and (iv) forming a palladium oxide film directly in contact with the semiconductor layer.

Abstract: A semiconductor device has a satisfactory ohmic contact on a p-type principal surface tilting from a c-plane. The principal surface 13a of a p-type semiconductor region 13 extends along a plane tilting from a c-axis (axis <0001>) of hexagonal group-III nitride. A metal layer 15 is deposited on the principal surface 13a of the p-type semiconductor region 13. The metal layer 15 and the p-type semiconductor region 13 are separated by an interface 17 such that the metal layer functions as a non-alloy electrode. Since the hexagonal group-III nitride contains gallium as a group-III element, the principal surface 13a comprising the hexagonal group-III nitride is more susceptible to oxidation compared to the c-plane of the hexagonal group-III nitride. The interface 17 avoids an increase in amount of oxide after the formation of the metal layer 15 for the electrode.

Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film is formed on the entire upper surface of the Ta film which forms part of the p electrode, and serves as an antioxidant film that prevents oxidation of the Ta film. Preventing oxidation of the Ta film, the second Pd film can reduce the resistance that may exist between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the p electrode with low resistance.

Abstract: To provide a semiconductor device that has a sufficiently low on-resistance and excellent low-capacitance and high-speed characteristics as compared with conventional GaN-based diodes. The semiconductor device includes: a substrate (101); a buffer layer (102); a stack structure (103 and 104) including at least one heterojunction unit (103 and 104) that is a stack of a layer (GaN layer 103) made of a nitride semiconductor and a layer (AlGaN layer 104) made of another nitride semiconductor having a larger band gap than the nitride semiconductor (GaN layer 103); a Schottky electrode (106) that is placed at a first end of the stack structure (103 and 104) and forms a Schottky barrier contact with the heterojunction unit (103 and 104); and an ohmic electrode (107) that is placed at a second end of the stack structure (103 and 104) and forms an ohmic contact with the heterojunction unit (103 and 104).

Abstract: A low contact resistance ohmic contact for a III-Nitride or compound semiconductor wafer or die consists of 4 layers of Ti, AlSi, Ti and TiW. The AlSi has about 1% Si. The layers are sequentially deposited as by sputtering, are patterned and plasma etched and then annealed in a rapid thermal anneal process. The use of AlSi in place of pure Al reduces contact resistance by about 15% to 30%.

Abstract: A two-dimensional carrier is generated in the vicinity of an interface that is a hetero interface between a semiconductor layer and a semiconductor layer. Two concave portions are formed so as to extend from a primary surface as far as the interface. An electrode that is made of metal and provides a Schottky junction with the semiconductor layers is formed on a bottom surface and a side surface of the concave portion. An electrode that is made from metal and provides a low resistance contact with the semiconductor layers and is also in low resistance contact therewith is formed on the bottom surface and side surface of the concave portion. As a result, a semiconductor device is provided in which contact resistance between the electrodes and the semiconductor layers is reduced and high frequency characteristics are improved.

Abstract: A laterally configured electrooptical device including: a substrate having a surface; a first semiconductor layer of a first type semiconductor material; a second semiconductor layer formed of a second type semiconductor material different from the first type semiconductor material; a first electrode; and a second electrode. The lower surface of the first semiconductor layer is coupled to a section of the surface of the substrate. The lower surface of the second semiconductor layer is coupled to the upper surface of the first semiconductor layer to form a junction. The first electrode is directly electrically coupled to one side of the first semiconductor layer and the second electrode is directly electrically coupled to an opposite side of the second semiconductor layer. These electrodes are configured such that the lower surface of the first semiconductor layer and/or the upper surface of the second semiconductor layer are substantially unoccluded by them.

Abstract: In an n-type semiconductor layer that contains gallium (Ga), contact resistance is to be suppressed at a low level. An n-side electrode is provided on a surface of the n-type semiconductor layer containing Ga. The electrode includes a metal layer having a Ga content of equal to or more than 1 at % and equal to or less than 25 at %. The metal layer is disposed in contact with the n-type semiconductor layer.

Abstract: A semiconductor device includes a p-type nitride semiconductor layer (14); and a p-side electrode (18) including a palladium oxide film (30) connected to a surface of the nitride semiconductor layer (14).

Abstract: The present invention discloses a fully Cu-metallized III-V group compound semiconductor device, wherein the fully Cu-metallized of a III-V group compound semiconductor device is realized via using an N-type gallium arsenide ohmic contact metal layer formed of a palladium/germanium/copper composite metal layer, a P-type gallium arsenide ohmic contact metal layer formed of a platinum/titanium/platinum/copper composite metal layer, and interconnect metals formed of a titanium/platinum/copper composite metal layer. Thereby, the fabrication cost of III-V group compound semiconductor devices can be greatly reduced, and the performance of III-V group compound semiconductor devices can be greatly promoted. Besides, the heat-dissipation effect can also be increased, and the electric impedance can also be reduced.

Abstract: An improved ohmic contact for a nitride-based semiconductor device is provided. In particular, a semiconductor device and method of manufacturing the semiconductor device are provided in which a semiconductor structure has an ohmic contact that includes a contact layer and a metal layer thereon. The contact layer includes at least Aluminum (Al) and Indium (In), and can further include Gallium (Ga) and/or Nitrogen (N). The molar fraction of Al and/or In can be increased/decreased within the contact layer.

Abstract: A nitride semiconductor device is provided which reduces the contact resistance at the interface between a P-type electrode and a nitride semiconductor layer. A nitride semiconductor device includes a P-type nitride semiconductor layer and a P-type electrode formed on the P-type nitride semiconductor layer. The P-type electrode is formed by successive laminations of a metal layer of a metal having a work function of 5.1 eV or more, a Pd layer of palladium, and a Ta layer of tantalum on the P-type nitride semiconductor layer.

Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film is formed on the entire upper surface of the Ta film which forms part of the p electrode, and serves as an antioxidant film that prevents oxidation of the Ta film. Preventing oxidation of the Ta film, the second Pd film can reduce the resistance that may exist between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the p electrode with low resistance.

Abstract: A semiconductor device and a manufacturing method thereof are provided which enable reduction and enhanced stability of contact resistance between the back surface of a nitride substrate and an electrode formed thereover. A nitride semiconductor device includes an n-type GaN substrate (1) over which a semiconductor element is formed, and an n-electrode (10) as a metal electrode formed over the back surface of the GaN substrate (1). A connection layer (20) is formed between the GaN substrate (1) and the n-electrode (10), and the connection layer (20) is composed of a material that is other than nitride semiconductors and that contains silicon.

Abstract: The present invention is a compound semiconductor device characterized in that it is Cu-metalized to improved the reliability of the device and to greatly reduce the cost of production.

Abstract: Provided are a p-type electrode and a III-V group GaN-based compound semiconductor device using the same. The electrode includes a first layer disposed on a III-V group nitride compound semiconductor layer and formed of a Zn-based material containing a solute; and a second layer stacked on the first layer and formed of at least one selected from the group consisting of Au, Co, Pd, Pt, Ru, Rh, Ir, Ta, Cr, Mn, Mo, Tc, W, Re, Fe, Sc, Ti, Sn, Ge, Sb, Al, ITO, and ZnO. The Zn-based p-type electrode has excellent electrical, optical, and thermal properties.

Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.

Abstract: A GaN layer is formed on a sapphire substrate through an AlN buffer layer and doped with Mg to prepare a laminate (referred to as “GaN substrate”). A metal (Pt and Ni) electrode 50 nm thick is formed on the GaN substrate by (1) vapor deposition after the GaN substrate is heated to a temperature of 300° C. or by (2) vapor deposition while the GaN substrate is left at room temperature. (3) The electrode obtained in (2) is heated to 300° C. in a nitrogen atmosphere. The contact resistance of the electrode obtained in (1) is lower by two or three digits than that of the electrode obtained in (2) or (3). That is, the electric characteristic of the electrode obtained in (1) is improved greatly.

Abstract: An ohmic electrode is formed by stacking a lower Ti layer, a diffusion preventing layer, an upper Ti layer, and a metallic (Au) layer on a p-type GaAs layer. The diffusion preventing layer includes tantalum (Ta) or niobium (Nb). Thus, interdiffusion of Ga and As in the p-type GaAs layer and Au in the metallic layer can be prevented, and variation in resistivity of the ohmic electrode in a high-temperature, high-humidity environment can be suppressed.