Abstract: According to one embodiment, a semiconductor device having a semiconductor substrate, first to fourth semiconductor layers of nitride, first to third electrodes and a gate electrode is provided. The first semiconductor layer is provided directly on the semiconductor substrate or on the same via a buffer layer. The second semiconductor layer is provided so as to be spaced apart from the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer and has a band gap wider than that of the second semiconductor layer. The fourth semiconductor layer insulates the first and second semiconductor layers. The first electrode forms an ohmic junction with the first to the third semiconductor layers. The second electrode is provided on the third semiconductor layer. The gate electrode is provided between the first and the second electrodes. The third electrode forms a Schottky junction with the first semiconductor layer.

Abstract: The present disclosure relates to a Schottky contact for a semiconductor device. The semiconductor device has a body formed from one or more epitaxial layers, which reside over a substrate. The Schottky contact may include a Schottky layer, a first diffusion barrier layer, and a third layer. The Schottky layer is formed of a first metal and is provided over at least a portion of a first surface of the body. The first diffusion barrier layer is formed of a silicide of the first metal and is provided over the Schottky layer. The third layer is formed of a second metal and is provided over the first diffusion barrier layer. In one embodiment, the first metal is nickel, and as such, the silicide is nickel silicide. Various other layers may be provided between or above the Schottky layer, the first diffusion barrier layer, and the third layer.

Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).

Abstract: In a Schottky electrode formation region on a nitride semiconductor, the total length of junctions of Schottky electrodes and a surface of a nitride semiconductor layer is longer than the perimeter of the Schottky electrode formation region. The total length is preferably 10 times longer than the perimeter. For example, the Schottky electrodes are formed concentrically and circularly.

Abstract: A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer.

Abstract: A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.

Abstract: A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.

Abstract: An electronic component is described that includes a metallic layer on a substrate that is made of a semiconductor material and a diffusion barrier layer that is made of a material that has a small diffusion coefficient for the metal of the metallic layer which is formed between the metallic layer and the substrate.

Abstract: A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device includes a group III nitride semiconductor supporting base, a GaN based semiconductor region, an active layer, and a GaN semiconductor region. The primary surface of the group III nitride semiconductor supporting base is not any polar plane, and forms a finite angle with a reference plane that is orthogonal to a reference axis extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region, grown on the semipolar primary surface, includes a semiconductor layer of, for example, an n-type GaN based semiconductor doped with silicon. A GaN based semiconductor layer of an oxygen concentration of 5×1016 cm?3 or more provides an active layer, grown on the primary surface, with an excellent crystal quality.

Abstract: Embodiments of the present invention are directed toward a trench metal-oxide-semiconductor field effect transistor (TMOSFET) device. The TMOSFET device includes a source-side-gate TMOSFET coupled to a drain-side-gate TMOSFET 1203. A switching node metal layer couples the drain of the source-side-gate TMOSFET to the source of the drain-side-gate TMOSFET so that the TMOSFETs are packaged as a stacked or lateral device.

Abstract: A GaN semiconductor device which has a low on-resistance, has a very small leak current when a reverse bias voltage is applied and is very excellent in withstand voltage characteristic, said GaN semiconductor device having a structure being provided with a III-V nitride semiconductor layer containing at least one hetero junction structure of III-V nitride semiconductors having different band gap energies; a first anode electrode arranged on a surface of said III-V nitride semiconductor by Schottky junction; a second anode electrode which is arranged on the surface of said III-V nitride semiconductor layer by Schottky junction, is electrically connected with said first anode electrode and forms a higher Schottky barrier than a Schottky barrier formed by said first anode electrode; and an insulating protection film which is brought into contact with said second anode electrode and is arranged on the surface of said III-V nitride semiconductor layer.

Abstract: To provide a semiconductor device that has a sufficiently low on-resistance and excellent low-capacitance and high-speed characteristics as compared with conventional GaN-based diodes. The semiconductor device includes: a substrate (101); a buffer layer (102); a stack structure (103 and 104) including at least one heterojunction unit (103 and 104) that is a stack of a layer (GaN layer 103) made of a nitride semiconductor and a layer (AlGaN layer 104) made of another nitride semiconductor having a larger band gap than the nitride semiconductor (GaN layer 103); a Schottky electrode (106) that is placed at a first end of the stack structure (103 and 104) and forms a Schottky barrier contact with the heterojunction unit (103 and 104); and an ohmic electrode (107) that is placed at a second end of the stack structure (103 and 104) and forms an ohmic contact with the heterojunction unit (103 and 104).

Abstract: A normally-off cascode power switch circuit is disclosed fabricated in wide bandgap semiconductor material such as silicon carbide or gallium nitride and which is capable of conducting current in the forward and reverse direction under the influence of a positive gate bias. The switch includes cascoded junction field effect transistors (JFETs) that enable increased gain, and hence blocking voltage, while minimizing specific on-resistance.

Abstract: The invention provides a semiconductor device and a method for fabricating the same capable of preventing a field plate portion from being delaminated from an insulating film by stress inherent in a semiconductor layer even if the stress is released in forming a trench in part of the semiconductor layer where the semiconductor device is to be separated and capable of having a higher breakdown property of the semiconductor device. The semiconductor device has source, drain and gate electrodes, insulating films that insulate the electrodes on an electron supplying layer and a mesa-structure formed at part where the semiconductor device is to be separated. The gate electrode has a first electrode layer having a function of the electrode and a second electrode layer having a field plate portion whose part that contacts with the insulating film is made of a metallic material that adheres well to the insulating film.

Abstract: A two-dimensional carrier is generated in the vicinity of an interface that is a hetero interface between a semiconductor layer and a semiconductor layer. Two concave portions are formed so as to extend from a primary surface as far as the interface. An electrode that is made of metal and provides a Schottky junction with the semiconductor layers is formed on a bottom surface and a side surface of the concave portion. An electrode that is made from metal and provides a low resistance contact with the semiconductor layers and is also in low resistance contact therewith is formed on the bottom surface and side surface of the concave portion. As a result, a semiconductor device is provided in which contact resistance between the electrodes and the semiconductor layers is reduced and high frequency characteristics are improved.

Abstract: A laterally configured electrooptical device including: a substrate having a surface; a first semiconductor layer of a first type semiconductor material; a second semiconductor layer formed of a second type semiconductor material different from the first type semiconductor material; a first electrode; and a second electrode. The lower surface of the first semiconductor layer is coupled to a section of the surface of the substrate. The lower surface of the second semiconductor layer is coupled to the upper surface of the first semiconductor layer to form a junction. The first electrode is directly electrically coupled to one side of the first semiconductor layer and the second electrode is directly electrically coupled to an opposite side of the second semiconductor layer. These electrodes are configured such that the lower surface of the first semiconductor layer and/or the upper surface of the second semiconductor layer are substantially unoccluded by them.

Abstract: A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.

Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.

Abstract: A semiconductor device which is suitable for miniaturization, capable of improving variations in characteristics of a transistor and enhancing the current driving capability comprises a semiconductor substrate, an isolation protruding from the semiconductor substrate and having a width above the semiconductor substrate narrower than a width in the semiconductor substrate, a semiconductor layer formed on the semiconductor substrate portion between the isolations, and a MOSFET formed on the semiconductor layer.

Abstract: A trench power semiconductor device including a recessed termination structure.

Abstract: A silicon carbide Schottky barrier semiconductor device provided with a Ta electrode as a Schottky electrode, in which the Schottky barrier height is controlled to a desired value in a range where power loss is minimized without increasing the n factor. The method for manufacturing the silicon carbide Schottky barrier semiconductor device includes the steps of depositing Ta on a crystal face of an n-type silicon carbide epitaxial film, the crystal face having an inclined angle in the range of 0° to 10° from a (000-1) C face, and carrying out a thermal treatment at a temperature range of 300 to 1200° C. to form the Schottky electrode.

Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.

Abstract: There are provided a method of producing a group III-V compound semiconductor, a Schottky barrier diode, a light emitting diode, a laser diode and methods of fabricating the diodes, that can achieve a reduced n type carrier density. The method of producing a group III-V compound semiconductor is a method of producing the compound semiconductor by metal organic chemical vapor deposition employing a material containing a group III element. Initially the step of preparing a seed substrate is performed. Then the step of growing a group III-V compound semiconductor on the seed substrate is performed by employing as a group III element-containing material an organic metal containing at most 0.01 ppm of silicon, at most 10 ppm of oxygen and less than 0.04 ppm of germanium.

Abstract: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n? doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n? doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

Abstract: The present invention provides a Schottky electrode for a nitride semiconductor device having a high barrier height, a low leak current performance and a low resistance and being thermally stable, and a process for production thereof. The Schottky electrode for a nitride semiconductor has a layered structure that comprises a copper (Cu) layer being in contact with the nitride semiconductor and a first electrode material layer formed on the copper (Cu) layer as an upper layer. As the first electrode material, a metal material which has a thermal expansion coefficient smaller than the thermal expansion coefficient of copper (Cu) and starts to undergo a solid phase reaction with copper (Cu) at a temperature of 400° C. or higher is employed.

Abstract: A GaN semiconductor device which has a low on-resistance, has a very small leak current when a reverse bias voltage is applied and is very excellent in withstand voltage characteristic, said GaN semiconductor device having a structure being provided with a III-V nitride semiconductor layer containing at least one hetero junction structure of III-V nitride semiconductors having different band gap energies; a first anode electrode arranged on a surface of said III-V nitride semiconductor by Schottky junction; a second anode electrode which is arranged on the surface of said III-V nitride semiconductor layer by Schottky junction, is electrically connected with said first anode electrode and forms a higher Schottky barrier than a Schottky barrier formed by said first anode electrode; and an insulating protection film which is brought into contact with said second anode electrode and is arranged on the surface of said III-V nitride semiconductor layer.

Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.