P-i-n Device (epo) Patents (Class 257/E33.046)
  • Patent number: 10283346
    Abstract: A method for recycling a sapphire substrate is disclosed. The method includes the steps of: high-temperature baking, wherein an intact epitaxial wafer to be scrapped is placed and baked in a baking oven at a high temperature of from 600° C. to 1000° C., and wherein the epitaxial wafer contains the sapphire substrate; and high-temperature rinsing in a concentrated acid, wherein the baked epitaxial wafer is then rinsed in the concentrated acid having a concentration ranging from 60% to 99% at a high temperature of from 160° C. to 300° C. The method can be used for recycling both patterned and smooth sapphire substrates.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: May 7, 2019
    Assignee: ENRAYTEK OPTOELECTRONICS CO., LTD.
    Inventors: Houyong Ma, Jing Ju, Zhengzhang You, Qiming Li, Jingchao Xie
  • Patent number: 8946877
    Abstract: A semiconductor package comprises: a substrate comprising a semiconductor device; a cap comprising a seal ring disposed over a surface of the cap; and a gap between the substrate and the surface of the cap. The seal ring comprises a tread comprising at least two columns.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: February 3, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Rick Snyder, Joel Philliber
  • Patent number: 8872294
    Abstract: Photonic structures and methods of formation are disclosed in which a photo detector interface having crystalline misfit dislocations is displaced with respect to a waveguide core to reduce effects of dark current on a detected optical signal.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Roy Meade, Zvi Sternberg, Ofer Tehar-Zahav
  • Patent number: 8841741
    Abstract: A high breakdown voltage diode of the present embodiment includes a first conductive semiconductor substrate, a drift layer formed on the first conductive semiconductor substrate and formed of a first conductive semiconductor, a buffer layer formed on the drift layer and formed of a second conductive semiconductor, a second conductive high concentration semiconductor region formed at an upper portion of the buffer layer, a mesa termination unit formed on an end region of a semiconductor apparatus to relax an electric field of the end region when reverse bias is applied between the semiconductor substrate and the buffer layer, and an electric field relaxation region formed at the mesa termination unit and formed of a second conductive semiconductor. A breakdown voltage of a high breakdown voltage diode, in which a pn junction is provided to a semiconductor layer, is increased, and a process yield is improved.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamu Kamaga, Makoto Mizukami, Takashi Shinohe
  • Patent number: 8829638
    Abstract: Electrical pumping of photonic crystal (PC) nanocavities using a lateral p-i-n junction is described. Ion implantation doping can be used to form the junction, which under forward bias pumps a gallium arsenide photonic crystal nanocavity with indium arsenide quantum dots. Efficient cavity-coupled electroluminescence is demonstrated in a first experimental device. Electrically pumped lasing is demonstrated in a second experimental device. High speed modulation of a single mode LED is demonstrated in a third experimental device. This approach provides several significant advantages. Ease of fabrication is improved because difficult timed etch steps are not required. Any kind of PC design can be employed. Current flow can be lithographically controlled to focus current flow to the active region of the device, thereby improving efficiency, reducing resistance, improving speed, and reducing threshold.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: September 9, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Gary Shambat, Bryan Ellis, Jelena Vuckovic
  • Patent number: 8664741
    Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 8652871
    Abstract: A thin film photovoltaic device on a substrate is being realized by a method for manufacturing a p-i-n junction semiconductor layer stack with a p-type microcrystalline silicon layer, a p-type amorphous silicon layer, a buffer silicon layer comprising preferably intrinsic amorphous silicon, an intrinsic type amorphous silicon layer, and an n-type silicon layer over the intrinsic type amorphous silicon layer.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: February 18, 2014
    Assignee: Tel Solar AG
    Inventors: Stefano Benagli, Daniel Borrello, Evelyne Vallat-Sauvain, Johannes Meier, Ulrich Kroll
  • Patent number: 8637897
    Abstract: A semiconductor light emitting device includes a substrate and a plurality of light emitting cells arranged on the substrate. Each of the light emitting cells includes a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer disposed therebetween to emit blue light. An interconnection structure electrically connects the first-conductivity-type and the second-conductivity-type semiconductor layers of one light emitting cell to the first-conductivity-type and the second-conductivity-type semiconductor layers of another light emitting cell. A light conversion part is formed in a light emitting region defined by the light emitting cells and includes a red and/or a green light conversion part respectively having a red and/or a green light conversion material.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je Won Kim, Tae Sung Jang, Jong Gun Woo, Jong Ho Lee
  • Patent number: 8618603
    Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Fumiki Aiso
  • Patent number: 8598619
    Abstract: A semiconductor light emitting device includes a substrate and a plurality of light emitting cells arranged on the substrate. Each of the light emitting cells includes a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer disposed therebetween to emit blue light. An interconnection structure electrically connects the first-conductivity-type and the second-conductivity-type semiconductor layers of one light emitting cell to the first-conductivity-type and the second-conductivity-type semiconductor layers of another light emitting cell. A light conversion part is formed in a light emitting region defined by the light emitting cells and includes a red and/or a green light conversion part respectively having a red and/or a green light conversion material.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: December 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je Won Kim, Tae Sung Jang, Jong Gun Woo, Jong Ho Lee
  • Patent number: 8481352
    Abstract: The present invention provides a method of fabricating a light emitting diode chip having an active layer between an N type semiconductor layer and a P type semiconductor layer. The method comprises the steps of preparing a substrate; laminating the semiconductor layers on the substrate, the semiconductor layers having the active layer between the N type semiconductor layer and the P type semiconductor layer; and forming grooves on the semiconductor layers laminated on the substrate until the substrate is exposed, whereby inclined sidewalls are formed by the grooves in the semiconductor layers divided into a plurality of chips. According to embodiments of the present invention, a sidewall of a semiconductor layer formed on a substrate of a light emitting diode chip is inclined with respect to the substrate, whereby its directional angle is widened as compared with a light emitting diode chip without such inclination.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: July 9, 2013
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Jun Hee Lee, Jong Kyu Kim, Yeo Jin Yoon
  • Patent number: 8470657
    Abstract: An ion implantation method for semiconductor sidewalls includes steps of: forming a trench on a substrate, and the trench having a lower reflecting layer and two sidewalls adjacent to a bottom section; performing a plasma doping procedure to sputter conductive ions to the lower reflecting layer and the conductive ions being rebounded from the lower reflecting layer to adhere to the sidewalls to respectively form an adhesion layer thereon; and performing an annealing procedure to diffuse the conductive ions of the adhesion layer into the substrate to form a conductive segment. Thus, without damaging the substrate, the conductive segment having a high conductive ion doping concentration is formed at a predetermined region to satisfy semiconductor design requirements.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: June 25, 2013
    Assignee: Rexchip Electronics Corporation
    Inventor: Chih-Hsin Lo
  • Patent number: 8471270
    Abstract: An indirect-bandgap-semiconductor, light-emitting diode. The indirect-bandgap-semiconductor, light-emitting diode includes a plurality of portions including a p-doped portion of an indirect-bandgap semiconductor, an intrinsic portion of the indirect-bandgap semiconductor, and a n-doped portion of the indirect-bandgap semiconductor. The intrinsic portion is disposed between the p-doped portion and the n-doped portion and forms a p-i junction with the p-doped portion, and an i-n junction with the n-doped portion. The p-i junction and the i-n junction are configured to facilitate formation of at least one hot electron-hole plasma in the intrinsic portion when the indirect-bandgap-semiconductor, light-emitting diode is reverse biased and to facilitate luminescence produced by recombination of a hot electron with a hole.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: June 25, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Alexandre M. Bratkovski, Viatcheslav Osipov
  • Patent number: 8471352
    Abstract: Electrical pumping of photonic crystal (PC) nanocavities using a lateral p-i-n junction is described. Ion implantation doping can be used to form the junction, which under forward bias pumps a gallium arsenide photonic crystal nanocavity with indium arsenide quantum dots. Efficient cavity-coupled electroluminescence is demonstrated in a first experimental device. Electrically pumped lasing is demonstrated in a second experimental device. This approach provides several significant advantages. Ease of fabrication is improved because difficult timed etch steps are not required. Any kind of PC design can be employed. Current flow can be lithographically controlled to focus current flow to the active region of the device, thereby improving efficiency, reducing resistance, improving speed, and reducing threshold. Insulating substrates can be employed, which facilitates inclusion of these devices in photonic integrated circuits.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: June 25, 2013
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Bryan Ellis, Jelena Vuckovic, Ilya Fushman
  • Patent number: 8198620
    Abstract: A resistance switching memory is introduced herein. The resistance switching memory includes a highly-insulating or resistance-switching material formed to cover the sidewall of a patterned metal line, and extended alongside a dielectric layer sidewall to further contact a portion of the top surface of the lower electrode. The other part of the top surface of the lower electrode is covered by an insulating layer between the top electrode and the lower electrode. An oxygen gettering metal layer in the lower electrode occupies a substantial central part of the top surface of the lower electrode and is partially covered by the highly-insulating or resistance-switching material. A switching area is naturally very well confined to the substantial central part of the oxygen gettering metal layer of the lower electrode.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: June 12, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Frederick T. Chen, Ming-Jinn Tsai, Wei-Su Chen, Heng-Yuan Lee
  • Patent number: 8129730
    Abstract: An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare die electronic element is provided having a top conductive side and a bottom conductive side. Each bare die electronic element is disposed so that the top conductive side is in electrical communication with the top electrically conductive surface and so that the bottom conductive side is in electrical communication with the bottom electrically conductive surface.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: March 6, 2012
    Assignee: Lumachip, Inc.
    Inventor: John J. Daniels
  • Patent number: 8089067
    Abstract: A self emission silicon emission display is provided at a low price, which contains silicon and oxygen which exist in abundance on the earth as the main component and which can be easily formed by conventional silicon process. A light emission element includes a first electrode for injecting electrons, a second electrode for injecting holes, and a light emission part electrically connected to the first electrode and the second electrode, where the light emission part includes amorphous or polycrystalline silicon consisting of a single layer or plural layers and where the dimension of the silicon in at least one direction is controlled to be several nanometers.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: January 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Saito, Hiroyuki Uchiyama, Toshiyuki Mine
  • Patent number: 8076669
    Abstract: An organic light emitting display includes an organic light emitting diode formed on a substrate, coupled to a transistor; a photodiode formed on the substrate and including a semiconductor layer including a high-concentration P doping region, an intrinsic region with defects and a high-concentration N doping region; and a controller that uniformly controls the luminance of light emitted from the organic light emitting diode by controlling a voltage applied to the first electrode and the second electrode according to the voltage outputted from the photodiode.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: December 13, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Chul-kyu Kang, Byoung-keon Park
  • Publication number: 20110248242
    Abstract: Electrical pumping of photonic crystal (PC) nanocavities using a lateral p-i-n junction is described. Ion implantation doping can be used to form the junction, which under forward bias pumps a gallium arsenide photonic crystal nanocavity with indium arsenide quantum dots. Efficient cavity-coupled electroluminescence is demonstrated in a first experimental device. Electrically pumped lasing is demonstrated in a second experimental device. This approach provides several significant advantages. Ease of fabrication is improved because difficult timed etch steps are not required. Any kind of PC design can be employed. Current flow can be lithographically controlled to focus current flow to the active region of the device, thereby improving efficiency, reducing resistance, improving speed, and reducing threshold. Insulating substrates can be employed, which facilitates inclusion of these devices in photonic integrated circuits.
    Type: Application
    Filed: April 5, 2011
    Publication date: October 13, 2011
    Inventors: Bryan Ellis, Jelena Vuckovic, Ilya Fushman
  • Patent number: 7952107
    Abstract: An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare die electronic element is provided having a top conductive side and a bottom conductive side. Each bare die electronic element is disposed so that the top conductive side is in electrical communication with the top electrically conductive surface and so that the bottom conductive side is in electrical communication with the bottom electrically conductive surface.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: May 31, 2011
    Assignee: Lumachip, Inc.
    Inventors: John James Daniels, Gregory Victor Nelson
  • Patent number: 7936037
    Abstract: A photo-sensor having a structure which can suppress electrostatic discharge damage is provided. Conventionally, a transparent electrode has been formed over the entire surface of a light receiving region; however, in the present invention, the transparent electrode is not formed, and a p-type semiconductor layer and an n-type semiconductor layer of a photoelectric conversion layer are used as an electrode. Therefore, in the photo-sensor according to the present invention, resistance is increased an electrostatic discharge damage can be suppressed. In addition, positions of the p-type semiconductor layer and the n-type semiconductor layer, which serve as an electrode, are kept away; and thus, resistance is increased and withstand voltage can be improved.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: May 3, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuo Nishi, Yuusuke Sugawara, Hironobu Takahashi, Tatsuya Arao
  • Patent number: 7936038
    Abstract: Disclosed herein is a photodiode cell, including: a first-type substrate; a second-type epitaxial layer disposed on the first-type substrate; heavily-doped second-type layers, each having a small depth, formed on the second-type epitaxial layer; and heavily-doped first-type layers, each having a narrow and shallow section, disposed on the second-type epitaxial layer and formed between the heavily-doped second-type layers, wherein the first-type and second-type have opposite doped states.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: May 3, 2011
    Assignee: Samsung Electro-Mechanics Co.
    Inventors: Ha Woong Jeong, Kyoung Soo Kwon, Chae Dong Go, Deuk Hee Park
  • Patent number: 7893448
    Abstract: The present invention relates to a light emitting device having nano structures for light extraction and a method for manufacturing the same, nano structures comprising nano rods, nano agglomerations, nano recesses, nano patterns with nano line widths, nano through-holes or a combination thereof, formed on a light emitting surface of a light emitting device, thereby enhancing the light extraction efficiency of the device.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: February 22, 2011
    Assignees: LG Electronics Inc., LG Innotek Co., Ltd.
    Inventor: Jong wook Kim
  • Patent number: 7875871
    Abstract: In the present invention a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor; for example a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: January 25, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Tanmay Kumar, S. Brad Herner
  • Patent number: 7858994
    Abstract: An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare die electronic element is provided having a top conductive side and a bottom conductive side. Each bare die electronic element is disposed so that the top conductive side is in electrical communication with the top electrically conductive surface and so that the bottom conductive side is in electrical communication with the bottom electrically conductive surface.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: December 28, 2010
    Assignee: Articulated Technologies, LLC
    Inventor: John J. Daniels
  • Publication number: 20100181570
    Abstract: An active matrix substrate in which variations in output characteristics of photodiodes are reduced, and a display device using this active matrix substrate, are provided. An active matrix substrate (1) having an n-TFT (20), a p-TFT (30), and a photodiode (10) is used. The photodiode (10) includes a p-layer (7), an i-layer (8), and an n-layer (9). The i-layer (8) includes a p-type semiconductor region (8a) at a position adjacent to the player (7), said p-type semiconductor region (8a) having a diffusion concentration of p-type impurities that is set at the same level as that of a diffusion concentration of p-type impurities in the channel region (23) of the n-TFT (20); and an n-type semiconductor region (8b) at a position adjacent to the n-layer (9), said n-type semiconductor region (8b) having a diffusion concentration of n-type impurities that is set at the same level as that of a diffusion concentration of n-type impurities in the channel region (33) of the p-TFT (30).
    Type: Application
    Filed: July 11, 2008
    Publication date: July 22, 2010
    Inventors: Hiromi Katoh, Benjamin James Hadwen
  • Patent number: 7759757
    Abstract: An electro-optical device includes an insulating substrate, a switching element, at least one PIN diode, and at least one reflector. The switching element includes a first polysilicon semiconductor layer formed on the insulating substrate, and a gate electrode formed between the insulating substrate and the first semiconductor layer. Each of the at least one PIN diode includes a second polysilicon semiconductor layer formed on the insulating substrate. The at least one reflector is formed in the same layer as the gate electrode and opposite the second semiconductor layer or layers of the at least one PIN diode.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: July 20, 2010
    Assignee: Sony Corporation
    Inventors: Shin Koide, Hiroko Muramatsu, Shin Fujita
  • Patent number: 7732886
    Abstract: A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: June 8, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Tsan-Chi Chu, Wen-Shiang Liao, Wen-Ching Tsai
  • Patent number: 7683396
    Abstract: A high power light emitting device assembly with electro-static-discharge (ESD) protection ability and the method of manufacturing the same, the assembly comprising: at least two sub-mounts, respectively being electrically connected to an anode electrode and a cathode electrode, each being made of a metal of high electric conductivity and high thermal conductivity; a light emitting device, arranged on the sub-mounts; and an ESD protection die, sandwiched and glued between the sub-mounts, for enabling the high-power operating light emitting device to have good heat dissipating path while preventing the same to be damaged by transient power overload of static surge.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: March 23, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Chieh Chou, Wen-Shan Lin, Hung-Hsin Tsai
  • Patent number: 7645646
    Abstract: In the manufacture of an electronic device such as an active matrix display, a vertical amorphous PIN photodiode or similar thin-film diode (D) is advantageously integrated with a polysilicon TFT (TFT1, TFT2) in a manner that permits a good degree of optimization of the respective TFT and diode properties while being compatible with the complex pixel context of the display. High temperature processes for making the active semiconductor film (10) of the TFT more crystalline than an active semiconductor film (40) of the diode and for forming the source and drain doped regions (s1,s2, d1,d2) of the TFT are carried out before depositing the active semiconductor film (40) of the diode. Thereafter, the lateral extent of the diode is defined by etching while protecting with an etch-stop film (30) an interconnection film (20) that can provide a doped bottom electrode region (41) of the diode as well as one of the doped regions (s2, g1) of the TFT.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: January 12, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Nigel D. Young
  • Publication number: 20090321868
    Abstract: A waveguide photodetector detecting light incident on a light detecting end face includes: a substrate; and a layer stack structure on the substrate and including a semiconductor layer of a first conductivity type, an undoped semiconductor layer, and a semiconductor layer of a second conductivity type. The undoped semiconductor layer includes two or more undoped light absorbing layers and undoped non-light-absorbing layers. One non-light-absorbing layer is disposed between adjacent undoped light absorbing layers. The non-light-absorbing layers have a bandgap wavelength shorter than the wavelength of the incident light that is detected.
    Type: Application
    Filed: December 11, 2008
    Publication date: December 31, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Masaharu Nakaji
  • Patent number: 7595517
    Abstract: A charge coupled device comprises a semiconductor substrate of one conductive type, a first charge couple device having a series of electrodes linearly arranged on the semiconductor substrate, a second charge coupled device diverged into tow lines at an end of the first charge coupled device, detectors, each of which detects a signal transferred by one of two lines of the diverged second charge coupled device, and output devices, each of which outputs the signal detected by one of the detectors, wherein a plane shape of a last electrode of the first charge coupled device connecting to the diverged second charge coupled device is a shape wherein a length of a transfer channel of the last electrode becomes shorter as going far from a right angled direction of a transfer direction of the first charge coupled device starting from a boundary part of divergence of the diverged second charge coupled device.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: September 29, 2009
    Assignee: Fujifilm Corporation
    Inventor: Katsumi Ikeda
  • Patent number: 7498649
    Abstract: An electro-optical device includes an insulating substrate, a switching element, at least one PIN diode, and at least one reflector. The switching element includes a first polysilicon semiconductor layer formed on the insulating substrate, and a gate electrode formed between the insulating substrate and the first semiconductor layer. Each of the at least one PIN diode includes a second polysilicon semiconductor layer formed on the insulating substrate. The at least one reflector is formed in the same layer as the gate electrode and opposite the second semiconductor layer or layers of the at least one PIN diode.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: March 3, 2009
    Assignee: Epson Imaging Devices Corporation
    Inventors: Shin Koide, Hiroko Muramatsu, Shin Fujita
  • Patent number: 7492028
    Abstract: A photo-sensor having a structure which can suppress electrostatic discharge damage is provided. Conventionally, a transparent electrode has been formed over the entire surface of a light receiving region; however, in the present invention, the transparent electrode is not formed, and a p-type semiconductor layer and an n-type semiconductor layer of a photoelectric conversion layer are used as an electrode. Therefore, in the photo-sensor according to the present invention, resistance is increased an electrostatic discharge damage can be suppressed. In addition, positions of the p-type semiconductor layer and the n-type semiconductor layer, which serve as an electrode, are kept away; and thus, resistance is increased and withstand voltage can be improved.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: February 17, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuo Nishi, Yuusuke Sugawara, Hironobu Takahashi, Tatsuya Arao
  • Publication number: 20080315225
    Abstract: Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device comprises a p-type substrate, a p-type semiconductor layer, an active layer, and an n-type semiconductor layer. The p-type semiconductor layer is formed on the p-type substrate. The active layer is formed on the p-type semiconductor layer. The n-type semiconductor layer is formed on the active layer.
    Type: Application
    Filed: June 23, 2008
    Publication date: December 25, 2008
    Inventor: Kyung Jun KIM
  • Publication number: 20080246122
    Abstract: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity.
    Type: Application
    Filed: May 7, 2008
    Publication date: October 9, 2008
    Applicant: ICEMOS TECHNOLOGY CORPORATION
    Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
  • Patent number: 7244997
    Abstract: An electronic system includes a three terminal device having a light emitting portion and a magnetically sensitive portion. The magnetically sensitive portion is for modulating light emission from the light emitting portion. The device is a spin valve transistor having a light-emitting quantum well in its collector. The device can convert a magnetic digital signal to both an electrical digital signal and an optical digital signal, wherein either or both of these signals can be provided as a device output. The magnetically sensitive portion of the device is formed of a pair of magnetically permeable layers. When the layers are aligned electron current can pass through with sufficient energy to reach a quantum well where they recombine, generating light. The device may be used to read a magnetic storage medium, such as a disk drive. Or it can be used to provide a display or a memory array composed of single device magnetic write, optical read memory cells.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: July 17, 2007
    Assignee: President and Fellows of Harvard College
    Inventors: Ian Robert Appelbaum, Douwe Johannes Monsma, Kasey Joe Russell
  • Patent number: 7217956
    Abstract: Device structures for sheets of light active material. A first substrate has a transparent first conductive layer. A pattern of light active semiconductor elements are fixed to the first substrate. The light active semiconductor elements have an n-side and a p-side. Each light active semiconductor element has either of the n-side or the p-side in electrical communication with the transparent conductive layer. A second substrate has a second conductive layer. An adhesive secures the second substrate to the first substrate so that the other of said n-side or said p-side of each said light active semiconductor element is in electrical communication with the second conductive layer. Thus forming a solid-state light active device.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: May 15, 2007
    Assignee: Articulated Technologies, LLC.
    Inventors: John James Daniels, Gregory Victor Nelson
  • Patent number: 7180147
    Abstract: A method of forming a high germanium concentration, low defect density silicon germanium film and its associated structures is described, comprising forming a dielectric layer on a substrate, patterning the dielectric layer to form a silicon region and at least one dielectric region, and forming a low defect silicon germanium layer on at least one dielectric region.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventor: Mike Morse