Comprising Only Group Iii-v Compound (epo) Patents (Class 257/E33.049)
  • Patent number: 11942519
    Abstract: A semiconductor structure includes a superlattice structure, an electrical isolation layer, a channel layer, and a composition gradient layer. The superlattice structure is disposed on a substrate, the electrical isolation layer is disposed on the superlattice structure, the channel layer is disposed on the electrical isolation layer, and the composition gradient layer is disposed between the electrical isolation layer and the superlattice structure. The composition gradient layer and the superlattice structure include a same group III element, and the atomic percentage of the same group III element in the composition gradient layer is gradually decreased in the direction from the superlattice structure to the electrical isolation layer. In addition, a high electron mobility transistor including the semiconductor structure is also provided.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 26, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen Chen, Franky Juanda Lumbantoruan
  • Patent number: 11688827
    Abstract: A nanorod semiconductor layer having a flat upper surface, a micro-LED including the nanorod semiconductor layer, a pixel plate including the micro-LED, a display device including the pixel plate, and an electronic device including the pixel plate are provided. The nanorod semiconductor layer includes: a main body; and an upper end formed from the main body, wherein the upper end includes: a first inclined surface; a second inclined surface facing the first inclined surface; and a flat upper surface between the first inclined surface and the second inclined surface, and a width of the upper end becomes narrower in an upward direction, and when a length of the upper end protruded from the main body (a thickness of the upper end) is L1, an inclination angle between a surface extending parallel to a surface selected from the first and second inclined surfaces and the flat upper surface is ?, and a width of the main body is D, a width D1 of the flat upper surface satisfies Equation 1.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: June 27, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nakhyun Kim, Junhee Choi, Jinjoo Park, Joohun Han
  • Patent number: 10431957
    Abstract: Disclosed is a laser source capable of producing mid-IR laser radiation comprises growing a first core structure on a substrate, etching away the first core structure in one or more locations, and growing a second core structure on the substrate. At least one of the core structures comprises a quantum cascade gain medium emitting at a frequency within the range from 3-14 ?m. Also disclosed is a laser source capable of producing mid-IR laser radiation comprising a quantum-cascade core positioned on a substrate for emitting within the range from 3-14 ?m and a second core on the substrate positioned in-plane relative to the first core. The second core is one of a) a passive waveguide core b) a second quantum-cascade core and c) a semiconductor active core region.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 1, 2019
    Assignee: THORLABS QUANTUM ELECTRONICS, INC.
    Inventors: Catherine Genevieve Caneau, Feng Xie, Chung-En Zah
  • Patent number: 9882348
    Abstract: Until now, the laser beam light is the main feature to be provided by semiconductor laser diodes. The highly ordered direct current of charge carriers injected into the active region of these electronic components above the lasing threshold can be used in innovative ways. This attribute is associated with a new theoretical concept when all particles which are part of macroscopic objects are widely coupled to each other via quantum entanglements—it can generate a distance force induction and a self-induction of force. Considering this, a force can be inducted in the external objects—thrusting them—and a force can be inducted in the own semiconductor laser diode structure for its self propulsion.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: January 30, 2018
    Inventor: Elio Battista Porcelli
  • Patent number: 9859381
    Abstract: A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jizhong Li, Anthony J. Lochtefeld
  • Patent number: 8872294
    Abstract: Photonic structures and methods of formation are disclosed in which a photo detector interface having crystalline misfit dislocations is displaced with respect to a waveguide core to reduce effects of dark current on a detected optical signal.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Roy Meade, Zvi Sternberg, Ofer Tehar-Zahav
  • Patent number: 8866173
    Abstract: A light emitting device according to the embodiment may include a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer; an electrode on the light emitting structure; a protection layer under a peripheral region of the light emitting structure; and an electrode layer under the light emitting structure, wherein the protection layer comprises a first layer, a second layer, and a third layer, wherein the first layer comprises a first metallic material, and wherein the second layer is disposed between the first layer and the third layer, the second layer has an insulating material or a conductive material.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: October 21, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hwan Hee Jeong
  • Patent number: 8859313
    Abstract: A method for manufacturing a semiconductor light emitting element (1) which includes a first step of forming a first n-type semiconductor layer (12c) on a substrate (11) and a second step of sequentially forming a regrowth layer (12d) of the first n-type semiconductor layer (12c), a second n-type semiconductor layer (12b), a light emitting layer (13), and a p-type semiconductor layer (14) on the first n-type semiconductor layer (12c). In the step of forming the second n-type semiconductor layer (12b), a step (1) of supplying Si less than that forming the regrowth layer (12d) as a dopant to form a first layer of the second n-type semiconductor layer and a step (2) of supplying the Si more than that in the step (1) to form a second layer of the second n-type semiconductor layer are performed in this order.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: October 14, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Hiromitsu Sakai
  • Patent number: 8728834
    Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: May 20, 2014
    Assignee: Phostek, Inc.
    Inventor: Yuan-Hsiao Chang
  • Patent number: 8729575
    Abstract: The semiconductor light emitting device according to an embodiment includes an N-type nitride semiconductor layer, a nitride semiconductor active layer disposed on the N-type nitride semiconductor layer, and a P-type nitride semiconductor layer disposed on the active layer. The P-type nitride semiconductor layer includes an aluminum gallium nitride layer. The indium concentration in the aluminum gallium nitride layer is between 1E18 atoms/cm3 and 1E20 atoms/cm3 inclusive. The carbon concentration is equal to or less than 6E17 atoms/cm3. Where the magnesium concentration is denoted by X and the acceptor concentration is denoted by Y, Y>{(?5.35e19)2?(X?2.70e19)2}1/2?4.63e19 holds.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jongil Hwang, Hung Hung, Yasushi Hattori, Rei Hashimoto, Shinji Saito, Masaki Tohyama, Shinya Nunoue
  • Patent number: 8674337
    Abstract: A light emitting diode (LED) and a method for fabricating the same, capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer disposed on a sapphire substrate; a GaN layer disposed on the buffer layer; a doped GaN layer disposed on the GaN layer; a GaN layer having indium disposed on the GaN layer; an active layer disposed on the GaN layer having indium; and a P-type GaN disposed on the active layer. Here, an empirical formula of the GaN layer having indium is given by In(x)Ga(1?x)N and a range of x is given by 0<x<2, and a thickness of the GaN layer having indium is 50-200 ?.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: March 18, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Seong Jae Kim
  • Patent number: 8647901
    Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: February 11, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yih-Der Guo, Chih-Ming Lai, Jenq-Dar Tsay, Po-Chun Liu
  • Patent number: 8643037
    Abstract: There is provided a nitride semiconductor light emitting device including: n-type and p-type nitride semiconductor layers; an active layer disposed between the n-type and p-type nitride semiconductor layers; and an electron injection layer disposed between the n-type nitride semiconductor layer and the active layer. The electron injection layer has a multilayer structure, in which three or more layers having different energy band gaps are stacked, and the multilayer structure is repetitively stacked at least twice. At least one layer among the three or more layers has a reduced energy band gap in individual multilayer structures in a direction toward the active layer, and the layer having the lowest energy band gap has an increased thickness in individual multilayer structures in a direction toward the active layer.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Wook Shim, Suk Ho Yoon, Tan Sakong, Je Won Kim, Ki Sung Kim
  • Patent number: 8633469
    Abstract: A Group III nitride semiconductor light-emitting device includes a sapphire substrate; and an n contact layer, an n cladding layer, a light-emitting layer, a p cladding layer, and a p contact layer, each of the layers being formed of Group III nitride semiconductor, are sequentially deposited on the sapphire substrate. The n cladding layer includes two layers of a high impurity concentration layer and a low impurity concentration layer in this order on the n contact layer, and the low impurity concentration layer is in contact with the light-emitting layer. The low impurity concentration layer is a layer having a lower n-type impurity concentration than that of the high impurity concentration layer, which has an n-type impurity concentration of 1/1000 to 1/100 of the p-type impurity concentration of the p cladding layer and a thickness of 10 ? to 400 ?.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: January 21, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Ryo Nakamura
  • Patent number: 8524581
    Abstract: Methods and apparatus for depositing thin films incorporating the use of a surfactant are described. Methods and apparatuses include a deposition process and system comprising multiple isolated processing regions which enables rapid repetition of sub-monolayer deposition of thin films. The use of surfactants allows the deposition of high quality epitaxial films at lower temperatures having low values of surface roughness. The deposition of Group III-V thin films such as GaN is used as an example.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: September 3, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Boris Borisov, Thai Cheng Chua, Sandeep Nijhawan, Yoga Saripalli
  • Patent number: 8507364
    Abstract: An object of the present invention is to realize, by the flux process, the production of a high-quality n-type semiconductor crystal having high concentration of electrons. The method of the invention for producing an n-type Group III nitride-based compound semiconductor by the flux process, the method including preparing a melt by melting at least a Group III element by use of a flux; supplying a nitrogen-containing gas to the melt; and growing an n-type Group III nitride-based compound semiconductor crystal on a seed crystal from the melt. In the method, carbon and germanium are dissolved in the melt, and germanium is incorporated as a donor into the semiconductor crystal, to thereby produce an n-type semiconductor crystal. The mole percentage of germanium to gallium in the melt is 0.05 mol % to 0.5 mol %, and the mole percentage of carbon to sodium is 0.1 mol % to 3.0 mol %.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: August 13, 2013
    Assignees: Toyoda Gosei Co., Ltd., NGK Insulators, Ltd., Osaka University
    Inventors: Seiji Nagai, Shiro Yamazaki, Yasuhide Yakushi, Takayuki Sato, Makoto Iwai, Katsuhiro Imai, Yusuke Mori, Yasuo Kitaoka
  • Patent number: 8415690
    Abstract: Provided is an epitaxial substrate using a silicon substrate as a base substrate. An epitaxial substrate, in which a group of group-III nitride layers are formed on a (111) single crystal Si substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a surface of the substrate, includes: a first group-III nitride layer made of AlN with many defects configured of at least one kind from a columnar or granular crystal or domain; a second group-III nitride layer whose interface with the first group-III nitride layer is shaped into a three-dimensional concave-convex surface; and a third group-III nitride layer epitaxially formed on the second group-III nitride layer as a graded composition layer in which the proportion of existence of Al is smaller in a portion closer to a fourth group-III nitride.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: April 9, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Shigeaki Sumiya, Mikiya Ichimura, Mitsuhiro Tanaka
  • Patent number: 8405102
    Abstract: Disclosed herein is a light emitting device. The light emitting device includes a support member and a light emitting structure on the support member and including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer interposed between the first and second conductive semiconductor layers, and the active layer includes at least one quantum well layer and at least one barrier layer, at least one potential barrier layer located between the first conductive semiconductor layer and a first quantum well layer, closest to the first conductive semiconductor layer, out of the at least one quantum well layer, and an undoped barrier layer formed between the at least one potential barrier layer and the first quantum well layer and having a thickness different from that of the at least one barrier layer. Thereby, brightness of the light emitting device is improved through effective diffusion of current.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: March 26, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventors: Hosang Yoon, Sanghyun Lee, Jongpil Jeong, Seonho Lee
  • Patent number: 8395165
    Abstract: A laterally contacted blue LED device involves a PAN structure disposed over an insulating substrate. The substrate may be a sapphire substrate that has a template layer of GaN grown on it. The PAN structure includes an n-type GaN layer, a light-emitting active layer involving indium, and a p-type GaN layer. The n-type GaN layer has a thickness of at least 500 nm. A Low Resistance Layer (LRL) is disposed between the substrate and the PAN structure such that the LRL is in contact with the bottom of the n-layer. In one example, the LRL is an AlGaN/GaN superlattice structure whose sheet resistance is lower than the sheet resistance of the n-type GnA layer. The LRL reduces current crowding by conducting current laterally under the n-type GaN layer. The LRL reduces defect density by preventing dislocation threads in the underlying GaN template from extending up into the PAN structure.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: March 12, 2013
    Assignee: Bridelux, Inc.
    Inventors: Zhen Chen, William Fenwick, Steve Lester
  • Patent number: 8390006
    Abstract: Provided are a light emitting device, a method of manufacturing the light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a reflective layer including a first GaN-based semiconductor layer having a first refractive index, a second GaN-based semiconductor layer having a second refractive index less than the first refractive index, and a third GaN-based semiconductor layer having a third refractive index less than the second refractive index and a light emitting structure layer including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer on the reflective layer.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: March 5, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventors: Dae Sung Kang, Myung Hoon Jung
  • Publication number: 20130032834
    Abstract: A vertical GaN-based blue LED has an n-type GaN layer that was grown directly on Low Resistance Layer (LRL) that in turn was grown over a silicon substrate. In one example, the LRL is a low sheet resistance GaN/AlGaN superlattice having periods that are less than 300 nm thick. Growing the n-type GaN layer on the superlattice reduces lattice defect density in the n-type layer. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate is then removed. Electrodes are added and the structure is singulated to form finished LED devices. In some examples, some or all of the LRL remains in the completed LED device such that the LRL also serves a current spreading function. In other examples, the LRL is entirely removed so that no portion of the LRL is present in the completed LED device.
    Type: Application
    Filed: August 2, 2011
    Publication date: February 7, 2013
    Applicant: Bridgelux, Inc.
    Inventor: Zhen Chen
  • Patent number: 8343824
    Abstract: Gallium nitride material devices and related processes are described. In some embodiments, an N-face of the gallium nitride material region is exposed by removing an underlying region.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: January 1, 2013
    Assignee: International Rectifier Corporation
    Inventors: Edwin Lanier Piner, Jerry Wayne Johnson, John Claassen Roberts
  • Patent number: 8227284
    Abstract: The present invention provides a group-III nitride compound semiconductor light-emitting device having high productivity and good emission characteristics, a method of manufacturing a group-III nitride compound semiconductor light-emitting device, and a lamp. A method of manufacturing a group-III nitride compound semiconductor light-emitting device includes a step of forming on a substrate 11 a semiconductor layer made of a group-III nitride compound semiconductor including Ga as a group-III element using a sputtering method. The substrate 11 and a sputtering target are arranged so as to face each other, and a gap between the substrate 11 and the sputtering target is in the range of 20 to 100 mm. In addition, when the semiconductor layer is formed by the sputtering method, a bias of more than 0.1 W/cm2 is applied to the substrate 11. Further, when the semiconductor layer is formed, nitrogen and argon are supplied into a chamber used for sputtering.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: July 24, 2012
    Assignee: Showa Denko K.K.
    Inventors: Hisayuki Miki, Kenzo Hanawa, Yasumasa Sasaki
  • Publication number: 20120168717
    Abstract: Disclosed is a light-emitting diode, which has a red and infrared emitting wavelength, excellent monochromatism characteristics, and high output and high efficiency and excellent humidity resistance. The light-emitting diode is provided with: a light-emitting section, which includes an active layer having a quantum well structure and formed by laminating alternately a well layer which comprises a composition expressed by the composition formula of (AlX1Ga1-X1)As (0?X1?1) and a barrier layer which comprises a composition expressed by the composition formula of (AlX2Ga1-X2)As (0<X2?1), and a first clad layer and a second clad layer, between both of which the active layer is sandwiched, wherein the first clad layer and the second clad layer comprise a composition expressed by the composition formula of (AlX3Ga1-X3)Y1In1-Y1P (0?X3?1, 0<Y1?1); a current diffusion layer formed on the light-emitting section; and a functional substrate bonded to the current diffusion layer.
    Type: Application
    Filed: September 15, 2010
    Publication date: July 5, 2012
    Applicant: SHOWA DENKO K.K.
    Inventors: Noriyuki Aihara, Noriyoshi Seo, Noritaka Muraki, Ryouichi Takeuchi
  • Patent number: 8178375
    Abstract: A method of manufacturing a light generating device with required wavelength is disclosed. According to the method, a) a required wavelength is determined. b) A polar angle and an azimuthal angle corresponding to the required wavelength in a nitride semiconductor are determined. Then, c) a nitride semiconductor crystal is grown according to the polar angle and the azimuthal angle. Therefore, a light generating device with required wavelength may be manufactured without adjusting amounts of elements of compound semiconductor.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: May 15, 2012
    Assignee: Wooree LST Co. Ltd.
    Inventors: Do-Yeol Ahn, Seoung-Hwan Park, Jung-Tae Jang
  • Publication number: 20120086027
    Abstract: A group-III nitride compound semiconductor light-emitting device, a method of manufacturing the group-III nitride compound semiconductor light-emitting device, and a lamp. The method includes the steps of: forming an intermediate layer (12) made of a group-III nitride compound on a substrate (11) by activating and reacting gas including a group-V element with a metal material in plasma; and sequentially forming an n-type semiconductor layer (14), a light-emitting layer (15), and a p-type semiconductor layer (16) each made of a group-III nitride compound semiconductor on the intermediate layer (12). Nitrogen is used as the group-V element, and the thickness of the intermediate layer (12) is in the range of 20 to 80 nm.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 12, 2012
    Applicant: SHOWA DENKO K.K.
    Inventors: Yasunori YOKOYAMA, Hisayuki MIKI
  • Patent number: 8154036
    Abstract: A nitride semiconductor device according to the present invention sequentially includes at least an n-electrode, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The n-type semiconductor layer includes: an n-type GaN contact layer including n-type impurity-doped GaN having an electron concentration ranging from 5×1016 cm?3 to 5×1018 cm?3; the n-electrode provided on one of a main surface of the n-type GaN contact layer; and a generating layer provided on other main surface of the n-type GaN contact layer, including at least any one of AlxGa1-xN (0<x<1) and InxGa1-xN (0<x<1), and generates an electron accumulation layer for accumulating layer electrons at a boundary surface with the n-type GaN contact layer.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: April 10, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Ken Nakahara
  • Patent number: 8148714
    Abstract: A method for producing a light-emitting device, includes: performing, on a first substrate made of III-V group compound semiconductor, crystal growth of a laminated body including an etching easy layer contiguous to the first substrate and a light-emitting layer made of nitride semiconductor; bonding a second substrate and the laminated body; and detaching the second substrate provided with the light-emitting layer from the first substrate by, one of removing the etching easy layer by using a solution etching method, and removing the first substrate and the etching easy layer by using mechanical polishing method.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryo Saeki
  • Publication number: 20120074424
    Abstract: Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a conductive heat dissipation substrate (that is, a thermal conductive substrate); an GaN-based multi-layer arranged on the heat dissipation substrate; and a Schottky electrode arranged on the GaN-based multi-layer. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 29, 2012
    Inventor: Jae-hoon LEE
  • Publication number: 20120032209
    Abstract: According to one embodiment, a semiconductor light emitting device includes: semiconductor layers; a multilayered structural body; and a light emitting portion. The multilayered structural body is provided between the semiconductor layers, and includes a first layer and a second layer including In. The light emitting portion is in contact with the multilayered structural body between the multilayered structural body and p-type semiconductor layer, and includes barrier layers and a well layer including In with an In composition ratio among group III elements higher than an In composition ratio among group III elements in the second layer. An average lattice constant of the multilayered structural body is larger than that of the n-type semiconductor layer. Difference between the average lattice constant of the multilayered structural body and that of the light emitting portion is less than difference between that of the multilayered structural body and that of the n-type semiconductor layer.
    Type: Application
    Filed: February 23, 2011
    Publication date: February 9, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomonari SHIODA, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
  • Publication number: 20110291072
    Abstract: A semiconductor die includes at least one first region and at least one second region. The at least one first region is configured to emit light having at least a first wavelength. The at least one second region is configured to emit light having at least a second wavelength, which is different from the first wavelength.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 1, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Taek Kim
  • Publication number: 20110272670
    Abstract: A nitride semiconductor device according to the present invention includes a p-type nitride semiconductor layer, an n-type nitride semiconductor layer, and an active layer interposed between the p-type nitride semiconductor layer and the n-type nitride semiconductor layer. The p-type nitride semiconductor layer includes: a first p-type nitride semiconductor layer containing Al and Mg; and a second p-type nitride semiconductor layer containing Mg. The first p-type nitride semiconductor layer is located between the active layer and the second p-type nitride semiconductor layer, and the second p-type nitride semiconductor layer has a greater band gap than a band gap of the first p-type nitride semiconductor layer.
    Type: Application
    Filed: June 16, 2011
    Publication date: November 10, 2011
    Inventors: Yasutoshi KAWAGUCHI, Toshitaka SHIMAMOTO, Akihiko ISHIBASHI, Isao KIDOGUCHI, Toshiya YOKOGAWA
  • Patent number: 8053806
    Abstract: A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device 11a includes a group III nitride semiconductor supporting base 13, a GaN based semiconductor region 15, an active layer active layer 17, and a GaN semiconductor region 19. The primary surface 13a of the group III nitride semiconductor supporting base 13 is not any polar plane, and forms a finite angle with a reference plane Sc that is orthogonal to a reference axis Cx extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region 15 is grown on the semipolar primary surface 13a. A GaN based semiconductor layer 21 of the GaN based semiconductor region 15 is, for example, an n-type GaN based semiconductor, and the n-type GaN based semiconductor is doped with silicon.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: November 8, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Yusuke Yoshizumi, Yohei Enya, Katsushi Akita, Masaki Ueno, Takamichi Sumitomo, Takao Nakamura
  • Publication number: 20110248281
    Abstract: A nitride semiconductor substrate includes two principal surfaces including an upper surface that is a growth face and a lower surface on its opposite side. An FWHM in a surface layer region at depths of from 0 to 250 nm from the upper surface is narrower than an FWHM in an inner region at depths exceeding 5 ?m from the upper surface, where the FWHMs are obtained by X-ray rocking curve measurement using diffraction off a particular asymmetric plane inclined relative to the upper surface.
    Type: Application
    Filed: August 2, 2010
    Publication date: October 13, 2011
    Applicant: Hitachi Cable, Ltd.
    Inventors: Yuichi Oshima, Takehiro Yoshida
  • Patent number: 8026534
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: September 27, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Publication number: 20110215295
    Abstract: A method of producing a radiation-emitting thin film component includes providing a substrate, growing nanorods on the substrate, growing a semiconductor layer sequence with at least one active layer epitaxially on the nanorods, applying a carrier to the semiconductor layer sequence, and detaching the semiconductor layer sequence and the carrier from the substrate by at least partial destruction of the nanorods.
    Type: Application
    Filed: October 19, 2009
    Publication date: September 8, 2011
    Applicant: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Hans-Jurgen Lugauer, Klaus Streubel, Martin Strassburg, Reiner Windisch, Karl Engl
  • Publication number: 20110198562
    Abstract: Provided is a light emitting device. In one embodiment, a light emitting device includes: a substrate including ?-Ga203; a light emitting structure on the substrate, the light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; an electrode on the light emitting structure; and a porous layer at a lateral surface region of the substrate.
    Type: Application
    Filed: February 8, 2011
    Publication date: August 18, 2011
    Inventors: Yong Tae Moon, Jeong Soon Yim, Jeong Sik Lee
  • Publication number: 20110186883
    Abstract: A light emitting device includes a light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer, and a light extraction structure that extracts light from the light emitting structure. The light extraction structure includes at least a first light extraction zone and a second light extraction zone, where a period and/or size of first concave and/or convex structures of the first light extraction zone is different from a period and/or size of second concave and/or convex structures of the second light extraction zone.
    Type: Application
    Filed: October 7, 2010
    Publication date: August 4, 2011
    Applicant: LG Innotek Co., Ltd.
    Inventor: Sun Kyung KIM
  • Publication number: 20110186882
    Abstract: Provided are a light emitting device, a method of manufacturing the light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a reflective layer including a first GaN-based semiconductor layer having a first refractive index, a second GaN-based semiconductor layer having a second refractive index less than the first refractive index, and a third GaN-based semiconductor layer having a third refractive index less than the second refractive index and a light emitting structure layer including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer on the reflective layer.
    Type: Application
    Filed: November 17, 2010
    Publication date: August 4, 2011
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Dae Sung KANG, Myung Hoon JUNG
  • Publication number: 20110175057
    Abstract: The device including an active layer composed of AlGaInP, and an n-type clad layer and a p-type clad layer disposed so as to sandwich the active layer, the n-type clad layer and the p-type clad layer each having a bandgap greater than the bandgap of the active layer. The n-type clad layer includes a first n-type clad layer composed of AlGaInP and a second n-type clad layer composed of AlInP; and the second n-type clad layer has a thickness in the range from 40 nm to 200 nm.
    Type: Application
    Filed: January 19, 2011
    Publication date: July 21, 2011
    Applicant: STANLEY ELECTRIC CO., LTD.
    Inventors: Wataru TAMURA, Chiharu Sasaki
  • Publication number: 20110163324
    Abstract: A light emitting diode of one embodiment includes a light emitting device having a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on an upper layer of the plurality of N-type semiconductor layers, and a P-type semiconductor layer on the active layer. The first N-type semiconductor layer includes a first Si doped Nitride layer and the second N-type semiconductor layer includes a second Si doped Nitride layer. The first and second N-type semiconductor layers have a Si impurity concentration different from each other.
    Type: Application
    Filed: March 11, 2011
    Publication date: July 7, 2011
    Inventor: Tae Yun KIM
  • Publication number: 20110147763
    Abstract: According to the present invention, an AlN crystal film seed layer having high crystallinity is combined with selective/lateral growth, whereby a Group III nitride semiconductor multilayer structure more enhanced in crystallinity can be obtained. The Group III nitride semiconductor multilayer structure of the present invention is a Group III nitride semiconductor multilayer structure where an AlN crystal film having a crystal grain boundary interval of 200 nm or more is formed as a seed layer on a C-plane sapphire substrate surface by a sputtering method and an underlying layer, an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer, each composed of a Group III nitride semiconductor, are further stacked, wherein regions in which the seed layer is present and is absent are formed on the C-plane sapphire substrate surface and/or regions capable of epitaxial growth and incapable of epitaxial growth are formed in the underlying layer.
    Type: Application
    Filed: July 30, 2009
    Publication date: June 23, 2011
    Applicant: SHOWA DENKO K.K.
    Inventors: Kenzo Hanawa, Yasumasa Sasaki
  • Publication number: 20110147772
    Abstract: Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. The method can further include forming a volume of gallium nitride carried by the crystals, with the selected orientation of the crystals at least partially controlling a crystal orientation of the gallium nitride, and without bonding the gallium nitride, as a unit, to the support member. In other embodiments, the number of crystals can be increased by a process that includes annealing a region in which the crystals are present, etching the region to remove crystals having an orientation other than the selected orientation, and/or growing the crystals having the selected orientation.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 23, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Anthony Lochtefeld, Hugues Marchand
  • Publication number: 20110143467
    Abstract: One embodiment of the present invention provides a method for fabricating an InGaAlN light-emitting semiconductor structure. During the fabrication process, at least one single-crystal sacrificial layer is deposited on the surface of a base substrate to form a combined substrate, wherein the single-crystal sacrificial layer is lattice-matched with InGaAlN, and wherein the single crystal layer forms a sacrificial layer. Next, the InGaAlN light-emitting semiconductor structure is fabricated on the combined substrate. The InGaAlN structure fabricated on the combined substrate is then transferred to a support substrate, thereby facilitating a vertical electrode configuration. Transferring the InGaAlN structure involves etching the single-crystal sacrificial layer with a chemical etchant. Furthermore, the InGaAlN and the base substrate are resistant to the chemical etchant. The base substrate can be reused after the InGaAlN structure is transferred.
    Type: Application
    Filed: August 22, 2008
    Publication date: June 16, 2011
    Applicant: LATTICE POWER (JIANGXI) CORPORATION
    Inventors: Chuanbing Xiong, Fengyi Jiang, Li Wang, Shaohua Zhang, Guping Wang, Guangxu Wang
  • Patent number: 7943964
    Abstract: An AlxGayIn1-x-yN crystal substrate of the present invention has a main plane having an area of at least 10 cm2. The main plane has an outer region located within 5 mm from an outer periphery of the main plane, and an inner region corresponding to a region other than the outer region. The inner region has a total dislocation density of at least 1×102 cm?2 and at most 1×106 cm?2. It is thereby possible to provide an AlxGayIn1-x-yN crystal substrate having a large size and a suitable dislocation density for serving as a substrate for a semiconductor device, a semiconductor device including the AlxGayIn1-x-yN crystal substrate, and a method of manufacturing the same.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: May 17, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinsuke Fujiwara, Tomoki Uemura, Takuji Okahisa, Koji Uematsu, Manabu Okui, Muneyuki Nishioka, Shin Hashimoto
  • Patent number: 7928471
    Abstract: A structure including a Si1-xGex substrate and a distributed Bragg reflector layer disposed directly onto the substrate. The distributed Bragg reflector layer includes a repeating pattern that includes at least one aluminum nitride layer and a second layer having the general formula AlyGa1-yN. Another aspect of the present invention is various devices including this structure. Another aspect of the present invention is directed to a method of forming such a structure comprising providing a Si1-xGex substrate and depositing a distributed Bragg reflector layer directly onto the substrate. Another aspect of the present invention is directed to a photodetector or photovoltaic cell device, including a Si1-xGex substrate device, a group III-nitride device and contacts to provide a conductive path for a current generated across at least one of the Si1-xGex substrate device and the group III-nitride device upon incident light.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: April 19, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Michael A. Mastro, Charles R. Eddy, Jr., Shahzad Akbar
  • Patent number: 7880187
    Abstract: Radiation occurs when current is injected into an active layer from electrodes. A pair of clad layers is disposed sandwiching the active layer, the clad layer having a band gap wider than a band gap of the active layer. An optical absorption layer is disposed outside at least one clad layer of the pair of clad layers. The optical absorption layer has a band gap wider than the band gap of the active layer and narrower than the band gap of the clad layer. A spread of a spectrum of radiated light can be narrowed.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: February 1, 2011
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Ken Sasakura, Keizo Kawaguchi, Hanako Ono
  • Patent number: 7879632
    Abstract: Provided is a method for manufacturing a surface-emitting laser capable of forming a photonic crystal structure inside a semiconductor highly accurately and easily without direct bonding. It is a method by laminating on a substrate a plurality of semiconductor layers including an active layer and a semiconductor layer having a photonic crystal structure formed therein, the method including the steps of forming a second semiconductor layer on a first semiconductor layer to form the photonic crystal structure, forming a plurality of microholes in the second semiconductor layer, forming a low refractive index portion in a part of the first semiconductor layer via the plurality of microholes thereby to provide the first semiconductor layer with the photonic crystal structure having a one-dimensional or two-dimensional refractive index distribution in a direction parallel to the substrate, and forming a third semiconductor layer by crystal regrowth from a surface of the second semiconductor layer.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: February 1, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsuhiro Ikuta
  • Patent number: 7867803
    Abstract: A Metal Organic Vapor Phase Epitaxy step of growing a light emitting layer section 24, composed of a first Group III-V compound semiconductor, epitaxially on a single crystal growth substrate 1 by Metal Organic Vapor Phase Epitaxy, and a Hydride Vapor Phase Epitaxial Growth step of growing a current spreading layer 7 on the light emitting layer section 24 epitaxially by Hydride Vapor Phase Epitaxial Growth Method, are conducted in this order. Then, the current spreading layer 7 is grown, having a low-rate growth layer 7a positioned close to the light emitting layer side and then a high-rate growth layer 7b, having a growth rate of the low-rate growth layer 7a lower than that of the high-rate growth layer 7b, so as to provide a method of fabricating a light emitting device capable of preventing hillock occurrence while forming the thick current spreading layer.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: January 11, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumitaka Kume, Masayuki Shinohara
  • Patent number: 7847302
    Abstract: A technique for forming a white light LED is disclosed. In one embodiment, the LED emits blue light. A first phosphor for producing red, yellow, yellow-green, or green light is formed to conformably coat the LED die. One suitable deposition technique is electrophoretic deposition (EPD). Over the resulting LED structure is deposited another phosphor (to add the remaining color component) in a binder (e.g., silicone) for encapsulating the die. The blue LED light combines with the two phosphor colors to create white light. Since the two different deposition techniques are independent and easily controllable, the resulting white light temperature is highly controllable and the color emission is substantially uniform.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: December 7, 2010
    Assignees: Koninklijke Philips Electronics, N.V., Philips Lumileds Lighting, LLC
    Inventors: Grigoriy Basin, Paul S. Martin, Robert Scott West, Yasumasa Morita, Tewe Heemstra