Having Heterojunction Or Graded Gap (epo) Patents (Class 257/E33.048)
  • Patent number: 11881499
    Abstract: A micro-LED display panel includes a substrate, an insulating layer on the substrate, and a plurality of micro-LEDs on the substrate and embedded in the insulating layer. The micro-LEDs define a display area. Each micro-LED includes a bottom surface coupled to a lower electrode and a top surface exposed from the insulating layer and coupled to the upper electrode. Conductive blocks are set outside the display area, the conductive blocks are electrically coupled to a driving circuit on the substrate. Top wires are set on a surface of the insulating layer away from the substrate and each top wire is electrically coupled to at least one upper electrode and at least one conductive block.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: January 23, 2024
    Assignee: Century Technology (Shenzhen) Corporation Limited
    Inventor: Chiao-Yu Yang
  • Patent number: 11621369
    Abstract: A semiconductor device can define a plurality of points on the basis of an In ion concentration, a first dopant concentration, and a second dopant concentration, and identify each layer on the basis of a region between the points defined as above. The Mg concentration in a specific layer may increase along a specific direction and then decrease.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: April 4, 2023
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventors: Dae Seob Han, Kwang Sun Baek, Young Suk Song
  • Patent number: 11499707
    Abstract: A lighting fixture is disclosed with effective disinfection properties against bacteria, fungi, and viruses. The fixture includes a fan to continuously draw air into the light fixture. The air drawn in is irradiated with UV radiation within the fixture, such as is provided from UV LED chips. The relatively small volume of the light fixture allows the flux or energy density of the UV radiation to be made more intense. After the air is sterilized, it can be put back into the room or building in which the fixture is placed. The white light provided by white light LEDs in the fixture provides illumination, and can further provide significant emission peaks at 405 nm and 470 nm which is also useful to pathogen inactivation.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: November 15, 2022
    Assignee: CalyxPure, Inc.
    Inventors: John C. Higgins, Mark Sam
  • Patent number: 11355662
    Abstract: A method of manufacturing a nitride semiconductor light emitting element includes: growing an n-side nitride semiconductor layer; growing an active layer on the n-side nitride semiconductor layer; and growing a p-side nitride semiconductor layer on the active layer, which includes: growing a first p-side nitride semiconductor layer, growing a second p-side nitride semiconductor layer, growing a third p-side nitride semiconductor layer, and growing a fourth p-side nitride semiconductor layer, while varying flow rates of an Al source gas, a Ga source gas, an N source gas, and a Mg source gas.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: June 7, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Hiroki Kondo
  • Patent number: 10446705
    Abstract: A quantum well device includes a first layer of a first two-dimensional material, a second layer of a second two-dimensional material, and a third layer of a third two-dimensional material disposed between the first layer and second layer. The first layer, the second layer, and the third layer are adhered predominantly by van der Waals force.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: October 15, 2019
    Assignee: Konica Minolta Laboratory U.S.A., Inc.
    Inventor: Jun Amano
  • Patent number: 9041027
    Abstract: A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a spinel substrate using a sacrificial buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The sacrificial buffer material and semiconductor materials may be deposited using lattice-matching epitaxy or coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The sacrificial buffer layer may be dissolved using an epitaxial liftoff technique in order to separate the semiconductor device from the spinel substrate, and the spinel substrate may be reused in the subsequent fabrication of other semiconductor devices.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: May 26, 2015
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Aaron Joseph Ptak, Yong Lin, Andrew Norman, Kirstin Alberi
  • Patent number: 9000414
    Abstract: An object of the present invention is to provide a light emitting diode having a heterogeneous material structure and a method of manufacturing thereof, in which efficiency of extracting light to outside is improved by forming depressions and prominences configured of heterogeneous materials different from each other before or in the middle of forming a semiconductor material on a substrate in order to improve the light extraction efficiency.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: April 7, 2015
    Assignee: Korea Photonics Technology Institute
    Inventors: Sang-Mook Kim, Jong-Hyeob Baek
  • Patent number: 8872308
    Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: October 28, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
  • Patent number: 8779437
    Abstract: According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8754445
    Abstract: A layer in which the potential level difference normally unrequired for device operation is generated is positively inserted in a device structure. The potential level difference has such a function that even if a semiconductor having a small bandgap is exposed on a mesa side surface, a potential drop amount of the portion is suppressed, and a leakage current inconvenient for device operation can be reduced. This effect can be commonly obtained for a heterostructure bipolar transistor, a photodiode, an electroabsorption modulator, and so on. In the photodiode, since the leakage current is alleviated, the device size can be reduced, so that in addition to improvement of operating speed with a reduction in series resistance, it is advantageous that the device can be densely disposed in an array.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: June 17, 2014
    Assignees: NTT Electronics Corporation, Nippon Telegraph and Telephone Corporation
    Inventors: Tadao Ishibashi, Seigo Ando, Yoshifumi Muramoto, Toshihide Yoshimatsu, Haruki Yokoyama
  • Patent number: 8653501
    Abstract: Provided is an emitting device which is capable of improving the luminous efficiency of an emitting layer formed using a group IV semiconductor material and obtaining an emission spectrum having a narrow band, and a manufacturing method therefor. The emitting device comprises: an emitting layer having a potential confinement structure, comprising: a well region comprising a group IV semiconductor material; and a barrier region being adjacent to the well region and comprising a group IV semiconductor material which is different from the group IV semiconductor material in the well region, wherein: a continuous region from the well region over an interface between the well region and the barrier region to a part of the barrier region comprises fine crystals; and a region in the barrier region, which is other than the continuous region comprising the fine crystals, is amorphous or polycrystalline region.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: February 18, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsuya Takeuchi, Tatsuro Uchida, Mitsuhiro Ikuta
  • Patent number: 8647905
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part provided therebetween. The light emitting part includes a plurality of light emitting layers. Each of the light emitting layers includes a well layer region and a non-well layer region which is juxtaposed with the well layer region in a plane perpendicular to a first direction from the n-type semiconductor layer towards the p-type semiconductor layer. Each of the well layer regions has a common An In composition ratio. Each of the well layer regions includes a portion having a width in a direction perpendicular to the first direction of 50 nanometers or more.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: February 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Harada, Toshiki Hikosaka, Tomonari Shioda, Koichi Tachibana, Hajime Nago, Shinya Nunoue
  • Patent number: 8633496
    Abstract: Provided is an optical device including a base wafer containing silicon, a plurality of seed crystals disposed on the base wafer, and a plurality of Group 3-5 compound semiconductors lattice-matching or pseudo lattice-matching the plurality of seed crystals. At least one of the Group 3-5 compound semiconductors has a photoelectric semiconductor formed therein, the photoelectric semiconductor including a light emitting semiconductor that emits light in response to a driving current supplied thereto or a light receiving semiconductor that generates a photocurrent in response to light applied thereto, and at least one of the plurality of Group 3-5 compound semiconductors other than the Group 3-5 compound semiconductor having the photoelectric semiconductor has a heterojunction transistor formed therein.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: January 21, 2014
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Masahiko Hata, Sadanori Yamanaka, Tomoyuki Takada
  • Patent number: 8536615
    Abstract: A semiconductor device may include a doped semiconductor region wherein a dopant concentration of the semiconductor region is modulated over a plurality of intervals. Each interval may include at least one portion having a relatively low dopant concentration and at least one portion having a relatively high dopant concentration. A plurality of delta doped layers may be included in the plurality of intervals. Related methods are also discussed.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: September 17, 2013
    Assignee: Cree, Inc.
    Inventors: Daniel Carleton Driscoll, Ashonita Chavan, Adam William Saxler
  • Patent number: 8525197
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part provided therebetween. The light emitting part includes a plurality of light emitting layers. Each of the light emitting layers includes a well layer region and a non-well layer region which is juxtaposed with the well layer region in a plane perpendicular to a first direction from the n-type semiconductor layer towards the p-type semiconductor layer. Each of the well layer regions has a common An In composition ratio. Each of the well layer regions includes a portion having a width in a direction perpendicular to the first direction of 50 nanometers or more.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Harada, Toshiki Hikosaka, Tomonari Shioda, Koichi Tachibana, Hajime Nago, Shinya Nunoue
  • Patent number: 8519437
    Abstract: A light emitting device comprising a three-dimensional polarization-graded (3DPG) structure that improves lateral current spreading within the device without introducing additional dopant impurities in the epitaxial structures. The 3DPG structure can include a repeatable stack unit that may be repeated several times within the 3DPG. The stack unit includes a compositionally graded layer and a silicon (Si) delta-doped layer. The graded layer is compositionally graded over a distance from a first material to a second material, introducing a polarization-induced bulk charge into the structure. The Si delta-doped layer compensates for back-depletion of the electron gas at the interface of the graded layers and adjacent layers. The 3DPG facilitates lateral current spreading so that current is injected into the entire active region, increasing the number of radiative recombination events in the active region and improving the external quantum efficiency and the wall-plug efficiency of the device.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: August 27, 2013
    Assignee: Cree, Inc.
    Inventor: Arpan Chakraborty
  • Patent number: 8519378
    Abstract: Semiconductor surface emitting elements having a plurality of wavelengths being manufactured on a signal substrate through MOVPE selective growth. More specifically, provided is a semiconductor light emitting element array which comprises; a semiconductor crystal substrate; an insulating film disposed on a surface of the substrate, the insulating film being divided into two or more regions, each of which having two or more openings exposing the surface of the substrate; semiconductor rods extending from the surface of the substrate upward through the openings, the semiconductor rods each having an n-type semiconductor layer and a p-type semiconductor layer being laminated in its extending direction, thereby providing a p-n junction; a first electrode connected to the semiconductor crystal substrate; and a second electrode connected to upper portions of the semiconductor rods; wherein the heights of the semiconductor rods as measured from the substrate surface vary by each of the two or more regions.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: August 27, 2013
    Assignees: National University Corporation Hokkaido University, Sharp Kabushiki Kaisha
    Inventors: Kenji Hiruma, Shinjiro Hara, Junichi Motohisa, Takashi Fukui
  • Patent number: 8421195
    Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: April 16, 2013
    Inventor: G. R. Mohan Rao
  • Publication number: 20130050810
    Abstract: Wavelength converters for solid state lighting devices, and associated systems and methods. A system in accordance with a particular embodiment includes a solid state radiative semiconductor structure having a first region and a second region. The first region is positioned to receive radiation at a first wavelength and has a first composition and an associated first bandgap energy. The second region is positioned adjacent to the first region to receive energy from the first region and emit radiation at a second wavelength different than the first wavelength. The second region has a second composition different than the first composition, and an associated second bandgap energy that is less than the first bandgap energy.
    Type: Application
    Filed: August 23, 2011
    Publication date: February 28, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov
  • Publication number: 20130032810
    Abstract: A vertical GaN-based blue LED has an n-type GaN layer that was grown over a ZnS layer that in turn was grown directly on a silicon substrate. In one example, the ZnS layer is a transitional buffer layer that is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type layer. The ZnS buffer layer provides a good lattice constant match with the silicon substrate and provides a compound polar template for subsequent GaN growth. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate and the ZnS buffer layer are then removed. Electrodes are added and the structure is singulated to form finished LED devices.
    Type: Application
    Filed: August 3, 2011
    Publication date: February 7, 2013
    Applicant: Bridgelux, Inc.
    Inventor: Zhen Chen
  • Patent number: 8367449
    Abstract: A semiconductor light-emitting apparatus that has high luminous efficiency and a high breakdown voltage as well as reduced breakdown voltage variation among lots. The semiconductor light-emitting apparatus includes a first clad layer and a second clad layer. An average dopant concentration of the second clad layer is lower than that of the first clad layer. The light-emitting apparatus also includes an active layer having an average dopant concentration of 2×1016 to 4×1016 cm?3. The active layer is made of (AlyGa1-y)xIn1-xP (0<x?1, 0?y?1). The light-emitting apparatus also includes a third clad layer, and a second-conducting-type semiconductor layer made of Ga1-xInxP (0?x<1). If d is the layer thickness of the second clad layer (nm) and Nd1 is the average dopant concentration of the second clad layer (cm?3), then d?1.2×Nd1×10?15+150 is satisfied.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: February 5, 2013
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Chiharu Sasaki, Wataru Tamura, Keita Akiyama
  • Patent number: 8344422
    Abstract: A semiconductor device includes a lower barrier layer 12 composed of a layer of AlxGa1-xN (0?x?1) in a state of strain relaxation, and a channel layer 13, which is composed of a layer of InyGa1-yN (0?y?1) disposed on the lower barrier layer 12, has band gap that is smaller than band gap of the lower barrier layer 12, and exhibits compressive strain. A gate electrode 1G is formed over the channel layer 13 via an insulating film 15 and a source electrode 1S and a drain electrode 1D serving as ohmic electrodes are formed over the channel layer 13. The insulating film 15 is constituted of polycrystalline or amorphous member.
    Type: Grant
    Filed: December 25, 2008
    Date of Patent: January 1, 2013
    Assignee: NEC Corporation
    Inventors: Yuji Ando, Yasuhiro Okamoto, Kazuki Ota, Takashi Inoue, Tatsuo Nakayama, Hironobu Miyamoto
  • Publication number: 20120327422
    Abstract: Provided is a semiconductor optical integrated device, formed by arranging a light emitting element and a light detecting element in a plane of the same substrate, each formed by laminating layers which at least include a first clad layer of a first conductive type, an active layer and a second clad layer of a second conductive type on a substrate, wherein the active layer has a structure where a second active area of a conductive type and an undoped first active area are laminated, and the second active area has the same conductive type as that of the first or second clad layer laminated in the closest position to the second active area. This device suppresses heat generation due to increased operating current and unnecessary light generation at an operation of the light emitting element, and enhancing light absorption efficiency at the an operation of the light emitting element.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 27, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yasuhisa Inao, Mamoru Uchida, Takeshi Uchida
  • Publication number: 20120292592
    Abstract: According to one embodiment, a semiconductor light emitting device includes: first and second semiconductor layers, a light emitting part, and an In-containing layer. The first semiconductor layer is formed on a silicon substrate via a foundation layer. The light emitting part is provided on the first semiconductor layer, and includes barrier layers and a well layer provided between the barrier layers including Ga1-z1Inz1N (0<z1?1). The second semiconductor layer is provided on the light emitting part. The In-containing layer is provided at at least one of first and second positions. The first position is between the first semiconductor layer and the light emitting part. The second position is between the second semiconductor layer and the light emitting part. The In-containing layer includes In with a composition ratio different from the In composition ratio z1 and has a thickness 10 nm to 1000 nm.
    Type: Application
    Filed: August 26, 2011
    Publication date: November 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jongil HWANG, Tomonari Shioda, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8304792
    Abstract: A semiconductor light emitting apparatus is supplied capable of providing a high performance that can optimize simultaneously both an electrical characteristic and a light emitting characteristic.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: November 6, 2012
    Assignee: Oki Data Corporation
    Inventors: Yusuke Nakai, Hironori Furuta, Mitsuhiko Ogihara, Hiroyuki Fujiwara
  • Patent number: 8294178
    Abstract: There is provided a light emitting device using a compound semiconductor, which can improve electrical characteristics and internal quantum efficiency by maximizing the recombination rate of electrons and holes in an active layer. The light emitting device using a compound semiconductor includes a substrate; a compound semiconductor layer formed on the substrate, the compound semiconductor layer comprising an active layer; and a current spreading layer formed on at least one of the top and bottom surfaces of the active layer, the current spreading layer allowing electrons or holes to be uniformly spread into the active layer.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: October 23, 2012
    Assignee: Wooree E&L Co., Ltd.
    Inventors: Bun-Hei Koo, Jae-Eung Oh
  • Publication number: 20120217473
    Abstract: An improved light emitting heterostructure is provided. The heterostructure includes an active region having a set of barrier layers and a set of quantum wells, each of which is adjoined by a barrier layer. The quantum wells have a delta doped p-type sub-layer located therein, which results in a change of the band structure of the quantum well. The change can reduce the effects of polarization in the quantum wells, which can provide improved light emission from the active region.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 30, 2012
    Inventors: Michael Shur, Remigijus Gaska
  • Patent number: 8253215
    Abstract: A two-terminal mesa phototransistor and a method for making it are disclosed. The photo transistor has a mesa structure having a substantially planar semiconductor surface. In the mesa structure is a first semiconductor region of a first doping type, and a second semiconductor region of a second doping type opposite to that of the first semiconductor region, forming a first semiconductor junction with the first region. In addition, a third semiconductor region of the first doping type forms a second semiconductor junction with the second region. The structure also includes a dielectric layer. The second semiconductor region, first semiconductor junction, and second semiconductor junction each has an intersection with the substantially planar semiconductor surface. The dielectric covers, and is in physical contact with, all of the intersections.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: August 28, 2012
    Assignee: Wavefront Holdings, LLC
    Inventor: Jie Yao
  • Publication number: 20120187368
    Abstract: A sensing device is used to detect the spatial distributions of stresses applied by physical contact with the surface of the sensor or induced by pressure, temperature gradients, and surface absorption. The sensor comprises a hybrid active layer that includes luminophores doped in a polymeric or organic host, altogether embedded in a matrix. Under an electrical bias, the sensor simultaneously converts stresses into electrical and optical signals. Among many applications, the device may be used for tactile sensing and biometric imaging.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 26, 2012
    Applicant: West Virginia University
    Inventor: Xian-An Cao
  • Publication number: 20120175676
    Abstract: A photodetector detects the absence or presence of light by detecting a change in the inductance of a coil. The magnetic field generated when a current flows through the coil passes through an electron-hole generation region. Charged particles in the electron-hole generation region come under the influence of the magnetic field, and generate eddy currents whose magnitudes depend on whether light is absent or present. The eddy currents generate a magnetic field that opposes the magnetic field generated by current flowing through the coil.
    Type: Application
    Filed: January 11, 2011
    Publication date: July 12, 2012
    Inventors: Ann Gabrys, Peter J. Hopper, William French, Kyuwoon Hwang
  • Patent number: 8207545
    Abstract: This light-emitting device includes a first electrode, a second electrode disposed opposite to the first electrode and a phosphor layer which is sandwiched between the first electrode and the second electrode and constituted by dispersing n-type semiconductor particles in a p-type semiconductor medium. A light-emitting device in another embodiment includes a first electrode, a second electrode disposed opposite to the first electrode and a phosphor layer which is sandwiched between the first electrode and the second electrode wherein a p-type semiconductor is segregated among the n-type semiconductor particles.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: June 26, 2012
    Assignee: Panasonic Corporation
    Inventors: Eiichi Satoh, Shogo Nasu, Reiko Taniguchi, Toshiyuki Aoyama, Masayuki Ono, Kenji Hasegawa, Masaru Odagiri
  • Publication number: 20120138889
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting part, and a p-side electrode. The light emitting part is provided between the n-type and the p-type semiconductor layers, and includes a plurality of barrier layers and a plurality of well layers. The p-side electrode contacts the p-type semiconductor layer. The p-type semiconductor layer includes first, second, third, and fourth p-type layers. The first p-type layer contacts the p-side electrode. The second p-type layer contacts the light emitting part. The third p-type layer is provided between the first p-type layer and the second p-type layer. The fourth p-type layer is provided between the second p-type layer and the third p-type layer. The second p-type layer contains Al and contains a p-type impurity in a lower concentration lower than that in the first concentration.
    Type: Application
    Filed: August 4, 2011
    Publication date: June 7, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi TACHIBANA, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
  • Patent number: 8164105
    Abstract: Disclosed is a light emitting device. The light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, the second conductive semiconductor layer comprising a first area and a second area, a third conductive semiconductor layer on the second area of the second conductive semiconductor layer, a first electrode layer electrically connecting the first conductive semiconductor layer with the second conductive semiconductor layer of the second area, and a second electrode layer electrically connecting the second conductive semiconductor layer with the third conductive semiconductor layer.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: April 24, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyung Jo Park
  • Patent number: 8148714
    Abstract: A method for producing a light-emitting device, includes: performing, on a first substrate made of III-V group compound semiconductor, crystal growth of a laminated body including an etching easy layer contiguous to the first substrate and a light-emitting layer made of nitride semiconductor; bonding a second substrate and the laminated body; and detaching the second substrate provided with the light-emitting layer from the first substrate by, one of removing the etching easy layer by using a solution etching method, and removing the first substrate and the etching easy layer by using mechanical polishing method.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryo Saeki
  • Publication number: 20120068207
    Abstract: Provided is an optical device including a base wafer containing silicon, a plurality of seed crystals disposed on the base wafer, and a plurality of Group 3-5 compound semiconductors lattice-matching or pseudo lattice-matching the plurality of seed crystals. At least one of the Group 3-5 compound semiconductors has a photoelectric semiconductor formed therein, the photoelectric semiconductor including a light emitting semiconductor that emits light in response to a driving current supplied thereto or a light receiving semiconductor that generates a photocurrent in response to light applied thereto, and at least one of the plurality of Group 3-5 compound semiconductors other than the Group 3-5 compound semiconductor having the photoelectric semiconductor has a heterojunction transistor formed therein.
    Type: Application
    Filed: December 2, 2011
    Publication date: March 22, 2012
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Masahiko HATA, Sadanori Yamanaka, Tomoyuki Takada
  • Publication number: 20120043526
    Abstract: Disclosed are a light emitting device and a lighting system having the same. The light emitting device includes a first conductivity-type semiconductor layer, an interfacial layer including at least two superlattice structures adjacent to the first conductivity-type semiconductor layer, an active layer adjacent to the interfacial layer, and a second conductivity-type semiconductor layer adjacent to the active layer. The first conductivity-type semiconductor layer, interfacial layer, active layer, and second conductivity-type semiconductor layer are stacked in a same direction, the first and second semiconductor layer are of different conductivity types, an energy band gap of the superlattice structure adjacent to the active layer is smaller than an energy band gap of the superlattice structure adjacent to the first conductivity-type semiconductor layer.
    Type: Application
    Filed: November 3, 2011
    Publication date: February 23, 2012
    Inventors: Yong Tae MOON, Dae Seob Han, Jeong Sik Lee
  • Publication number: 20120032143
    Abstract: Provided is an emitting device which is capable of improving the luminous efficiency of an emitting layer formed using a group IV semiconductor material and obtaining an emission spectrum having a narrow band, and a manufacturing method therefor. The emitting device comprises: an emitting layer having a potential confinement structure, comprising: a well region comprising a group IV semiconductor material; and a barrier region being adjacent to the well region and comprising a group IV semiconductor material which is different from the group IV semiconductor material in the well region, wherein: a continuous region from the well region over an interface between the well region and the barrier region to a part of the barrier region comprises fine crystals; and a region in the barrier region, which is other than the continuous region comprising the fine crystals, is amorphous or polycrystalline region.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 9, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Takeuchi, Tatsuro Uchida, Mitsuhiro Ikuta
  • Publication number: 20120032210
    Abstract: The present invention introduces the novel, improved design approach of the semiconductor devices that utilize the effect of carrier recombination, for example, to produce the electromagnetic radiation. The approach is based on the separate control over the injection of the electrons and holes into the active region of the device. As a result, better recombination efficiencies can be achieved, and the effect of the wavelength shift of the produced radiation can be eliminated. The devices according to the present invention outperform existing solid state light and electromagnetic radiation sources and can be used in any applications where solid state light sources are currently involved, as well as any applications future discovered.
    Type: Application
    Filed: August 3, 2011
    Publication date: February 9, 2012
    Inventors: Alexei Koudymov, Christian Martin Wetzel
  • Publication number: 20120012814
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part provided therebetween. The light emitting part includes a plurality of light emitting layers. Each of the light emitting layers includes a well layer region and a non-well layer region which is juxtaposed with the well layer region in a plane perpendicular to a first direction from the n-type semiconductor layer towards the p-type semiconductor layer. Each of the well layer regions has a common An In composition ratio. Each of the well layer regions includes a portion having a width in a direction perpendicular to the first direction of 50 nanometers or more.
    Type: Application
    Filed: February 25, 2011
    Publication date: January 19, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki HARADA, Toshiki Hikosaka, Tomonari Shioda, Koichi Tachibana, Hajime Nago, Shinya Nunoue
  • Publication number: 20120007113
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a well layer, a barrier layer, an Al-containing layer, and an intermediate layer. The p-type semiconductor layer is provided on a side of [0001] direction of the n-type semiconductor layer. The well layer, the barrier layer, the Al-containing layer and the intermediate layer are disposed between the n-type semiconductor layer and the p-type semiconductor layer subsequently. The Al-containing layer has a larger band gap energy than the barrier layer, a smaller lattice constant than the n-type semiconductor layer, and a composition of Alx1Ga1-x1-y1Iny1N. The intermediate layer has a larger band gap energy than the well layer, and has a first portion and a second portion provided between the first portion and the p-type semiconductor layer. A band gap energy of the first portion is smaller than that of the second portion.
    Type: Application
    Filed: February 23, 2011
    Publication date: January 12, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jongil Hwang, Shinji Saito, Maki Sugai, Rei Hashimoto, Yasushi Hattori, Masaki Tohyama, Shinya Nunoue
  • Publication number: 20110316019
    Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.
    Type: Application
    Filed: September 8, 2011
    Publication date: December 29, 2011
    Inventors: Lars Ivar SAMUELSON, Patrik SVENSSON, Jonas OHLSSON, Truls LOWGREN
  • Publication number: 20110315956
    Abstract: In accordance with certain embodiments, a semiconductor die is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the semiconductor die or non-coplanarity of the semiconductor die contacts.
    Type: Application
    Filed: June 29, 2011
    Publication date: December 29, 2011
    Inventors: Michael Tischler, Philippe Schick, Ian Ashdown, Calvin Wade Sheen, Paul Jungwirth
  • Patent number: 8022389
    Abstract: In accordance with the invention, a light source for display and/or illumination is provided, the light source comprising a heterostructure including semiconductor layers, the heterostructure forming a waveguide between a first end and a second end, the heterostructure comprising a plurality of layers and comprising an optically active zone formed by the plurality of layers, the optically active zone capable of emitting light guided by said waveguide, at least two different radiative transitions being excitable in the optically active an electrical current between a p-side electrode and an n-side electrode, transition energies of said at least two different radiative transitions corresponding to wavelengths in the visible part of the optical spectrum, the light source further comprising means for preventing reflections of light from the waveguide by at least one of said first and second end back into the waveguide, thereby causing the light source to comprise a superluminescent light emitting diode.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: September 20, 2011
    Assignee: Exalos AG
    Inventors: Lorenzo Occhi, Valerio Laino, Christian Velez
  • Publication number: 20110204327
    Abstract: Semiconductor surface emitting elements having a plurality of wavelengths being manufactured on a signal substrate through MOVPE selective growth. More specifically, provided is a semiconductor light emitting element array which comprises; a semiconductor crystal substrate; an insulating film disposed on a surface of the substrate, the insulating film being divided into two or more regions, each of which having two or more openings exposing the surface of the substrate; semiconductor rods extending from the surface of the substrate upward through the openings, the semiconductor rods each having an n-type semiconductor layer and a p-type semiconductor layer being laminated in its extending direction, thereby providing a p-n junction; a first electrode connected to the semiconductor crystal substrate; and a second electrode connected to upper portions of the semiconductor rods; wherein the heights of the semiconductor rods as measured from the substrate surface vary by each of the two or more regions.
    Type: Application
    Filed: October 17, 2008
    Publication date: August 25, 2011
    Applicant: NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY
    Inventors: Kenji Hiruma, Shinjiro Hara, Junichi Motohisa, Takashi Fukui
  • Publication number: 20110204395
    Abstract: Disclosed is a hybrid LED chip: comprising a first clad layer of P-type semiconductor material; a second clad layer of N-type semiconductor material; an active layer between the first and second clad layers; a first bonding metal layer on the first clad layer; a second bonding metal layer on the second clad layer; a ceramic substrate positioned on and bonded to the first and second bonding metal layers, wherein the ceramic substrate includes at least one first via hole to expose the first bonding metal layer, and at least one second via hole to expose the second bonding metal layer; a P-type electrode formed by burying a conductive material in the at least one first via hole; and an N-type electrode formed by burying a conductive material in the at least one second via hole, wherein the first and second via holes in the ceramic substrate are formed in cylindrical shapes, and the circumferential surface of each cylindrical shape is provided with an intaglio pattern.
    Type: Application
    Filed: December 20, 2010
    Publication date: August 25, 2011
    Inventors: Young Gi Hong, Seung Ho Jang, Won Ho Kim
  • Publication number: 20110198634
    Abstract: A semiconductor light-emitting apparatus that has high luminous efficiency and a high breakdown voltage as well as reduced breakdown voltage variation among lots. The semiconductor light-emitting apparatus includes a first clad layer and a second clad layer. An average dopant concentration of the second clad layer is lower than that of the first clad layer. The light-emitting apparatus also includes an active layer having an average dopant concentration of 2×1016 to 4×1016 cm?3. The active layer is made of (AlyGa1-y)xIn1-xP (0<x?1, 0?y?1). The light-emitting apparatus also includes a third clad layer, and a second-conducting-type semiconductor layer made of Ga1-xInxP (0?x<1). If d is the layer thickness of the second clad layer (nm) and Nd1 is the average dopant concentration of the second clad layer (cm?3), then d?1.2×Nd1×10?15+150 is satisfied.
    Type: Application
    Filed: February 14, 2011
    Publication date: August 18, 2011
    Applicant: STANLEY ELECTRIC CO., LTD.
    Inventors: Chiharu SASAKI, Wataru Tamura, Keita Akiyama
  • Publication number: 20110168970
    Abstract: A light emitting structure comprising a hot electron source and a layer of ptoelectronic material disposed thereon and optionally p-type material disposed on the optoelectronic material. For example, a light emitting structure that comprises, in order, a polycrystalline silicon layer, a silicon dioxide layer, a zinc oxide layer and an indium tin oxide (ITO) layer. When a sufficient voltage is applied across the layers, light is generated.
    Type: Application
    Filed: March 5, 2009
    Publication date: July 14, 2011
    Applicant: AUCKLAND UNISERVICES LIMITED
    Inventors: Zoran Salcic, Fei Chen, Wei Gao, Wong C. Cheong, Franck Chollet
  • Publication number: 20110143475
    Abstract: Method for manufacturing of optoelectronic devices based on thin-film, intermediate band materials, characterized in that it comprises, at least, the following steps: a first stage wherein a substrate (1) is coated with a metal layer acting as electrode (2); a second stage, whereby atop the metal layer (2) a p-type semiconductor (3) is deposited; and a third stage, whereby the intermediate band material is processed; and wherein such an intermediate band material comprises nanoscopic structures (4) of multinary material of the type (Cu,Ag)(Al,Ga,In)(S,Se,Te)2 embedded in a matrix (5) of a similar composition, except for the absence of, at least, one cationic species present in the nanostructure.
    Type: Application
    Filed: May 29, 2009
    Publication date: June 16, 2011
    Applicant: UNIVERSIDAD POLITÉCNICA DE MADRID
    Inventors: David Fuertes Marron, Antonio Marti Vega, Antonio Luque Lopez
  • Publication number: 20110133230
    Abstract: Disclosed are a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises a substrate, in which concave-convex patterns are in at least a portion of a backside of the substrate, and a light emitting structure on the substrate and comprising a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 9, 2011
    Applicant: LG INNOTEK CO., INC.
    Inventor: Ho Sang YOON
  • Patent number: 7919784
    Abstract: One embodiment of the present invention provides a semiconductor light-emitting device, which comprises: an upper cladding layer; a lower cladding layer; an active layer between the upper and lower cladding layers; an upper ohmic-contact layer forming a conductive path to the upper cladding layer; and a lower ohmic-contact layer forming a conductive path the lower cladding layer. The lower ohmic-contact layer has a shape substantially different from the shape of the upper ohmic-contact layer, thereby diverting a carrier flow away from a portion of the active layer which is substantially below the upper ohmic-contact layer when a voltage is applied to the upper and lower ohmic-contact layers.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: April 5, 2011
    Assignee: Lattice Power (Jiangxi) Corporation
    Inventors: Fengyi Jiang, Li Wang, Wenqing Fang