Abstract: The present invention provides a light emitting diode including a lower semiconductor layer formed on a substrate; an upper semiconductor layer disposed above the lower semiconductor layer, exposing an edge region of the lower semiconductor layer; a first electrode formed on the upper semiconductor layer; an insulation layer interposed between the first electrode and the upper semiconductor layer, to supply electric current to the lower semiconductor layer; a second electrode formed on another region of the upper semiconductor layer, to supply electric current to the upper semiconductor layer. The first electrode includes an electrode pad disposed on the upper semiconductor layer and an extension extending from the electrode pad to the exposed lower semiconductor layer. The insulation layer may have a distributed Bragg reflector structure.

Abstract: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating resin layer. The light source modules are mounted on the insulating resin layer and are electrically connected to the circuit patterns. The insulating resin layer has a thickness of 200 ?m or less, and is formed by laminating solid film insulating resin on the chassis or by applying liquid insulating resin to the chassis using a molding method employing spin coating or blade coating. Furthermore, the circuit patterns are formed by filling the engraved circuit patterns of the insulating resin layer with metal material.

Abstract: Provided is an organic electroluminescent device including: a substrate (11, 101); a first electrode (12, 102) formed on the substrate (11, 101) and including a pixel region; a partition wall (23, 203) formed on the substrate (11, 101), partitioning the first electrode (12, 102), and including a surface with a recessed and projected form; a luminescent medium layer (19, 109) formed on the pixel region and the partition wall (23, 203), a film thickness of the partition wall (23, 203) being uneven according to the recessed and projected form; and a second electrode (17, 107) formed on the luminescent medium layer (19, 109).

Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.

Abstract: The luminous element includes a luminescence lamination, a second transparent oxidative conducting layer and a composite conducting layer. The composite conducting layer includes first transparent oxidative conducting layer and a metal layer. The second transparent oxidative conducting layer is positioned between the metal layer and luminescence lamination the second transparent oxidative conducting layer forms good ohmic contact with the luminous element and with metal layer. Thus, the metal layer will not be influenced by interfusion so as to maintain good light transmissivity and raise luminous efficiency of luminous element.

Abstract: A nitride light emitting device includes a first conduction type cladding layer, an active layer, and a second conduction type cladding layer that are stacked on a substrate. The second conduction type cladding layer has an uneven shape including at least one concave and/or convex portion.

Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.

Abstract: A lamp unit is provided having polymer electrical conductors adhered to a non-conductive substrate in which adjacent conductors present a gap therebetween for securing a light radiating device within the gap the conductors of one embodiment having raised abutments formed in the conductors at the gap for capture of a light radiating device therebetween, such as an LED in said gap to hold the light device between the abutments to secure the light device in the lamp and power the light device.

Abstract: The lighting device mainly contains a first material, a second material, at a light generation chip, and multiple metallic leads. The metallic leads are sandwiched between the first and second materials, and arranged in a radial manner around the indentation or the raised stand. The center of the first material has an obconical through channel and the center of the second material has either an indentation or a raised stand. The light generation chips are positioned in the center of the second material. High thermal conducting insulation paste is provided between the first material, the metallic leads, and the second material so that they are electrical insulated from each other. The present invention could achieve versatile color combinations and high brightness under superior heat dissipation effect, and could be applied in various types of packaging and welding.

Abstract: The present invention aims at providing a structure in which a high p-type carrier concentration of 1×1017 cm?3 or more is obtained in a material in which, although it shows normally p-type conductivity, a carrier concentration smaller than 1×1017 cm?3 is only obtained. Also, the present invention aims at providing highly reliable semiconductor element and device each of which has excellent characteristics such as light emitting characteristics and a long lifetime. Each specific layer, i.e., each ZnSe0.53Te0.47 layer (2 ML) is inserted between host layers, i.e., Mg0.5Zn0.29Cd0.21Se layers (each having 10 ML (atomic layer) thickness) each of which is lattice matched to an InP substrate. In this case, each specific layer in which a sufficient carrier concentration of 1×1018 cm?3 or more is obtained when a single layer is inserted at suitable intervals.

Abstract: A light source and method for making the same are disclosed. The light source includes a plurality of Segmented LEDs connected in parallel to a power bus and a controller. The power bus accepts a variable number of Segmented LEDs. The controller receives AC power and provides a power signal on the power bus. Each Segmented LED is characterized by a driving voltage that is greater than 3 times the driving voltage of a conventional LED fabricated in the same material system as the Segmented LED. The number of Segmented LEDs in the light source is chosen to compensate for variations in the light output of individual Segmented LEDs introduced by the manufacturing process. In another aspect of the invention, the number of Segmented LEDs connected to the power bus can be altered after the light source is assembled.

Abstract: A light emitting diode comprising a lead, an LED chip mounted on said lead, said LED chip having a substrate and semiconductor layers formed on said substrate, a transparent material covering said LED chip, and a phosphor contained in said transparent material and absorbing a part of light emitted by said LED chip and emitting light of wavelength different from that of the absorbed light, wherein the main emission peak of said LED chip is within the range from 400 nm to 530 nm, and said LED chip is mounted on said lead with substrate-side up and is electrically connected with said lead by a metallic bump.

Abstract: The invention discloses a semiconductor light-emitting device. The semiconductor light-emitting device includes a substrate, a first semiconductor material layer, a light-emitting layer, a second semiconductor material layer, a first transparent insulating layer, a metal layer and at least one electrode. The first semiconductor material layer, the light-emitting layer, and the second semiconductor material layer are formed in sequence on the substrate. An opening is formed on the upper surface of the second semiconductor material layer and extends to the interior of the first semiconductor material layer. The first transparent insulating layer overlays the sidewalls of the opening and substantially overlays the upper surface of the second semiconductor material layer such that a region of the upper surface is exposed. The metal layer fills the opening, overlays the exposed region, and partially overlays the first transparent insulating layer. The at least one electrode is formed on the metal layer.

Abstract: Disclosed is a light-emitting device using a transistor structure, including a substrate, a first gate electrode, a first insulating layer, a source electrode, a drain electrode, and a light-emitting layer formed between the source electrode and the drain electrode in a direction parallel to these electrodes. In the light-emitting device using the transistor structure, it is possible to adjust the mobility of electrons or holes and to selectively set a light-emitting region through the control of the magnitude of voltage applied to the gate electrode, thus increasing the lifespan of the light-emitting device, facilitating the manufacturing process thereof, and realizing light-emitting or light-receiving properties having high efficiency and high purity.

Abstract: A phosphor for light sources, the emission from which lies in the short-wave optical spectral region, as a garnet structure A3B5O12. It is activated with Ce, the second component B representing at least one of the elements Al and Ga, and the first component A is terbium or terbium together with at least one of the elements Y, Gd, La and/or Lu. In a preferred embodiment, a phosphor having a garnet of structure (Tb1?x?yRExCEy)3(Al,Ga)5O12, where RE=Y, Gd, La and/or Lu; 0?x?0.5?y; 0<y<0.1 is used.

Abstract: An object of the present invention is to provide a novel semiconductor mounting system having a semiconductor mounting member, a metal member and a joining layer joining the mounting and metal members, to improve the flatness of a mounting surface and to control the temperature on the surface of a semiconductor. A semiconductor mounting system 12 has a semiconductor mounting member 1, a metal member 7 and a joining layer 27 joining the mounting member 1 and metal member 7. The metal member 1 has a surface mounting a semiconductor. The adhesive sheet 4 has a resin matrix 11 and a filler 10 dispersed in the resin matrix 11.