Abstract: Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays.

Abstract: A sacrificial pattern is formed to partially cover the pipe-shaped electrode. A sacrificial spacer is formed on a lateral surface of the sacrificial pattern. The sacrificial spacer extends across the pipe-shaped electrode. The sacrificial spacer has a first side and a second side opposite the first side. The sacrificial pattern is removed to expose the pipe-shaped electrode proximal to the first and second sides of the sacrificial spacer. The pipe-shaped electrode exposed on both sides of the sacrificial spacer may be primarily trimmed. The pipe-shaped electrode is retained under the sacrificial spacer to form a first portion, and a second portion facing the first portion. The second portion of the pipe-shaped electrode is secondarily trimmed. The sacrificial spacer is removed to expose the first portion of the pipe-shaped electrode. A data storage plug is formed on the first portion of the pipe-shaped electrode.

Abstract: Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays.

Abstract: In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.

Abstract: A phase change memory device includes a switching device and a storage node connected to the switching device. The storage node includes a bottom stack, a phase change layer disposed on the bottom stack and a top stack disposed on the phase change layer. The phase change layer includes a unit for increasing a path of current flowing through the phase change layer and reducing a volume of a phase change memory region. The area of a surface of the unit disposed opposite to the bottom stack is greater than or equal to the area of a surface of the bottom stack in contact with the phase change layer.

Abstract: A nonvolatile, resistively switching memory cell has a layer of a porous dielectric between a first electrode. The dielectric is not a chalcogenide.