Solid-state Devices Adapted For Rectifying, Amplifying, Oscillating, Or Switching Without Potential-jump Barrier Or Surface Barrier, E.g., Dielectric Triodes; Ovshinsky-effect Devices, Processes, Or Apparatus Peculiar To Manufacture Or Treatment Thereof, Or Of Parts Thereof (epo) Patents (Class 257/E45.001)
  • Patent number: 9368750
    Abstract: A method for fabricating an intermediate member of an electronic element, comprises: preparing a glass substrate as a support substrate having a first surface; forming a first inorganic film that contains silicon and has a second surface and a third surface opposite to the second surface, in such a manner that the first surface of the support substrate is in contact with the second surface of the first inorganic film; forming a first polyimide film containing fluorine on the third surface of the first inorganic film; and forming a second inorganic film containing silicon on the first polyimide film.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: June 14, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Yuka Isaji
  • Patent number: 9040960
    Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Xiangdong Chen, Haining S. Yang
  • Patent number: 9035272
    Abstract: A memristor structure has two electrodes sandwiching an insulating region, and includes a nanoparticle providing a conducting path between the two electrodes, wherein either the insulating region comprises an inorganic material and nanoparticle comprises a solid nanoparticle or a core/shell nanoparticle or the insulating region comprises an inorganic or organic material and the nanoparticle comprises a core/shell nanoparticle.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: May 19, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Xia Sheng, Zhang-Lin Zhou, Richard H. Henze
  • Patent number: 9029248
    Abstract: A nano-ionic memory device is provided. The memory device includes a substrate, a chemically inactive lower electrode provided on the substrate, a solid electrolyte layer provided on the lower electrode and including a silver (Ag)-doped telluride (Te)-based nano-material, and an oxidizable upper electrode provided on the electrolyte layer.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: May 12, 2015
    Assignee: EWHA University-Industry Collaboration Foundation
    Inventors: William Jo, Ah-Reum Jeong
  • Patent number: 9012970
    Abstract: A memory array including a plurality of memory cells. In one embodiment, each memory cell is coupled to an electrically conductive gate material. A word line is coupled to the gate material at a contact interface level. A pair of pillars is comprised of an insulating material that extends below the contact interface level. Also, a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, forming a pair of pillars comprised of an insulating material and depositing a gate contact between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level and the insulating material extends below the contact interface level.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Chung H. Lam, Gen P. Lauer
  • Patent number: 9000412
    Abstract: A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: April 7, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Wei-Chih Chien, Feng-Ming Lee, Ming-Hsiu Lee
  • Patent number: 9000409
    Abstract: The present application discloses a 3D semiconductor memory device having 1T1R memory configuration based on a vertical-type gate-around transistor, and a manufacturing method thereof. A on/off current ratio can be well controlled by changing a width and a length of a channel of the gate-around transistor, so as to facilitate multi-state operation of the 1T1R memory cell. Moreover, the vertical transistor has a smaller layout size than a horizontal transistor, so as to reduce the layout size effectively. Thus, the 3D semiconductor memory device can be integrated into an array with a high density.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 7, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zongliang Huo, Ming Liu
  • Patent number: 8999733
    Abstract: An RRAM includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the RRAM is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. When the RRAM is applied with another voltage, the oxygen ions or nitrogen ions are removed from the vacancies to lower the resistance of the resistive layer.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 7, 2015
    Assignee: Nanya Technology Corp.
    Inventors: Chun-I Hsieh, Chang-Rong Wu, Neng-Tai Shih
  • Patent number: 8993374
    Abstract: Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are disclosed herein. One example of forming a memory cell includes forming a first electrode material, forming a phase change material gradient on the first electrode material, and forming a second electrode material on the phase change material gradient.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Davide Erbetta, Luca Fumagalli
  • Patent number: 8981328
    Abstract: A resistive random access memory cell formed in an integrated circuit includes first and second resistive random access memory devices, each including an anode and a cathode. The anode of the second resistive random access memory device is connected to the anode of the first resistive random access memory device. A programming transistor has a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anodes of the first and second resistive random access memory devices, and a gate connected to a program-enable node.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: March 17, 2015
    Assignee: Microsemi SoC Corporation
    Inventors: Jonathan Greene, Frank Hawley, John McCollum
  • Patent number: 8969843
    Abstract: According to one embodiment, a memory device includes first and second conductive layers, a variable resistance portion, and a multiple tunnel junction portion. The variable resistance portion is provided between the first and second conductive layers. The multiple tunnel junction portion is provided between the first conductive layer and the variable resistance portion, and includes first, second, and third tunnel insulating films, and first and second nanocrystal layers. The first nanocrystal layer between the first and second tunnel insulating films includes first conductive minute particles. The second nanocrystal layer between the second and third tunnel insulating films includes second conductive minute particles.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryuji Ohba
  • Patent number: 8969846
    Abstract: A variable resistance memory according to the present embodiment includes a memory cell including an ion source electrode including metal atoms, an opposite electrode, an amorphous silicon film formed between the ion source electrode and the opposite electrode, and a polysilicon film formed between the amorphous silicon film and the ion source electrode.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirohisa Kawasaki
  • Patent number: 8962466
    Abstract: A metal oxide formed by in situ oxidation assisted by radiation induced photo-acid is described. The method includes depositing a photosensitive material over a metal surface of an electrode. Upon exposure to radiation (for example ultraviolet light), a component, such as a photo-acid generator, of the photosensitive material forms an oxidizing reactant, such as a photo acid, which causes oxidation of the metal at the metal surface. As a result of the oxidation, a layer of metal oxide is formed. The photosensitive material can then be removed, and subsequent elements of the component can be formed in contact with the metal oxide layer. The metal oxide can be a transition metal oxide by oxidation of a transition metal. The metal oxide layer can be applied as a memory element in a programmable resistance memory cell. The metal oxide can be an element of a programmable metallization cell.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Feng-Min Lee, Erh-Kun Lai, Wei-Chih Chien, Ming-Hsiu Lee, Chih-Chieh Yu
  • Patent number: 8946672
    Abstract: A resistance changing element according to the present invention comprises a first electrode (101) and a second electrode (103); and an ion conducting layer (102) that is formed between the first electrode (101) and the second electrode (103) and that contains at least oxygen and carbon.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: February 3, 2015
    Assignee: NEC Corporation
    Inventors: Munehiro Tada, Koichiro Okamoto, Toshitsugu Sakamoto, Hiromitsu Hada
  • Patent number: 8921821
    Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: December 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, D. V. Nirmal Ramaswamy, Qian Tao
  • Patent number: 8921819
    Abstract: A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: December 30, 2014
    Assignee: Powerchip Technology Corporation
    Inventors: Chan-Ching Lin, Chen-Hao Huang, Tzung-Bin Huang, Chun-Cheng Chen, Ching-Hua Chen
  • Patent number: 8916949
    Abstract: A resistive memory device and a method for manufacturing the same are provided. The resistive memory device includes a lower electrode, a variable resistive layer formed on the lower electrode and configured so that the volume thereof is contracted or expanded according to temperature, and an upper electrode formed on the variable resistive layer. At least a portion of the lower electrode is configured to be electrically connected to the upper electrode.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyo Seob Yoon, Han Woo Cho
  • Patent number: 8912515
    Abstract: A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: December 16, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8912519
    Abstract: Provided are a variable resistive memory device and a method of fabricating the same. The variable resistive memory device includes an interlayer insulating film having an opening therein, the opening exposing a surface of a first electrode which is disposed at a bottom of the opening. A variable resistive layer is formed in the opening and a second electrode is formed on the variable resistive layer. The variable resistive layer has a sidewall that is separated from an inner side surface of the opening to define a gap between the sidewall of the variable resistive layer and the inner side surface of the opening.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Keun Lee
  • Patent number: 8912524
    Abstract: Embodiments of the present invention generally relate to a resistive switching nonvolatile memory element that is formed in a resistive switching memory device that may be used in a memory array to store digital data. The memory element is generally constructed as a metal-insulator-metal stack. The resistive switching portion of the memory element includes a getter and/or a defect portion. In general, the getter portion is an area of the memory element that is used to help form, during the resistive switching memory device's fabrication process, a region of the resistive switching layer that has a greater number of vacancies or defects compared to the remainder of resistive switching layer. The defect portion is an area of the memory element that has a greater number of vacancies or defects compared to the remainder of the resistive switching layer, and is formed during the resistive switching memory device's fabrication process.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: December 16, 2014
    Assignees: SanDisk 3D LLC, Kabushiki Kaisha Toshiba
    Inventors: Yun Wang, Tony Chiang, Imran Hashim
  • Patent number: 8901527
    Abstract: An RRAM includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the RRAM is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. When the RRAM is applied with another voltage, the oxygen ions or nitrogen ions are removed from the vacancies to lower the resistance of the resistive layer.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: December 2, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Chun-I Hsieh, Chang-Rong Wu, Neng-Tai Shih
  • Patent number: 8895952
    Abstract: A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Kobayashi, Kazuhiko Yamamoto, Kenji Aoyama, Shigeto Oshino, Kei Watanabe, Shinichi Nakao, Satoshi Ishikawa, Takeshi Yamaguchi
  • Patent number: 8895948
    Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and a resistance change film. The resistance change film is connected between the first electrode and the second electrode. An ion metal is introduced in a matrix material in the resistance change film. A concentration of the ion metal in a first region on the first electrode side of the resistance change film is higher than a concentration of the ion metal in a second region on the second electrode side of the resistance change film A layer made of only the ion metal is not provided in the memory device.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yusuke Arayashiki
  • Patent number: 8895953
    Abstract: A programmable memory element can include an insulating layer formed over a bottom structure; an opening formed in the insulating layer; a sidewall structure formed next to side surfaces of the opening; a tapered structure formed within the opening adjacent to the sidewall structure; and a solid electrolyte forming at least a portion of a structure selected from: the bottom structure, the sidewall structure, and the tapered structure.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: November 25, 2014
    Assignee: Adesto Technologies Corporation
    Inventors: Jeffrey Allan Shields, John Ross Jameson, Wei Ti Lee
  • Patent number: 8889521
    Abstract: A method of depositing a silver layer includes forming a plurality of openings in a dielectric layer to expose a top surface of a structure comprising a resistive memory layer on top of a p-doped silicon-containing layer on top of a conductive structure, depositing a first metal layer comprising a tungsten layer overlying the top surface of the structure, wherein a first metal material of the first metal layer contacts a resistive memory material of the resistive memory layer and exposing the first metal layer in a bath comprising a solution of silver species having an alkaline pH for a predetermined time to form a silver metal layer from the silver species from the solution overlying the resistive memory material, wherein the silver species is reduced by the first metal material, and wherein the first metal material is solubilized while forming the silver metal layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 18, 2014
    Assignee: Crossbar, Inc.
    Inventors: Steven Patrick Maxwell, Sung-Hyun Jo
  • Patent number: 8890109
    Abstract: Provided are resistive random access memory (ReRAM) cells including resistive switching layers and thermally isolating structures for limiting heat dissipation from the switching layers during operation. Thermally isolating structures may be positioned within a stack or adjacent to the stack. For example, a stack may include one or two thermally isolating structures. A thermally isolating structure may directly interface with a switching layer or may be separated by, for example, an electrode. Thermally isolating structures may be formed from materials having a thermal conductivity of less than 1 W/m*K, such as porous silica and mesoporous titanium oxide. A thermally isolating structure positioned in series with a switching layer generally has a resistance less than the low resistance state of the switching layer. A thermally isolating structure positioned adjacent to a switching layer may have a resistance greater than the high resistance state of the switching layer.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 18, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8872147
    Abstract: A method for manufacturing a nonvolatile semiconductor storage device according to an embodiment includes laminating a first wire extending in a first direction, and a film made into a variable resistance element made of a metallic material, which are laminated in order on a semiconductor substrate, dividing, into a plurality of pieces, the film made into the variable resistance element, in the first direction and a second direction, forming an interlayer insulating film between the plurality of pieces formed by dividing the film made into the variable resistance element in the second direction, and oxidizing the metallic material of the film made into the variable resistance element, and laminating an upper electrode and a second wire extending in the second direction, which are laminated in order on the film made into the variable resistance element and the interlayer insulating film.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiharu Tanaka
  • Patent number: 8847195
    Abstract: Memory cells and methods of forming the same and devices including the same. The memory cells have first and second electrodes. An amorphous semiconductor material capable of electronic switching and having a first band gap is between the first and second electrodes. A material is in contact with the semiconductor material and having a second band gap, the second band gap greater than the first band gap.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Chandra Mouli, Roy Meade
  • Patent number: 8841649
    Abstract: Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 23, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Federico Pio
  • Patent number: 8841645
    Abstract: Some embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to a memory element. The electrode can include different materials located at different portions of the electrode. The materials can create different dielectrics contacting the memory elements at different locations. Various states of the materials in the memory device can be used to represent stored information. Other embodiments are described.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 23, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Kirk D. Prall
  • Patent number: 8841644
    Abstract: Thermal isolation in memory cells is described herein. A number of embodiments include a storage element, a selector device formed in series with the storage element, and an electrode between the storage element and the selector device, wherein the electrode comprises an electrode material having a thermal conductivity of less than 0.15 Watts per Kelvin-centimeter (W/K-cm).
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: September 23, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Elijah V. Karpov, David L. Kencke
  • Patent number: 8829484
    Abstract: Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: September 9, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Sills
  • Patent number: 8822973
    Abstract: Some embodiments include a memory cell that contains programmable material sandwiched between first and second electrodes. The memory cell can further include a heating element which is directly against one of the electrodes and directly against the programmable material. The heating element can have a thickness in a range of from about 2 nanometers to about 30 nanometers, and can be more electrically resistive than the electrodes. Some embodiments include methods of forming memory cells that include heating elements directly between electrodes and programmable materials.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 2, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8822968
    Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect. And the first memory layer contacts with the first wiring layer, and the first wiring layer is a layer which is capable of supplying a metal ion to the first memory layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideki Inokuma
  • Patent number: 8816313
    Abstract: Provided are a memory element and a memory device. A memory layer is provided with an ion source layer. The ion source layer includes Zr (zirconium), Cu (copper), and Al (aluminum) as a metal element together with an ion conductive material such as S (sulfur), Se (selenium), and Te (tellurium) (chalcogen element). The amount of Al in the ion source layer is 30 to 50 atomic percent. The amount of Zr is preferably 7.5 to 25 atomic percent, and more preferably, the composition ratio of Zr to the chalcogen element in total included in the ion source layer (=Zr (atomic percent)/chalcogen element in total (atomic percent)) falls within a range from 0.2 to 0.74.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: August 26, 2014
    Assignee: Sony Corporation
    Inventors: Kazuhiro Ohba, Tetsuya Mizuguchi, Shuichiro Yasuda
  • Patent number: 8809830
    Abstract: A variable resistance memory according to the present embodiment includes a memory cell including an ion source electrode including metal atoms, an opposite electrode, an amorphous silicon film formed between the ion source electrode and the opposite electrode, and a polysilicon film formed between the amorphous silicon film and the ion source electrode.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirohisa Kawasaki
  • Patent number: 8803122
    Abstract: Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: August 12, 2014
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Shyue Seng (Jason) Tan, Eng Huat Toh
  • Patent number: 8803125
    Abstract: Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ruthenium silicide. A ruthenium silicide interface may be a polycrystalline ruthenium silicide.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Nirmal Ramaswamy, Kirk D. Prall
  • Patent number: 8803121
    Abstract: Resistive memory elements and arrays of resistive memory elements are disclosed. In one embodiment, a resistive memory element includes a top electrode element lying in a plane parallel to a reference plane, and having, in perpendicular projection on the reference plane, a top electrode projection; a bottom electrode element lying in a plane parallel to the reference plane, and having, in perpendicular projection on the reference plane, a bottom electrode projection; and an active layer with changeable resistivity interposed between the top electrode element and the bottom electrode element. The top electrode projection and the bottom electrode projection overlap in an overlapping region that comprises a corner of the top electrode projection and/or a corner of the bottom electrode projection, and an area of the overlapping region constitutes less than 10% of a total projected area of the top electrode element and the bottom electrode element on the reference plane.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: August 12, 2014
    Assignee: IMEC
    Inventor: Ludovic Goux
  • Patent number: 8759808
    Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a first region adjacent to a second region itself adjacent to at least one third region, the first, second, and third regions each extending from the upper electrode to the lower electrode, the crystallization temperature of the second region ranging between that of the first region and that of the third region, and the melting temperatures of the first, second, and third regions being substantially identical.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: June 24, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Jean-Francois Nodin, Veronique Sousa, Sandrine Lhostis
  • Patent number: 8754391
    Abstract: Nonvolatile memory devices including a first interlayer insulating film and a second interlayer insulating film separated from each other and are stacked sequentially, a first electrode penetrating the first interlayer insulating film and the second interlayer insulating film, a resistance change film along a top surface of the first interlayer insulating film, side surfaces of the first electrode, and a bottom surface of the second interlayer insulating film, and a second electrode between the first interlayer insulating film and the second interlayer insulating film.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Jun Seong, Chan-Jin Park
  • Patent number: 8735862
    Abstract: Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, John K. Zahurak
  • Patent number: 8735859
    Abstract: A nonvolatile semiconductor memory device includes: a first interconnect; a second interconnect at a position opposing the first interconnect; and a variable resistance layer between the first interconnect and the second interconnect, the variable resistance layer being capable of reversibly changing between a first state and a second state by a voltage applied via the first interconnect and the second interconnect or a current supplied via the first interconnect and the second interconnect, the first state having a first resistivity, the second state having a second resistivity higher than the first resistivity. Wherein the variable resistance layer has a compound of carbon and silicon as a main component and including hydrogen.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Kuboi, Masayuki Takata, Tsukasa Nakai, Hiroyuki Fukumizu, Yasuhiro Nojiri, Kenichi Ootsuka
  • Patent number: 8722445
    Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a plurality of discrete wires on a substrate. The method further includes forming a sacrificial cavity layer on the discrete wires. The method further includes forming trenches in an upper surface of the sacrificial cavity layer. The method further includes filling the trenches with dielectric material. The method further includes depositing metal on the sacrificial cavity layer and on the dielectric material to form a beam with at least one dielectric bumper extending from a bottom surface thereof.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dinh Dang, Thai Doan, Jeffrey C. Maling, Anthony K. Stamper
  • Patent number: 8723151
    Abstract: A resistive random access memory cell formed in an integrated circuit includes a first resistive random access memory device including an anode and a cathode, a second resistive random access memory device including an anode and a cathode, the cathode of the second resistive random access memory device connected to the anode of the first resistive random access memory device, a programming transistor having a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device, and a gate connected to a program-enable nod, and at least one switch transistor having a gate connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 13, 2014
    Assignee: Microsemi SoC Corporation
    Inventors: Jonathan Greene, Frank W. Hawley, John McCollum
  • Patent number: 8723153
    Abstract: Formulations for voltage switchable dielectric materials include two or more different types of semiconductive materials uniformly dispersed within a dielectric matrix material. The semiconductive materials are selected to have different bandgap energies in order to provide the voltage switchable dielectric material with a stepped voltage response. The semiconductive materials may comprise inorganic particles, organic particles, or an organic material that is soluble in, or miscible with, the dielectric matrix material. Formulations optionally can also include electrically conductive materials. At least one of the conductive or semiconductive materials in a formulation can comprise particles characterized by an aspect ratio of at least 3 or greater.
    Type: Grant
    Filed: April 14, 2012
    Date of Patent: May 13, 2014
    Assignee: Littelfuse, Inc.
    Inventors: Lex Kosowsky, Robert Fleming
  • Patent number: 8716691
    Abstract: According to one embodiment, a nonvolatile memory device includes a lower electrode layer, a nanomaterial assembly layer, and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of micro conductive bodies assembled via a gap. The upper electrode layer is provided on the nanomaterial assembly layer. The portion of the micro conductive bodies is buried at least in a lower part of the upper electrode layer.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: May 6, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeto Oshino
  • Publication number: 20140117301
    Abstract: A device is disclosed. The device includes a top electrode, a bottom electrode and a storage element between the top and bottom electrodes. The storage element includes a heat generating element disposed on the bottom electrode, a phase change element wrapping around an upper portion of the heat generating element, and a dielectric liner sandwiched between the phase change element and the heat generating element.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Khee Yong LIM, Zufa ZHANG
  • Publication number: 20140110658
    Abstract: Some embodiments include memory constructions having a film of phase change material between first and second materials; with the entirety of film having a thickness of less than or equal to about 10 nanometers. The memory constructions are configured to transit from one memory state having a first phase of the phase change material to a second memory state having a second phase of the phase change material, and are configured so that an entirety of the phase change material film changes from the first phase to the second phase in transitioning from the first memory state to the second memory state. In some embodiments, at least one of the first and second materials may be carbon, W, TiN, TaN or TiAlN. In some embodiments, at least one of the first and second materials may be part of a structure having bands of two or more different compositions.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 24, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Andrea Redaelli
  • Publication number: 20140110657
    Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 24, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Andrea Redaelli, Agostino Pirovano