Abstract: Methods for forming a laminate film on substrate by a plasma-enhanced cyclical deposition process are provided. The methods may include: providing a substrate into a reaction chamber, and depositing on substrate a metal oxide laminate film by alternatingly depositing a first metal oxide film and a second metal oxide film different from the first metal oxide film, wherein depositing the first metal oxide film and the second metal oxide film comprises, contacting the substrate with sequential and alternating pulses of a metal precursor and an oxygen reactive species generated by applying RF power to a reactant gas comprising at least nitrous oxide (N2O).

Abstract: A sensor comprises a group of four memristors arranged in an array. Two of the memristors are connected in series as a first pair, and the other two memristors are connected in series as a second pair. The first and second pairs are connected in parallel between two connection points. Each memristor acts as a sensor element because it has an electrical resistance characteristic that is related to exposure to a species to be sensed. In the sensor, the resistance characteristic of the array between the first and second connection points is related to exposure to the species to be sensed. A sensor comprising a larger array can be composed of multiple groups of four memristors.

Abstract: A variable resistance non-volatile memory element includes first and second electrodes and a variable resistance layer between the electrodes. The layer has a resistance value reversibly variable based on an electrical signal. The layer includes a first variable resistance layer that includes an oxygen deficient first metal oxide containing a first metal element and oxygen, and a second variable resistance layer that includes a composite oxide containing the first metal element, a second metal element different from the first metal element, and oxygen, and having a different degree of oxygen deficiency from the first metal oxide. The composite oxide has a lower degree of oxygen deficiency than the first metal oxide. At room temperature, the composite oxide has a smaller oxygen diffusion coefficient than a second metal oxide containing the first metal element and oxygen, and having the degree of oxygen deficiency equal to that of the composite oxide.

Abstract: Disclosed herein are a Gaussian sampling apparatus and method based on resistive RAM. The Gaussian sampling apparatus based on resistive RAM includes Resistive RAM (RRAM) in which a resistive switching layer is disposed between an upper electrode and a lower electrode, and a sampling controller, wherein the sampling controller is configured to perform an operation corresponding to an erase command of applying a reset voltage to the RRAM when a Gaussian error request is received from an outside of the Gaussian sampling apparatus, perform an operation corresponding to a program command of applying a set voltage to the RRAM after the operation corresponding to the erase command has been completed, perform an operation of reading resistance data from the RRAM, and provide a response to the outside of the Gaussian sampling apparatus by transmitting the resistance data of the RRAM as Gaussian error data.

Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.

Abstract: In a semiconductor device, a device structure is positioned over a substrate, where the device structure includes devices. A wiring structure of the semiconductor device is positioned over the substrate and coupled to at least one of the devices. The wiring structure includes at least one of programmable lines and programmable vertical interconnects, where the programmable lines extend along a top surface of the substrate and the programmable vertical interconnects extend along a vertical direction perpendicular to the top surface of the substrate. The programmable lines and the programmable vertical interconnects include a programmable material having a modifiable resistivity in that the programmable lines and the programmable vertical interconnects change between being conductive and being non-conductive in responsive to a current pattern delivered to the programmable lines and the programmable vertical interconnects.

Abstract: A semiconductor structure for a vertical phase change memory cell that includes a bottom electrode on a portion of a semiconductor substrate and a pair of vertical phase change bridge elements that are each on a portion of the bottom electrode. The semiconductor structure for the vertical phase change memory cell includes a dielectric material separating the pair of vertical phase change bridge elements and a top electrode over the pair of vertical phase change bridge elements.

Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

Abstract: An ESD protection diode in a semiconductor device includes: a semiconductor substrate; a diode group that has a plurality of grouped VNW diodes, each of the VNW diodes having a VNW having a lower end and an upper end, that are formed on the semiconductor substrate and have a semiconductor material; and a top plate that is formed above the diode group and is a conductive layer electrically connected to the upper ends of the VNWs of the respective VNW diodes, and there is fabricated the semiconductor device that is capable of, even when large current flows through the VNW diode, suppressing current concentration and preventing damage of the VNW diode.

Abstract: Various embodiments provide methods for configuring a phase-change random-access memory (PCRAM) structures, such as PCRAM operating in a single-level-cell (SLC) mode or a multi-level-cell (MLC) mode. Various embodiments may support a PCRAM structure being operating in a SLC mode for lower power and a MLC mode for lower variability. Various embodiments may support a PCRAM structure being operating in a SLC mode or a MLC mode based at least in part on an error tolerance for a neural network layer.

Abstract: A switching device includes first and second RF terminals disposed over a substrate, one or more strips of phase change material connected between the first and second RF terminals, a region of thermally insulating material that separates the one or more strips of phase change material from the substrate, and a heater structure comprising one or more heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material. Each of the one or more strips of phase change material includes a first outer face and a second outer face opposite from the first outer face. For each of the one or more strips of phase change material, at least portions of both of the first and second outer faces are disposed against one of the heating elements.

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

Abstract: An artificial neuron device according to an embodiment of the present disclosure includes a first resistor connected between an input terminal and a first node; a capacitor connected between the first node and a ground terminal; a threshold switch connected between the first node and a second node; and a second resistor connected between the second node and the ground terminal, wherein, when an input voltage of a certain level is applied to the input terminal by time, a membrane potential occurs at the first node and a spike current flows through the second node. According to present disclosure, the artificial neuron device expresses the Integrate-and-Fire function, the rate coding ability, the SFA characteristics, and the chaotic activity of the biological neuron, and therefore may be widely used for the artificial neuron network device, the large-scale brain-inspired computing system, and the artificial intelligence (AI) system.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

Abstract: Disclosed are a thin film structure and an electronic device including the same. The disclosed thin film structure includes a dielectric material layer between a first material layer and a second material layer. The dielectric material layer includes a dopant in a matrix material having a fluorite structure. The dielectric material layer is uniformly doped with a low concentration of the dopant, and has ferroelectricity.

Abstract: A structure includes a word line, a bit line, and an anti-fuse cell. The anti-fuse cell includes a reading device, a programming device, and a dummy device. The reading device includes a first gate coupled to the first word line, a first source/drain region coupled to the bit line, and a second source/drain region. The first source/drain region and the second source/drain region are on opposite sides of the first gate. The programming device includes a second gate, a third source/drain region coupled to the second source/drain region, and a fourth source/drain region. The third source/drain region and the fourth source/drain region are on opposite sides of the second gate. The dummy device includes a third gate, a fifth source/drain region coupled to the fourth source/drain region, and a sixth source/drain region. The fifth source/drain region and the sixth source/drain region are on opposite sides of the third gate.

Abstract: A vertical resistive switching memory device is provided that includes a resistive random access memory (ReRAM) stack embedded in a material stack of alternating layers of an interlayer dielectric material and a recessed electrode material. A selector device encapsulates a portion of the ReRAM stack and is present in an undercut region that is laterally adjacent to each of the recessed electrode material layers of the material stack.

Abstract: A method for fabricating an intermediate member of an electronic element, comprises: preparing a glass substrate as a support substrate having a first surface; forming a first inorganic film that contains silicon and has a second surface and a third surface opposite to the second surface, in such a manner that the first surface of the support substrate is in contact with the second surface of the first inorganic film; forming a first polyimide film containing fluorine on the third surface of the first inorganic film; and forming a second inorganic film containing silicon on the first polyimide film.

Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

Abstract: A memristor structure has two electrodes sandwiching an insulating region, and includes a nanoparticle providing a conducting path between the two electrodes, wherein either the insulating region comprises an inorganic material and nanoparticle comprises a solid nanoparticle or a core/shell nanoparticle or the insulating region comprises an inorganic or organic material and the nanoparticle comprises a core/shell nanoparticle.

Abstract: A nano-ionic memory device is provided. The memory device includes a substrate, a chemically inactive lower electrode provided on the substrate, a solid electrolyte layer provided on the lower electrode and including a silver (Ag)-doped telluride (Te)-based nano-material, and an oxidizable upper electrode provided on the electrolyte layer.

Abstract: A memory array including a plurality of memory cells. In one embodiment, each memory cell is coupled to an electrically conductive gate material. A word line is coupled to the gate material at a contact interface level. A pair of pillars is comprised of an insulating material that extends below the contact interface level. Also, a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, forming a pair of pillars comprised of an insulating material and depositing a gate contact between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level and the insulating material extends below the contact interface level.

Abstract: The present application discloses a 3D semiconductor memory device having 1T1R memory configuration based on a vertical-type gate-around transistor, and a manufacturing method thereof. A on/off current ratio can be well controlled by changing a width and a length of a channel of the gate-around transistor, so as to facilitate multi-state operation of the 1T1R memory cell. Moreover, the vertical transistor has a smaller layout size than a horizontal transistor, so as to reduce the layout size effectively. Thus, the 3D semiconductor memory device can be integrated into an array with a high density.

Abstract: A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte.

Abstract: An RRAM includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the RRAM is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. When the RRAM is applied with another voltage, the oxygen ions or nitrogen ions are removed from the vacancies to lower the resistance of the resistive layer.

Abstract: Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are disclosed herein. One example of forming a memory cell includes forming a first electrode material, forming a phase change material gradient on the first electrode material, and forming a second electrode material on the phase change material gradient.

Abstract: A resistive random access memory cell formed in an integrated circuit includes first and second resistive random access memory devices, each including an anode and a cathode. The anode of the second resistive random access memory device is connected to the anode of the first resistive random access memory device. A programming transistor has a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anodes of the first and second resistive random access memory devices, and a gate connected to a program-enable node.

Abstract: According to one embodiment, a memory device includes first and second conductive layers, a variable resistance portion, and a multiple tunnel junction portion. The variable resistance portion is provided between the first and second conductive layers. The multiple tunnel junction portion is provided between the first conductive layer and the variable resistance portion, and includes first, second, and third tunnel insulating films, and first and second nanocrystal layers. The first nanocrystal layer between the first and second tunnel insulating films includes first conductive minute particles. The second nanocrystal layer between the second and third tunnel insulating films includes second conductive minute particles.

Abstract: A variable resistance memory according to the present embodiment includes a memory cell including an ion source electrode including metal atoms, an opposite electrode, an amorphous silicon film formed between the ion source electrode and the opposite electrode, and a polysilicon film formed between the amorphous silicon film and the ion source electrode.

Abstract: A metal oxide formed by in situ oxidation assisted by radiation induced photo-acid is described. The method includes depositing a photosensitive material over a metal surface of an electrode. Upon exposure to radiation (for example ultraviolet light), a component, such as a photo-acid generator, of the photosensitive material forms an oxidizing reactant, such as a photo acid, which causes oxidation of the metal at the metal surface. As a result of the oxidation, a layer of metal oxide is formed. The photosensitive material can then be removed, and subsequent elements of the component can be formed in contact with the metal oxide layer. The metal oxide can be a transition metal oxide by oxidation of a transition metal. The metal oxide layer can be applied as a memory element in a programmable resistance memory cell. The metal oxide can be an element of a programmable metallization cell.

Abstract: A resistance changing element according to the present invention comprises a first electrode (101) and a second electrode (103); and an ion conducting layer (102) that is formed between the first electrode (101) and the second electrode (103) and that contains at least oxygen and carbon.

Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.

Abstract: A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line.

Abstract: A resistive memory device and a method for manufacturing the same are provided. The resistive memory device includes a lower electrode, a variable resistive layer formed on the lower electrode and configured so that the volume thereof is contracted or expanded according to temperature, and an upper electrode formed on the variable resistive layer. At least a portion of the lower electrode is configured to be electrically connected to the upper electrode.

Abstract: Provided are a variable resistive memory device and a method of fabricating the same. The variable resistive memory device includes an interlayer insulating film having an opening therein, the opening exposing a surface of a first electrode which is disposed at a bottom of the opening. A variable resistive layer is formed in the opening and a second electrode is formed on the variable resistive layer. The variable resistive layer has a sidewall that is separated from an inner side surface of the opening to define a gap between the sidewall of the variable resistive layer and the inner side surface of the opening.

Abstract: Embodiments of the present invention generally relate to a resistive switching nonvolatile memory element that is formed in a resistive switching memory device that may be used in a memory array to store digital data. The memory element is generally constructed as a metal-insulator-metal stack. The resistive switching portion of the memory element includes a getter and/or a defect portion. In general, the getter portion is an area of the memory element that is used to help form, during the resistive switching memory device's fabrication process, a region of the resistive switching layer that has a greater number of vacancies or defects compared to the remainder of resistive switching layer. The defect portion is an area of the memory element that has a greater number of vacancies or defects compared to the remainder of the resistive switching layer, and is formed during the resistive switching memory device's fabrication process.

Abstract: A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described.

Abstract: An RRAM includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the RRAM is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. When the RRAM is applied with another voltage, the oxygen ions or nitrogen ions are removed from the vacancies to lower the resistance of the resistive layer.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and a resistance change film. The resistance change film is connected between the first electrode and the second electrode. An ion metal is introduced in a matrix material in the resistance change film. A concentration of the ion metal in a first region on the first electrode side of the resistance change film is higher than a concentration of the ion metal in a second region on the second electrode side of the resistance change film A layer made of only the ion metal is not provided in the memory device.

Abstract: A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.

Abstract: A programmable memory element can include an insulating layer formed over a bottom structure; an opening formed in the insulating layer; a sidewall structure formed next to side surfaces of the opening; a tapered structure formed within the opening adjacent to the sidewall structure; and a solid electrolyte forming at least a portion of a structure selected from: the bottom structure, the sidewall structure, and the tapered structure.

Abstract: A method of depositing a silver layer includes forming a plurality of openings in a dielectric layer to expose a top surface of a structure comprising a resistive memory layer on top of a p-doped silicon-containing layer on top of a conductive structure, depositing a first metal layer comprising a tungsten layer overlying the top surface of the structure, wherein a first metal material of the first metal layer contacts a resistive memory material of the resistive memory layer and exposing the first metal layer in a bath comprising a solution of silver species having an alkaline pH for a predetermined time to form a silver metal layer from the silver species from the solution overlying the resistive memory material, wherein the silver species is reduced by the first metal material, and wherein the first metal material is solubilized while forming the silver metal layer.

Abstract: Provided are resistive random access memory (ReRAM) cells including resistive switching layers and thermally isolating structures for limiting heat dissipation from the switching layers during operation. Thermally isolating structures may be positioned within a stack or adjacent to the stack. For example, a stack may include one or two thermally isolating structures. A thermally isolating structure may directly interface with a switching layer or may be separated by, for example, an electrode. Thermally isolating structures may be formed from materials having a thermal conductivity of less than 1 W/m*K, such as porous silica and mesoporous titanium oxide. A thermally isolating structure positioned in series with a switching layer generally has a resistance less than the low resistance state of the switching layer. A thermally isolating structure positioned adjacent to a switching layer may have a resistance greater than the high resistance state of the switching layer.

Abstract: A method for manufacturing a nonvolatile semiconductor storage device according to an embodiment includes laminating a first wire extending in a first direction, and a film made into a variable resistance element made of a metallic material, which are laminated in order on a semiconductor substrate, dividing, into a plurality of pieces, the film made into the variable resistance element, in the first direction and a second direction, forming an interlayer insulating film between the plurality of pieces formed by dividing the film made into the variable resistance element in the second direction, and oxidizing the metallic material of the film made into the variable resistance element, and laminating an upper electrode and a second wire extending in the second direction, which are laminated in order on the film made into the variable resistance element and the interlayer insulating film.

Abstract: Memory cells and methods of forming the same and devices including the same. The memory cells have first and second electrodes. An amorphous semiconductor material capable of electronic switching and having a first band gap is between the first and second electrodes. A material is in contact with the semiconductor material and having a second band gap, the second band gap greater than the first band gap.

Abstract: Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.

Abstract: Some embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to a memory element. The electrode can include different materials located at different portions of the electrode. The materials can create different dielectrics contacting the memory elements at different locations. Various states of the materials in the memory device can be used to represent stored information. Other embodiments are described.

Abstract: Thermal isolation in memory cells is described herein. A number of embodiments include a storage element, a selector device formed in series with the storage element, and an electrode between the storage element and the selector device, wherein the electrode comprises an electrode material having a thermal conductivity of less than 0.15 Watts per Kelvin-centimeter (W/K-cm).

Abstract: Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays.