Abstract: Operating a selector device that controls access of a signal to a memory element may comprise applying a main operating voltage pulse and a refresh voltage pulse to the selector device. The refresh voltage pulse and main operating voltage pulse have opposite polarities. A magnitude of the main operating voltage pulse is greater than or equal to a threshold voltage for turning on the selector device, and a maximum magnitude of the refresh voltage pulse is less than the threshold voltage. The refresh voltage pulse reduces a difference between the threshold voltage and a turn-off voltage of the selector device, and may be applied immediately before or immediately after the main operating voltage pulse. An electronic circuit may include the selector device and a driving circuit for apply the pulses. A nonvolatile memory may include the driving circuit and a plurality of nonvolatile memory elements each including a selector device.

Abstract: A superlattice phase-change thin film with a low density change, a phase-change memory and a preparation method. The superlattice phase-change thin film includes first phase-change layers (7) and second phase-change layers (8) that are alternately stacked to form a periodic structure; during crystallization, the first phase-change layer (7) has a conventional positive density change, and the second phase-change layer (8) has an abnormal negative density change, therefore, the abnormal density reduction and volume increase of the second phase-change layer (8) during crystallization can be used to offset the volume reduction of the first phase-change layer (7) during crystallization.

Abstract: A memory device includes a memory material portion, and an ovonic threshold switch selector element. The ovonic threshold switch selector element includes a first carbon-containing electrode comprising carbon and a metal, a second carbon-containing electrode comprising the carbon and the metal, and an ovonic threshold switch material portion located between the first electrode and the second electrode.

Abstract: A ring-shaped heater, system, and method to gradually change the conductance of the phase change memory through a concentric ring-shaped heater. The system may include a phase change memory. The phase change memory may include a bottom electrode. The phase change memory may also include a ring-shaped heater patterned on top of the bottom electrode, the ring-shaped heater including: a plurality of concentric conductive heating layers, and a plurality of insulator spacers, where each insulator spacer separates each conductive heating layer. The phase change memory may also include a phase change material proximately connected to the ring-shaped heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

Abstract: A process integration and patterning flow used to pattern a memory array area for an embedded memory without perturbing a fabricating process for logic circuitries. The fabrication process uses a pocket mask (e.g., a hard mask) to decouple the etching process of a memory array area and non-memory area. Such decoupling allows for a simpler fabrication process with little to no impact on the current fabrication process. The fabrication process may use multiple pocket masks to decouple the etching process of the memory array area and the non-memory area. This fabrication process (using multiple pocket masks) allows to avoid exposure of memory material into a second pocket etch chamber. The process of etching memory material is decoupled from the process of etching an encapsulation material. Examples of embedded memory include dynamic random-access memory and ferroelectric random-access memory.

Abstract: A memory device includes a first electrode, a second electrode, and a magnetic tunnel junction located between the first electrode and the second electrode. The magnetic tunnel junction includes a reference layer, a free layer, a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, and a platinum-containing layer containing platinum and at least one element selected from iridium, hafnium or ruthenium. The platinum-containing layer contacts the free layer.

Abstract: A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.

Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

Abstract: An optoelectronic synaptic memristor includes: a bottom electrode layer, a porous structure layer modified with quantum dots, a two-dimensional material layer, a transparent top electrode layer, and a waveguide layer, which are arranged in sequence from top to bottom, wherein the waveguide is ridge shaped for light conduction, comprising a wedge-shaped output terminal, wherein: through the wedge-shaped output terminal of the waveguide, light is vertically injected into the two-dimensional material layer and the porous structure layer modified with the quantum dots. By integrating the waveguide and the optoelectronic memristor, the present invention obtains the highly controlled characteristics with high alignment and confinement for light effect on the device and has advantages in realizing optoelectronic synergy in the optoelectronic synaptic memristors.

Abstract: An approach for minimizing stack height and reducing resistance of an MRAM (Magnetoresistive random-access memory) is disclosed. The approach leverages an MRAM device with a T shape magnetic bottom electrode. The T shape magnetic bottom electrode can be made from a lower resistance metal such as cobalt. Furthermore, the method of creating the MRAM can include, depositing a low-k dielectric layer, forming bottom electrode via within the low-k dielectric layer, depositing bottom electrode metal liner on the bottom electrode via, depositing bottom electrode magnetic metal on the bottom electrode metal liner, planarizing the bottom electrode magnetic metal, depositing coupling layer and an MRAM stack on the bottom electrode magnetic metal, patterning and etching anisotropically the MRAM stack and depositing in-situ conformal dielectric layer and forming a top contact via on the MRAM stack.

Abstract: A non-volatile multi-bit storage device that includes a phase change material doped with n-type or p-type semiconductor impurities, a first set of electrodes ohmically coupled to the phase change material, a second set of electrodes configured to apply an electric field across the phase change material. To program the non-volatile multi-bit storage device, an electrical field is applied to the phase change material as crystal annealing cool down is performed. Application of the electric field during the crystal annealing cool down forms a rectified current path through the phase change material.

Abstract: A semiconductor structure includes a first electrode; a second electrode; a dielectric material between the first electrode and the second electrode, the dielectric material having at least one wall extending from the first electrode to the second electrode to define a void within the dielectric material and between the first electrode and the second electrode; and a layer of phase change material on the at least one wall of the dielectric material and in contact with the first electrode and the second electrode.

Abstract: A sputtering target and a method for fabricating an electronic device using the same are provided. A sputtering target may include a carbon-doped GeSbTe alloy, wherein, for the carbon-doped GeSbTe alloy, an average grain diameter of a GeSbTe alloy after sintering is in a range of 0.5 ?m to 5 ?m, and a first ratio of an average grain diameter of carbon after the sintering is Y (?m) to the average grain diameter of the GeSbTe alloy after the sintering may be in a range of greater than 0.5 and equal to or less than 1.5. Alternatively, for the carbon-doped GeSbTe alloy, a condition of Y=X×(Z/100) may be satisfied, where an average grain diameter of a GeSbTe alloy after sintering is X (?m), an average grain diameter of carbon after the sintering is Y (?m), and a content of carbon is Z (at %).

Abstract: A method for mitigating moisture driven degradation of silicon doped chalcogenides includes placing a silicon doped chalcogenide composition in a process chamber, passivating dangling silicon bonds of the silicon doped chalcogenide composition by flooding the process chamber with forming gas or with hydrogen plasma, purging the forming gas or the hydrogen plasma from the process chamber, and removing the passivated silicon doped chalcogenide composition from the process chamber.

Abstract: In an embodiment, a phase change switch device is provided. The phase change switch includes a phase change material, a set of heaters arranged to heat the phase change material and a power source. A switch arrangement including a plurality of switches is provided, which is configured to selectively provide electrical power from the power source to the set of the heaters.

Abstract: A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MxSiOy, where “M” is at least one of Ru, Ti, Ta, Co, Pt, Ir, Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sig, and Nb, Other aspects, including method, are disclosed.

Abstract: A memory device, transistor, and methods of making the same, the memory device including a memory cell including: a bottom electrode layer; a high-k dielectric layer disposed on the bottom electrode layer; a discontinuous seed structure comprising discrete particles of a metal disposed on the high-k dielectric layer; a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure; and a top electrode layer disposed on the FE layer.

Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.

Abstract: Provided are a metal chalcogenide thin film and a method and device for manufacturing the same. The metal chalcogenide thin film includes a transition metal element and a chalcogen element, and at least one of the transition metal element and the chalcogen element having a composition gradient along the surface of the metal chalcogenide thin film, the composition gradient being an in-plane composition gradient. The metal chalcogenide thin film may be prepared by using a manufacturing method including providing a transition metal precursor and a chalcogen precursor on a substrate by using a confined reaction space in such a manner that at least one of the transition metal precursor and the chalcogen precursor forms a concentration gradient according to a position on the surface of the substrate; and heat-treating the substrate.

Abstract: A semiconductor memory device includes a first electrode and a second electrode, a phase change layer disposed between the first electrode and the second electrode, and a first layer disposed between the first electrode and the phase change layer. The phase change layer contains at least one of germanium (Ge), antimony (Sb), and tellurium (Te). The first layer contains aluminum (Al) and antimony (Sb), or tellurium (Te) and at least one of zinc (Zn), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

Abstract: A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements.

Abstract: A method of fabricating a variable resistance memory device includes: forming a bottom electrode on a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first trench that exposes the bottom electrode; forming a variable resistance layer in the first trench; and irradiating the variable resistance layer with a laser, wherein the variable resistance layer is irradiated by the laser for a time of about 1.8 ?s to about 54 ?s.

Abstract: An ovonic threshold switch comprises a thin film composed essentially of Si, Ge, Se, As, and an amount of a chalcogen that is effective to passivate oxidation of the composition in the presence of water vapor, wherein the chalcogen is selected from the list consisting of: Te and S. In one or more embodiments, the chalcogen is S. In one or more embodiments, the chalcogen is Te. In one or more embodiments, the effective amount of the chalcogen is greater than 1% by atomic percent. In one or more embodiments, the effective amount of the chalcogen is less than 10% by atomic percent. In one or more embodiments, the composition of matter comprises 10% Si, 15% Ge, 40% Se, 30% As, and 5% chalcogen by atomic percent.

Abstract: A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.

Abstract: The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

Abstract: An optically activated device that includes an active material on a substrate with two electrodes electrically connected to the active material, the active material conducts current in the presence of light and does not conduct appreciable current in the absence of light. The optically activated device functions as a photodiode, a switch, and an optically gated transistor. The optically activated device conducts current in the presences of light. The active material may be layers of germanium selenide and germanium selenide and an element. Germanium selenide may be sputtered onto a substrate to create layers of material separated by layers of co-sputtered germanium selenide with the element. The active material may be deposited onto a flexible substrate.

Abstract: An alloy of GexSbySezTem includes atoms of Ge, Sb, Se, and Te that form a crystalline structure having a plurality of vacancies randomly distributed in the crystalline structure. The alloy can be used to construct an optical device including a first waveguide to guide a light beam and a modulation layer disposed on the first waveguide. The modulation includes the alloy of GexSbySezTem which has a first refractive index n1 in an amorphous state and a second refractive index n2, greater than the first refractive index by at least 1, in a crystalline state. The first waveguide and the modulation layer are configured to guide about 1% to about 50% of the light beam in the modulation layer when the alloy is in the amorphous state and guide no optical mode when the alloy is in the crystalline state.

Abstract: A semiconductor structure includes stack structures. Each of the stack structures comprises a first conductive material, a chalcogenide material over the first conductive material, a second conductive material over the chalcogenide material, and a first dielectric material between the chalcogenide material and the first conductive material and between the chalcogenide material and the second conductive material. The semiconductor structure further comprises a second dielectric material on at least sidewalls of the chalcogenide material. The chalcogenide material may be substantially encapsulated by one or more dielectric materials. Related semiconductor structures and related methods are disclosed.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bottom electrode having a first width and a dielectric structure having a second width formed over the bottom electrode. The semiconductor structure further includes a top electrode having a third width formed over the dielectric structure. In addition, the second width of the dielectric structure is greater than the first width of the bottom electrode.

Abstract: A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.

Abstract: Systems and methods for providing a one-time programmable chalcogenide-based memory with improved memory cell IV characteristics are described. The memory cells of the one-time programmable chalcogenide-based memory may include a chalcogenide-based material. The chalcogenide-based material may comprise a germanium-antimony-tellurium compound (GST), a chalcogenide glass, or a chalcogenide alloy such as Ge10Se54As36 or Ge17Te50As33. The chalcogenide-based memory may be written as a one-time programmable memory in which forming operations are performed on only memory cells that are to be programmed to store a first binary value (e.g., binary “1” data values) and not performed on other memory cells that are to store a second binary value different from the first binary value (e.g., binary “0” data values).

Abstract: The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

Abstract: Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract: A storage element includes a first electrode and a second electrode separated by a gap and a dielectric layer provided between the first electrode and the second electrode to fill the gap. A separation distance of the gap changes in response to application of a voltage to a space between the first electrode and the second electrode, such that a switching phenomenon is produced which switches a resistance state between the first electrode and the second electrode between a high resistance state in which it is difficult for tunnel current to flow and a low resistance state in which it is easy for tunnel current to flow.

Abstract: An electrically actuated device comprises an active region disposed between a first electrode and a second electrode, a substantially nonrandom distribution of dopant initiators at an interface between the active region and the first electrode, and a substantially nonrandom distribution of dopants in a portion of the active region adjacent to the interface.

Abstract: According to one embodiment, an information recording device includes first and second electrodes, a variable resistance layer between the first and second electrodes, and a control circuit which controls the variable resistance layer to n (n is a natural number except 1) kinds of resistance. The variable resistance layer comprises a material filled between the first and second electrodes, and particles arranged in a first direction from the first electrode to the second electrode in the material, and each of the particles has a resistance lower than that of the material. A resistance of the variable resistance layer is decided by a short between the first electrode and at least one of the particles.

Abstract: Erosion of chalcogenides in phase change memories using ovonic threshold switch selectors can be reduced by controlling columnar morphology in electrodes used in the ovonic threshold switch. The columnar morphology may cause cracks to occur which allow etchants used to etch the ovonic threshold switch to sneak through the ovonic threshold switch and to attack chalcogenides, either in the switch or in the memory element. In one embodiment, the electrode may be split into two metal nitride layers separated by an intervening metal layer.

Abstract: A memory cell includes a first resistive switching device having a first terminal and a second terminal, a switching device having a first terminal and a second terminal, and an access device having a first access terminal and a second access terminal. The first access terminal is coupled to the first terminal of the first resistive switching device and the first terminal of the switching device.

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract: A method is provided for fabricating a phase change memory. The method includes providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices, and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a loop-shape electrode in the first dielectric layer, and forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode. Further, the method includes forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact, and forming a top electrode.

Abstract: A phase-change memory device and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate in which a word line is arranged, a diode line disposed over the word line and extending parallel to the word line, a phase-change line pattern disposed over the diode line, and a projection disposed between the diode line and the phase-change line pattern and protruding from the diode line. The diode line and the projection are formed of a single layer to be in continuity with each other.

Abstract: An electronic device includes a first electrode and a second electrode. The device also includes a resistive material between the first and second electrodes. An active material is between the first electrode and the resistive material. The active material is in electrical communication with the first electrode and the active material is in electrical communication with the second electrode through the resistive layer.

Abstract: Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are disclosed herein. One example of forming a memory cell includes forming a first electrode material, forming a phase change material gradient on the first electrode material, and forming a second electrode material on the phase change material gradient.

Abstract: A memory device includes a plurality of side-wall electrodes formed on a first side-wall of a trench within an insulating layer over a first plurality of contacts in an array of contacts in a substrate. The plurality of side-wall electrodes contact respective top surfaces of the first plurality of contacts. The side-wall electrodes respectively comprise a layer of tantalum nitride, having a composition TaxNy, where y is greater than x, and a layer of electrode material having a lower electrical resistivity and a lower thermal resistivity than the layer of tantalum nitride. Top surfaces of the plurality of side-wall electrodes contact memory material. A second plurality of side-wall electrodes may be formed on a second side-wall of the trench over a second plurality of contacts in the array of contacts.

Abstract: A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin film 4 contains any one of elements selected from Cu, Ag, Zn and the memory thin film 4 or the layer 3 in contact with the memory thin film 4 contains any one of elements selected from Te, S, Se. The memory device can record and read information with ease stably, and this memory device can be manufactured easily by a relatively simple manufacturing method.

Abstract: In some embodiments, a memory cell is provided that includes a metal-insulator-metal stack and a steering element coupled to the metal-insulator-metal stack. The metal-insulator-metal stack includes a first conductive layer, a reversible resistivity switching layer above the first conductive layer, and a second conductive layer above the reversible resistivity switching layer. The first conductive layer and/or the second conductive layer includes a first semiconductor material layer. The steering element includes the first semiconductor material layer. Numerous other aspects are provided.

Abstract: A resistive random access memory cell formed in an integrated circuit includes first and second resistive random access memory devices, each including an anode and a cathode. The anode of the second resistive random access memory device is connected to the anode of the first resistive random access memory device. A programming transistor has a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anodes of the first and second resistive random access memory devices, and a gate connected to a program-enable node.