Bistable Switching Devices, E.g., Ovshinsky-effect Devices (epo) Patents (Class 257/E45.002)
  • Patent number: 10374103
    Abstract: A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Fabio Carta, Chung H. Lam, Matthew J. BrightSky, Bahman Hekmatshoartabari
  • Patent number: 10290348
    Abstract: Systems and methods for providing a one-time programmable chalcogenide-based memory with improved memory cell IV characteristics are described. The memory cells of the one-time programmable chalcogenide-based memory may include a chalcogenide-based material. The chalcogenide-based material may comprise a germanium-antimony-tellurium compound (GST), a chalcogenide glass, or a chalcogenide alloy such as Ge10Se54As36 or Ge17Te50As33. The chalcogenide-based memory may be written as a one-time programmable memory in which forming operations are performed on only memory cells that are to be programmed to store a first binary value (e.g., binary “1” data values) and not performed on other memory cells that are to store a second binary value different from the first binary value (e.g., binary “0” data values).
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: May 14, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Federico Nardi
  • Patent number: 10103325
    Abstract: The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: October 16, 2018
    Assignee: Winbond Electronics Corp.
    Inventor: Frederick Chen
  • Patent number: 10008664
    Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 9397292
    Abstract: Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: July 19, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Pragati Kumar, Sean Barstow, Tony P. Chiang, Sunil Shanker
  • Patent number: 9287285
    Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: March 15, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Fang-Hao Hsu, Zusing Yang, Hong-Ji Lee
  • Patent number: 9236569
    Abstract: A storage element includes a first electrode and a second electrode separated by a gap and a dielectric layer provided between the first electrode and the second electrode to fill the gap. A separation distance of the gap changes in response to application of a voltage to a space between the first electrode and the second electrode, such that a switching phenomenon is produced which switches a resistance state between the first electrode and the second electrode between a high resistance state in which it is difficult for tunnel current to flow and a low resistance state in which it is easy for tunnel current to flow.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: January 12, 2016
    Assignee: Funai Electric Co., Ltd.
    Inventors: Shigeo Furuta, Yuichiro Masuda, Tsuyoshi Takahashi, Masatoshi Ono, Yutaka Hayashi, Taro Itaya, Yasuhisa Naitoh, Tetsuo Shimizu
  • Patent number: 9040949
    Abstract: According to one embodiment, an information recording device includes first and second electrodes, a variable resistance layer between the first and second electrodes, and a control circuit which controls the variable resistance layer to n (n is a natural number except 1) kinds of resistance. The variable resistance layer comprises a material filled between the first and second electrodes, and particles arranged in a first direction from the first electrode to the second electrode in the material, and each of the particles has a resistance lower than that of the material. A resistance of the variable resistance layer is decided by a short between the first electrode and at least one of the particles.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichiro Mitani, Daisuke Matsushita, Shosuke Fujii
  • Patent number: 9041157
    Abstract: An electrically actuated device comprises an active region disposed between a first electrode and a second electrode, a substantially nonrandom distribution of dopant initiators at an interface between the active region and the first electrode, and a substantially nonrandom distribution of dopants in a portion of the active region adjacent to the interface.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: May 26, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Wu, Sagi Varghese Mathai, Shih-Yuan (SY) Wang, Jianhua Yang
  • Patent number: 9029829
    Abstract: A memory cell includes a first resistive switching device having a first terminal and a second terminal, a switching device having a first terminal and a second terminal, and an access device having a first access terminal and a second access terminal. The first access terminal is coupled to the first terminal of the first resistive switching device and the first terminal of the switching device.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: May 12, 2015
    Assignee: Adesto Technologies Corporation
    Inventors: Juan Pablo Saenz Echeverry, Deepak Kamalanathan
  • Patent number: 9029826
    Abstract: Erosion of chalcogenides in phase change memories using ovonic threshold switch selectors can be reduced by controlling columnar morphology in electrodes used in the ovonic threshold switch. The columnar morphology may cause cracks to occur which allow etchants used to etch the ovonic threshold switch to sneak through the ovonic threshold switch and to attack chalcogenides, either in the switch or in the memory element. In one embodiment, the electrode may be split into two metal nitride layers separated by an intervening metal layer.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: May 12, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Wei Chang, Jinwook Lee, Jong-Won Lee, Elijah V. Karpov
  • Patent number: 9012282
    Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: April 21, 2015
    Assignee: Macronix International Co., Inc.
    Inventors: Fang-Hao Hsu, Zusing Yang, Hong-Ji Lee
  • Patent number: 9006022
    Abstract: A method is provided for fabricating a phase change memory. The method includes providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices, and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a loop-shape electrode in the first dielectric layer, and forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode. Further, the method includes forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact, and forming a top electrode.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Ying Li, Neil Zhu, Guanping Wu
  • Patent number: 9000408
    Abstract: An electronic device includes a first electrode and a second electrode. The device also includes a resistive material between the first and second electrodes. An active material is between the first electrode and the resistive material. The active material is in electrical communication with the first electrode and the active material is in electrical communication with the second electrode through the resistive layer.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: April 7, 2015
    Assignee: Ovonyx, Inc.
    Inventors: Sergey Kostylev, Tyler Lowrey, Wolodymyr Czubatyj
  • Patent number: 8999745
    Abstract: A phase-change memory device and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate in which a word line is arranged, a diode line disposed over the word line and extending parallel to the word line, a phase-change line pattern disposed over the diode line, and a projection disposed between the diode line and the phase-change line pattern and protruding from the diode line. The diode line and the projection are formed of a single layer to be in continuity with each other.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventor: Il Yong Lee
  • Patent number: 8993374
    Abstract: Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are disclosed herein. One example of forming a memory cell includes forming a first electrode material, forming a phase change material gradient on the first electrode material, and forming a second electrode material on the phase change material gradient.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Davide Erbetta, Luca Fumagalli
  • Patent number: 8987700
    Abstract: A memory device includes a plurality of side-wall electrodes formed on a first side-wall of a trench within an insulating layer over a first plurality of contacts in an array of contacts in a substrate. The plurality of side-wall electrodes contact respective top surfaces of the first plurality of contacts. The side-wall electrodes respectively comprise a layer of tantalum nitride, having a composition TaxNy, where y is greater than x, and a layer of electrode material having a lower electrical resistivity and a lower thermal resistivity than the layer of tantalum nitride. Top surfaces of the plurality of side-wall electrodes contact memory material. A second plurality of side-wall electrodes may be formed on a second side-wall of the trench over a second plurality of contacts in the array of contacts.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: March 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Sheng-Chih Lai, Hsiang-Lan Lung, Matthew J. Breitwisch
  • Patent number: 8981328
    Abstract: A resistive random access memory cell formed in an integrated circuit includes first and second resistive random access memory devices, each including an anode and a cathode. The anode of the second resistive random access memory device is connected to the anode of the first resistive random access memory device. A programming transistor has a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anodes of the first and second resistive random access memory devices, and a gate connected to a program-enable node.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: March 17, 2015
    Assignee: Microsemi SoC Corporation
    Inventors: Jonathan Greene, Frank Hawley, John McCollum
  • Patent number: 8981331
    Abstract: In some embodiments, a memory cell is provided that includes a metal-insulator-metal stack and a steering element coupled to the metal-insulator-metal stack. The metal-insulator-metal stack includes a first conductive layer, a reversible resistivity switching layer above the first conductive layer, and a second conductive layer above the reversible resistivity switching layer. The first conductive layer and/or the second conductive layer includes a first semiconductor material layer. The steering element includes the first semiconductor material layer. Numerous other aspects are provided.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: March 17, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Chuanbin Pan, Andrei Mihnea, Steven Maxwell, Kun Hou
  • Patent number: 8981330
    Abstract: A memory device includes an array of contacts and a patterned insulating layer over the array of contacts. The patterned insulating layer includes a trench. The trench includes a sidewall aligned over a plurality of contacts in the array. A plurality of bottom electrodes on a lower portion of the sidewall contacts respective top surfaces of the contacts in the plurality of contacts. A thermally confined spacer of memory material between the patterned insulating layer and an insulating fill material is formed on an upper portion of the sidewall in contact with the plurality of bottom electrodes.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: March 17, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8981325
    Abstract: A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin film 4 contains any one of elements selected from Cu, Ag, Zn and the memory thin film 4 or the layer 3 in contact with the memory thin film 4 contains any one of elements selected from Te, S, Se. The memory device can record and read information with ease stably, and this memory device can be manufactured easily by a relatively simple manufacturing method.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Katsuhisa Aratani, Akihiro Maesaka, Akira Kouchiyama, Tomohito Tsushima
  • Patent number: 8976565
    Abstract: MIMCAP diodes are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP diodes can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a barrier height modification layer, a low leakage dielectric layer and a high leakage dielectric layer. The layers can be sandwiched between two electrodes.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventor: Prashant B Phatak
  • Patent number: 8975148
    Abstract: Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: March 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Roberto Bez, Lorenzo Fratin
  • Patent number: 8969845
    Abstract: A memory cell is provided that includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. Numerous other aspects are provided.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: March 3, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Chuanbin Pan, Andrei Mihnea, Steven Maxwell, Kun Hou
  • Patent number: 8969843
    Abstract: According to one embodiment, a memory device includes first and second conductive layers, a variable resistance portion, and a multiple tunnel junction portion. The variable resistance portion is provided between the first and second conductive layers. The multiple tunnel junction portion is provided between the first conductive layer and the variable resistance portion, and includes first, second, and third tunnel insulating films, and first and second nanocrystal layers. The first nanocrystal layer between the first and second tunnel insulating films includes first conductive minute particles. The second nanocrystal layer between the second and third tunnel insulating films includes second conductive minute particles.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryuji Ohba
  • Patent number: 8962387
    Abstract: Some embodiments include methods of forming memory cells in which a metal oxide material is formed over a first electrode material, an oxygen-sink material is formed over and directly against the metal oxide material, and a second electrode material is formed over the oxygen-sink material. The second electrode material is of a different composition than the oxygen-sink material. The metal oxide material is treated to transfer oxygen from a region of the metal oxide material to the oxygen-sink material and thereby subdivide the metal oxide material into at least two regions, with one of the regions nearest the oxygen-sink material being relatively oxygen depleted relative to another of the regions.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Bhaskar Srinivasan
  • Patent number: 8962384
    Abstract: Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive memory cells can include forming a first resistive memory cell having a first heater element angled with respect to a vertical plane, forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater, and forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Giorgio Servalli, Pietro Petruzza, Cinzia Perrone
  • Patent number: 8952493
    Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 10, 2015
    Assignees: Adesto Technologies Corporation, Artemis Acquisition LLC
    Inventor: Sandra Mege
  • Patent number: 8952349
    Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 10, 2015
    Assignee: Crossbar, Inc.
    Inventors: Wei Lu, Sung Hyun Jo
  • Patent number: 8941094
    Abstract: Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: January 27, 2015
    Assignee: Nantero Inc.
    Inventors: C. Rinn Cleavelin, Thomas Rueckes, H. Montgomery Manning, Darlene Hamilton, Feng Gu
  • Patent number: 8941089
    Abstract: In accordance with an embodiment of the present invention, a resistive switching device includes an opening disposed within a first dielectric layer, a conductive barrier layer disposed on sidewalls of the opening, a fill material including an inert material filling the opening. A solid electrolyte layer is disposed over the opening. The solid electrolyte contacts the fill material but not the conductive barrier layer. A top electrode is disposed over the solid electrolyte.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: January 27, 2015
    Assignee: Adesto Technologies Corporation
    Inventors: Chakravarthy Gopalan, Jeffrey Shields, Venkatesh Gopinath, Janet Siao-Yian Wang, Kuei-Chang Tsai
  • Patent number: 8937290
    Abstract: Some embodiments include memory cells. A memory cell may contain a switching region and an ion source region between a pair of electrodes. The switching region may be configured to reversibly retain a conductive bridge, with the memory cell being in a low resistive state when the conductive bridge is retained within the switching region and being in a high resistive state when the conductive bridge is not within the switching region. The memory cell may contain an ordered framework extending across the switching region to orient the conductive bridge within the switching region, with the framework remaining within the switching region in both the high resistive and low resistive states of the memory cell.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: January 20, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Sills
  • Patent number: 8927957
    Abstract: A memory device includes a first conductor, a diode, a memory element, and a second conductor arranged in series. The diode includes a first semiconductor layer over and in electrical communication with the first conductor. A patterned insulating layer has a sidewall over the first semiconductor layer. The diode includes an intermediate semiconductor layer on a first portion of the sidewall, and in contact with the first semiconductor layer. The intermediate semiconductor layer has a lower carrier concentration than the first semiconductor layer, and can include an intrinsic semiconductor. A second semiconductor layer on a second portion of the sidewall, and in contact with the intermediate semiconductor layer, has a higher carrier concentration than the intermediate semiconductor layer. A memory element is electrically coupled to the second semiconductor layer. The second conductor is electrically coupled to the memory element.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: January 6, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8927328
    Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: January 6, 2015
    Assignee: SK Hynix Inc.
    Inventor: Suk Ki Kim
  • Patent number: 8921816
    Abstract: Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: December 30, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Bo-Young Seo, Byung-Suo Shim, Yong-Kyu Lee, Tea-Kwang Yu, Ji-Hoon Park
  • Patent number: 8916414
    Abstract: To form a memory cell with a phase change element, a hole is formed through an insulator to a bottom electrode, and a phase change material is deposited on the insulator surface covering the hole. A confining structure is formed over the phase change material so the phase change material expands into the hole when heated to melting to become electrically connected to the bottom electrode. A top electrode is formed over and electrically connects to the phase change material. The bottom electrode can include a main portion and an extension having a reduced lateral dimension. The confining structure can include capping material having a higher melting temperature than the phase change material, and sufficient tensile strength to ensure the phase change material moves into the hole when the phase change material melts and expands. The hole can be a J shaped hole.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: December 23, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Huai-Yu Cheng, Hsiang-Lan Lung
  • Patent number: 8916949
    Abstract: A resistive memory device and a method for manufacturing the same are provided. The resistive memory device includes a lower electrode, a variable resistive layer formed on the lower electrode and configured so that the volume thereof is contracted or expanded according to temperature, and an upper electrode formed on the variable resistive layer. At least a portion of the lower electrode is configured to be electrically connected to the upper electrode.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyo Seob Yoon, Han Woo Cho
  • Patent number: 8916847
    Abstract: A variable resistance memory device includes a plurality of first conductive lines extended in a first direction, a plurality of second conductive lines arranged over or under the first conductive lines and extended in a second direction crossing the first direction, an insulating layer disposed between the first conductive lines and the second conductive lines and having a trench extended in the second direction and defined by a first side wall and a second sidewall facing each other and a bottom surface connecting the first sidewall and the second sidewall, and a variable resistance material layer formed on the first and second sidewalls and the bottom surface of the trench, wherein the first and second sidewalls of the trench overlap two adjacent second conductive lines, respectively.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyun-Min Lee, Jung-Taik Cheong
  • Patent number: 8912515
    Abstract: A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: December 16, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8912516
    Abstract: A memory element, including: a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer containing an oxide, and the resistance change layer being provided on the first electrode side, and an ion source layer in a stacking structure of two or more of a unit ion source layer, the unit ion source layer including a first layer and a second layer, the first layer containing one or more of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and an easy-to-move element that is easy to move in the memory layer, and having a density distribution of the easy-to-move element from the first electrode to the second electrode, and the second layer containing a difficult-to-move element that is difficult to move in the memory layer.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: December 16, 2014
    Assignee: Sony Corporation
    Inventors: Kazuhiro Ohba, Tetsuya Mizuguchi, Shuichiro Yasuda, Masayuki Shimuta, Katsuhisa Aratani
  • Patent number: 8912520
    Abstract: A nanoscale switching device has an active region disposed between two electrodes of nanoscale widths. The active region contains a switching material that carries mobile ionic dopants capable of being transported over the active region under an electric field to change a resistive state of the device. The switching material further carries immobile ionic dopants for inhibiting clustering of the mobile ionic dopants caused by switching cycles of the device. The immobile ionic dopants have a charge opposite in polarity to the charge of the mobile ionic dopants, and are less mobile under the electric field than the mobile ion dopants.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: December 16, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Matthew Pickett, Gilberto Ribeiro
  • Patent number: 8907318
    Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Sonehara, Takayuki Okamura, Takashi Shigeoka, Masaki Kondo
  • Patent number: 8895401
    Abstract: A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 25, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Kristy A. Campbell
  • Patent number: 8890107
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Patent number: 8884262
    Abstract: A non-volatile memory device is provided wherein a lower molding layer is formed on a substrate; a first horizontal interconnection is formed on the lower molding layer; an upper molding layer is formed on the first horizontal interconnection; a pillar is formed connected to the substrate by vertically passing through the upper molding layer, the first horizontal interconnection and the lower molding layer. The pillar has a lower part and an upper part, wherein the lower part is disposed on the same level as the first horizontal interconnection and has a first width and the upper part is disposed on a higher level than the first horizontal interconnection and has a second width different from the first width.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Su Ju, Sun-Jung Kim, Soo-Doo Chae
  • Patent number: 8884261
    Abstract: A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: November 11, 2014
    Assignee: Crossbar, Inc.
    Inventors: Sung Hyun Jo, Wei Lu
  • Patent number: 8884397
    Abstract: A memory device 10 having an arrangement in which a memory thin film is sandwiched between first and second electrodes, the memory thin film contains at least rare earth elements, the memory thin film 4 or a layer in contact with the memory thin film contains any one of elements selected from Cu, Ag, Zn and the memory thin film or the layer in contact with the memory thin film contains any one of elements selected from Te, S, Se.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventors: Katsuhisa Aratani, Akihiro Maesaka, Akira Kouchiyama, Tomohito Tsushima
  • Patent number: 8885381
    Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: November 11, 2014
    Assignee: Sandisk 3D LLC
    Inventor: Roy E. Scheuerlein
  • Patent number: 8878240
    Abstract: A variable resistance memory device that includes a first electrode, a second electrode, a variable resistance layer interposed between the first electrode and a second electrode. A metal oxide electrode is interposed between the first electrode and the variable resistance layer, and the metal oxide electrode does not include a nitrogen constituent.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 4, 2014
    Assignee: SK Hynix Inc.
    Inventors: Ji-Won Moon, Sung-Hoon Lee, Sook-Joo Kim
  • Patent number: RE45356
    Abstract: Provided are a phase-change memory device using a phase-change material having a low melting point and a high crystallization speed, and a method of fabricating the same. The phase-change memory device includes an antimony (Sb)-selenium (Se) chalcogenide SbxSe100-x phase-change material layer contacting a heat-generating electrode layer exposed through a pore and filling the pore. Due to the use of SbxSe100-x in the phase-change material layer, a higher-speed, lower-power consumption phase-change memory device than a GST memory device can be manufactured.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Min Yoon, Nam Yeal Lee, Sang Ouk Ryu, Seung Yun Lee, Young Sam Park, Kyu Jeong Choi, Byoung Gon Yu