Abstract: A ladder filter includes a piezoelectric substrate, an antenna terminal, a transmission terminal, and ground terminals on the piezoelectric substrate, and IDT electrodes. Each of the IDT electrodes is disposed on the piezoelectric substrate and includes a plurality of electrode fingers and a pair of busbars to which first ends of the plurality of electrode fingers are connected commonly. The IDT electrodes define elastic wave resonators. The ladder filter further includes an interlayer insulating film disposed on at least one of the busbars and a thermally conductive member made of a material with thermal conductivity higher than that of the interlayer insulating film and disposed on the interlayer insulating film. The thermally conductive member is in contact with at least one of the antenna terminal, the transmission terminal, and the ground terminals.

Abstract: A substrate transfer method of a substrate processing apparatus that includes a load lock chamber including a drive unit that is capable of forming, between a first opening at an atmospheric side and a second opening connected to a transfer chamber of a housing of the load lock chamber, each of a first space in which a single substrate is capable of being transferred, and a second space in which a plurality of substrates are capable of being transferred, the substrate transfer method including selecting either of the first space or the second space of the load lock chamber in accordance with process statuses of substrates at a plurality of processing chambers, and controlling the drive unit based on the selected result to form either of the first space or the second space.

Abstract: A targeted-annealing system can automatically cure a conductive paste that may bind cascaded strips of a string. The targeted-annealing system can include a first heat-treating bar that may be heated to a first curing temperature, and can include a second heat-treating bar that may be heated to a second curing temperature. During operation, a controller of the targeted-annealing system can activate one or more actuators to conform the first heat-treating bar to a top surface of two cascaded strips, and conform the second heat-treating bar to a bottom surface of two cascaded strips. The first and second heat-treating bars may be aligned along an overlap portion between the two cascaded strips, and can heat the overlap portion to 160 degrees Celsius.

Abstract: A string-forming system is described. The string-forming system may include at least a first cell-lifting mechanism and a second cell-lifting mechanism that can automatically arrange a set of strips of a photovoltaic structure into a cascaded formation. During operation, a controller can cause the first cell-lifting mechanism to lift a first strip from a first platform, and can cause the second cell-lifting mechanism to lift, from the first platform, a second strip that may follow the first strip on the first platform. The controller may then activate a first shifting actuator of the first cell-lifting mechanism or a second shifting actuator of the second cell-lifting mechanism to place a leading edge of the second strip above a trailing edge of the first strip.

Abstract: A capacitor assembly that is capable of performing under extreme conditions, such as at high temperatures and/or high voltages, is provided. The ability to perform at high temperature is achieved in part by enclosing and hermetically sealing the capacitor element within a housing in the presence of a gaseous atmosphere that contains an inert gas, thereby limiting the amount of oxygen and moisture supplied to the solid electrolyte of the capacitor element. Furthermore, the present inventors have also discovered that the ability to perform at high voltages can be achieved through a unique and controlled combination of features relating to the formation of the anode, dielectric, and solid electrolyte. For example, the solid electrolyte is formed from a combination of a conductive polymer and a hydroxy-functional nonionic polymer.

Abstract: A plurality of support pins that support a semiconductor wafer are located upright on a top surface of a susceptor. A condenser lens is located on a bottom surface of the susceptor opposite to the support pins with respect to the susceptor. The condenser lens is located such that its optical axis coincides with the central axis of the corresponding support pin. Of light emitted from halogen lamps from below, light entering the condenser lens is condensed at a contact portion between the corresponding support pin and the semiconductor wafer, so that the vicinity of the contact portion rises in temperature. The vicinity of the contact portion of the semiconductor wafer in contact with the support pin in which the temperature tends to drop is relatively intensely heated in order to suppress the temperature drop, and an in-plane temperature distribution of the semiconductor wafer during light irradiation can thus be made uniform.

Abstract: A system and method for a cluster tool apparatus for processing a semiconductor product including processing modules located adjacent each other and configured to process a semiconductor module, loadlocks configured to retain and dispense unprocessed semiconductor products and each positioned adjacent one of the processing modules, a robot configured to load, transfer and unload a semiconductor product to and from the processing modules, a hardware controller in communication with the robot and executing a method to close down the cluster tool apparatus to an idle state, the method including determining a status of the processing modules, determining if a close down process is required based on the status or based on a close down signal, and, if required, determining a schedule for a close down process based on a semiconductor product residency parameter, and controlling the operation of the robot based on the schedule to perform the close down process.

Abstract: A substrate processing apparatus includes a substrate retaining mechanism; a detecting unit detecting a placed state of the substrate retained by the substrate retaining mechanism; a first determination unit comparing detection data of the substrate obtained by the detecting unit with master data that is a reference to determine if the detection data is within a first allowed value; a confirmation unit confirming substrate type; a second determination unit comparing the detection data of the substrate with the master data to determine if the detection data is within a second allowed value; and a transfer control unit controlling the substrate retaining mechanism depending on a determination result of the second determination unit when substrate type is confirmed as a predetermined type by the confirmation unit when it is determined that the detection data is not within the first allowed value as determined by the first determination unit.

Abstract: Implementations described herein generally relate to a method and apparatus for processing substrates in a processing system. The method includes identifying, in a buffer chamber coupled to a transfer chamber of a processing system, a first substrate that has been in the buffer chamber longer than a predetermined duration and identifying a first destination chamber of the processing system for the first substrate. After identifying the first substrate, a buffer chamber time-out operation is performed. The buffer time out operation includes suspending movement of substrates from a load lock chamber to the transfer chamber and removing the first substrate from the buffer chamber.

Abstract: A plasma processing device may include a plasma processing chamber, a plasma electrode assembly, a wafer stage, a plasma producing gas inlet, a plurality of vacuum ports, at least one vacuum pump, and a multi-port valve assembly. The multi-port valve assembly may comprise a movable seal plate positioned in the plasma processing chamber. The movable seal plate may comprise a transverse port sealing surface that is shaped and sized to completely overlap the plurality of vacuum ports in a closed state, to partially overlap the plurality of vacuum ports in a partially open state, and to avoid substantial overlap of the plurality of vacuum ports in an open state. The multi-port valve assembly may comprise a transverse actuator coupled to the movable seal plate and a sealing actuator coupled to the movable seal plate.

Abstract: A method includes providing a semiconductor processing system that includes a plurality of units. Each unit has a configuration that defines a predetermined orientation of a wafer that is provided in the unit and includes a plurality of wafer handling elements. An arrangement of the plurality of wafer handling elements of the unit relative to the predetermined orientation of the wafer is adjustable. For each of the plurality of units, the arrangement of the plurality of wafer handling elements of the unit is adjusted relative to the predetermined orientation of the wafer. For each of the plurality of units, an arrangement of the plurality of wafer handling elements relative to the predetermined orientation of the wafer is provided that is different from the arrangement of the plurality of wafer handling elements relative to the predetermined orientation of the wafer in one or more other units of the plurality of units.

Abstract: The scheduling problem of a multi-cluster tool with a tree topology whose bottleneck tool is process-bound is investigated. A method for scheduling the multi-cluster tool to thereby generate an optimal one-wafer cyclic schedule for this multi-cluster tool is provided. A Petri net (PN) model is developed for the multi-cluster tool by explicitly modeling robot waiting times such that a schedule is determined by setting the robot waiting times. Based on the PN model, sufficient and necessary conditions under which a one-wafer cyclic schedule exists are derived and it is shown that an optimal one-wafer cyclic schedule can be always found. Then, efficient algorithms are given to find the optimal cycle time and its optimal schedule. Examples are used to demonstrate the scheduling method.

Abstract: A SAW filter includes a substrate, an upper bus bar arranged on the substrate, a lower bus bar arranged on the substrate so as to face the upper bus bar, a first finger IDT arranged so as to be connected to the upper bus bar at one end, a second finger IDT arranged so as to be connected to the lower bus bar at one end, a passivation part formed on the first finger IDT and the second finger IDT, a first metal part formed on the passivation part and including all area of the upper bus bar and a partial area of the first finger IDT, and a second metal part formed on the passivation part and including all area of the lower bus bar and a partial area of the second finger IDT.

Abstract: A substrate transporting apparatus includes a first light emitting sensor emitting a first sensing light in a first direction, a first light receiving sensor receiving the first sensing light, a second light emitting sensor emitting a second sensing light in a second direction different than the first direction, a second light receiving sensor receiving the second sensing light, a substrate transporting loader passing through traveling lines of the first sensing light and the second sensing light, a state information storage unit storing state information of the substrate transporting loader, and an operation information computing unit computing operation information of the substrate transporting loader based on the state information.

Abstract: A heater or cooler chamber for a batch of more than one workpiece includes a heat storage block. In the block a multitude of pockets are provided, whereby each of the pockets may be closed or opened by a controllably operated door. A heater or cooler arrangement is applied. The pockets are tailored to surround a workpiece applied therein in a non-contact closely spaced manner.

Abstract: A manufacturing line for a semiconductor device according to the invention is a manufacturing line for manufacturing a semiconductor device by circulating a workpiece along a conveyance route on which a plurality of treatment devices are arranged. The conveyance route includes a first route on which the treatment devices with a large number of times of treatment are arranged, and a second route on which the treatment devices with a small number of times of treatment are arranged. Besides, the conveyance route makes a changeover between the conveyance of the workpiece that has moved along the first route to the first route in a continuous manner, and the conveyance of the workpiece that has moved along the first route to the second route.

Abstract: A method of degassing semiconductor substrates includes sequentially loading a plurality of semiconductor substrates into a degas apparatus, and degassing the semiconductor substrates in parallel, the degassing of each semiconductor substrate commencing at a different time related to the time at which the semiconductor substrate was loaded into the degas apparatus. The method further includes unloading a semiconductor substrate from the degas apparatus when the semiconductor substrate has been degassed, while semiconductor substrates which were loaded later in the sequence are still being degassed. The degassing of the semiconductor substrates is performed at pressure of less than 10?4 Torr, and the degas apparatus is pumped continuously during the degassing of the semiconductor substrates.

Abstract: The present invention provides a technique for improving the productivity of a processing apparatus including a plurality of process chambers. There is provided a technique including a method for manufacturing a semiconductor device including: (a) transferring a last remaining substrate stored in an xth storage unit of a plurality of storage units to an empty nth chamber in an mth processing unit of a plurality of processing units; and (b) transferring a first one of a plurality of substrates stored in an (x+1)th storage unit of the plurality of storage units to one of chambers in an (m+1)th processing unit of the plurality of processing units (where x, m and n are natural numbers).

Abstract: Embodiments of the present disclosure can help increase throughput and reduce resource conflicts and delays in semiconductor processing tools. An exemplary method according to various aspects of the present disclosure includes analyzing, by a computer program operating on a computer system, a plurality of expected times to complete each of a respective plurality of actions to be performed by a semiconductor processing tool, the semiconductor processing tool including a first process module and a second process module.

Abstract: A plating apparatus is described. The apparatus includes: a substrate holder configured to hold a substrate in a vertical position; at least one processing bath configured to process the substrate held by the substrate holder; a transporter configured to grip and horizontally transport the substrate holder; at least one lifter configured to receive the substrate holder from the transporter, lower the substrate holder to place the substrate holder in the processing bath, elevate the substrate holder from the processing bath after processing of the substrate, and transfer the substrate holder to the transporter; and a controller configured to control operations of the transporter and the lifter.

Abstract: An object is to prevent down flow gas from entering into a pod in an open state in an EFEM system. An upper canopy is provided along the upper edge of an opening portion on the mini-environment side to block down flow along the opening portion. The upper canopy provides a space in which inert gas supplied through a supply port provided in the pod flows into the mini-environment through the opening of the pod after circulating inside the pod. The down flow has no effect in this space, and the entrance of down flow into the pod can be prevented.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first material layer over a substrate. The first material layer has a sidewall defining a first opening, wherein the first opening has a first shape. The method also includes forming a sacrificial feature within the first opening and the sacrificial feature has a second shape, which is different than the first shape such that there is a cavity between an edge of the sacrificial feature and the sidewall of the first material layer. The method also includes filling in cavity with a second material layer, removing the sacrificial feature to form a second opening, filling in the second opening with a third material layer, removing the second material layer to reveal the cavity and forming a conductive feature within the cavity.

Abstract: A thin film deposition system for depositing a thin film on a moveable substrate using atmospheric pressure atomic-layer deposition includes a chamber and a moveable substrate having a levitation stabilizing structure located on the moveable substrate that defines an enclosed interior impingement area of the moveable substrate. A stationary support, located in the chamber, supports the moveable substrate. The stationary support extends beyond the enclosed interior impingement area. A pressurized-fluid source provides a fluid flow through the stationary support that impinges on the moveable substrate within the enclosed interior impingement area of the moveable substrate sufficient to levitate the moveable substrate and expose the moveable substrate to the fluid while restricting the lateral motion of the moveable substrate with the levitation stabilizing structure.

Abstract: According to an exemplary embodiment, a method of detecting edge cracks in a die under test is provided. The method includes the following operations: receiving a command signal; providing power from the command signal; providing a response signal based on the command signal; and self-destructing based on the command signal.

Abstract: Embodiments of method for cooling a wafer in an ion implantation process are provided. A method for cooling the wafer in the ion implantation process includes placing the wafer in a process module. The method also includes performing the ion implantation process on the wafer and simultaneously cooling the wafer in the process module. The method further includes removing the wafer from the process module. In addition, the method includes heating up the wafer.

Abstract: In a processing system of a linear tool in which plural carrying robots are arranged in carrying mechanical units to which processing modules are coupled and a processing target is delivered and received between the plural carrying robots, in the case where there are plural carrying routes on which the processing target is carried, the present invention provides a technique for determining the carrying route on which the highest throughput can be obtained. In the processing system of a linear tool, in the case where there are plural carrying routes on which the processing target is carried, the throughputs of the respective carrying routes are compared to each other, and the carrying route is determined by a unit for selecting the carrying route with the highest throughput.

Abstract: A solid electrolytic capacitor includes a porous sintered body made of a valve metal, a dielectric layer on the porous sintered body, a solid electrolyte layer on the dielectric layer, and a cathode layer on the solid electrolyte layer. The solid electrolyte layer includes an inner electrode layer covering the dielectric layer inside the porous sintered body and an outer electrode layer covering the inner electrode layer outside the porous sintered body. The outer electrode layer includes a solid particle containing layer formed by applying a dispersion material liquid containing a conductive polymer dispersion material, solid particles and a solvent to the inner electrode layer and then removing the solvent.

Abstract: A method for fabricating an EDLC includes (a) coating a porous activated carbon material onto current collector sheets to form carbon-based electrodes, (b) drying the carbon-based electrodes, (c) winding or stacking carbon-based electrodes interleaved with separator sheets to fabricate a jelly roll or prismatic electrode assembly, (d) inserting the electrode assembly into a package and forming electrical connections between the electrode assembly and package terminals, (e) filling the package with a liquid electrolyte, and (f) sealing the package. Steps (a)-(f) are performed in an atmosphere having a low moisture content. The atmosphere may be vacuum or purged with dry gas.

Abstract: A membrane enhanced deionized capacitor (MEDC) device, consisting of insulating plates (6,7) and a series of MEDC unit cells, is provided. The MEDC unit cell includes a cation and anion ion-exchange membranes (2,4), one pair of carbon electrodes (1-1,1-2), a spacer (3) and an insulating holder (5) and is assembled in the order of [(1-1)/(2)/(3)/(5)/(4)/(1-2)]. The cation-exchange membrane combined with one electrode is used as negative electrosorptive electrode while the anion-exchange membrane combined with another electrode is used as positive electrode. Unit cells can be connected with each other in series, or in parallel. The devices can be made as either stack type or roll type.

Abstract: A robot for use in vacuum chambers is disclosed. The robot may be mounted within an oblong transfer chamber and may be translated within the transfer chamber by an umbilical arm operating in conjunction with a linear motion guide and carriage. Motors or drive systems for the robot may be housed in atmospheric conditions, and the transfer chamber may be kept at a vacuum. The robot may include one or more arms configured for wafer handling. The robot may include one or more motors or drive systems and a multi-axial seal to realize independent extension/retraction of each arm and overall simultaneous rotation of the arm assembly.

Abstract: In some embodiments, a linked processing tool system is provided that includes (1) a first processing tool having at least a first transfer chamber configured to couple to a plurality of processing chambers; (2) a second processing tool having at least a second transfer chamber configured to couple to a plurality of processing chambers; (3) a third transfer chamber coupled between the first and second processing tools and configured to transfer substrates between the first and second processing tools; and (4) a single sequencer that controls substrate transfer operations between the first processing tool, the second processing tool and the third transfer chamber of the linked processing tool system. Numerous other aspects are provided.

Abstract: The present invention relates to an apparatus for the manufacture of semiconductor devices wherein the apparatus includes a bonding module that has a vacuum chamber to provide bonding of wafers under pressure below atmospheric pressure; and a loadlock module connected to the bonding module and configured for wafer transfer to the bonding module. The loadlock module is also connected to a first vacuum pumping device configured to reduce the pressure in the loadlock module to below atmospheric pressure. The bonding and loadlock modules remain at a pressure below atmospheric pressure while the wafer is transferred from the loadlock module into the bonding module.

Abstract: A layout pattern generating apparatus and a layout pattern generating method for an element used for layout design of a semiconductor integrated circuit (LSI) provide a reduction in time for generating a layout pattern with high versatility. The layout pattern generating apparatus for generating a layout pattern of each of elements included in a semiconductor integrated circuit, includes, for example, a storage, a basic figure generator, an additional figure generator, a display unit and an operation input unit. The apparatus and method also utilize at least terminal figure relative position information, figure adjustment value information, and additional figure relative position information, the additional figure being a figure other than the basic figure. The basic figure generator generates the effective area figure and the terminal figure of the layout pattern generation target element, and the additional figure generator generates the additional figure of the layout pattern generation target element.

Abstract: A bridging chamber is constructed between adjacent substrate processing workstation systems and connected by ports constructed in the adjacent substrate processing workstation systems. Transport mechanisms are used to move the substrates into and out of the bridging chamber to bypass primary transport systems.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: A combinatorial processing system having modular dispense heads is provided. The modular dispense heads are disposed on a rail system enabling an adjustable pitch of the modular dispense heads for the combinatorial processing. The modular dispense heads are configured so that sections of the modular dispense heads are detachable in order to accommodate various processes through a first section without having to completely disconnect and re-connect facilities to a second section.

Abstract: A solid solution-comprising ceramic article useful in semiconductor processing, which article may be in the form of a solid, bulk ceramic, or may be in the form of a substrate having a ceramic coating of the same composition as the bulk ceramic material on at least one outer surface. The ceramic article is resistant to erosion by halogen-containing plasmas and provides advantageous mechanical properties. The solid solution-comprising ceramic article is formed from a combination of yttrium oxide and zirconium oxide. The ceramic-comprising article includes ceramic which is formed from zirconium oxide at a molar concentration ranging from about 96 mole % to about 91 mole %, and yttrium oxide at a molar concentration ranging from about 4 mole % to about 9 mole %.

Abstract: An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit.

Abstract: Medical devices and methods for making and using medical devices are disclosed. An example medical device for sympathetic nerve ablation may include a catheter shaft. An expandable balloon may be coupled to the catheter shaft. The balloon may be capable of shifting between an unexpanded configuration and an expanded configuration. The balloon may include a first layer and a second layer. The first layer may include a convertible circuit. An electrode may be coupled to the balloon and may be in electrical contact with the convertible circuit.

Abstract: The present invention relates to a method of manufacturing an optical device for a back light unit, and an optical device and an optical device array manufactured by the method, in which optical device chips constituting the optical device array are each laid the sides thereof on a printed circuit board in such a manner that light can be emitted from the optical device chips in a lateral direction, thus reducing the overall thickness of the back light unit.

Abstract: A manufacturing method of an oscillator is a manufacturing method of an oscillator which includes a vibrator and a semiconductor circuit device including an oscillation part connected to the vibrator and a control part to switch an operation mode between a normal mode in which the oscillation part performs an oscillation operation and an inspection mode in which characteristics of the vibrator are inspected, and the manufacturing method includes preparing the semiconductor circuit device in which the operation mode is set to the inspection mode, connecting the semiconductor circuit device and the vibrator electrically, and inspecting the characteristics of the vibrator which is in a state electrically connected to the semiconductor circuit device.

Abstract: An optical subassembly includes a thru optical via (104) formed through a semiconductor substrate (102), an optoelectronic component (108) secured to the substrate (102) such that an active region (106) of the optoelectronic component is aligned with the thru optical via (104), and circuitry (110) formed into the substrate (102), the circuitry to connect to and operate in accordance with the optoelectronic component (108).

Abstract: A chip card device including a card-like carrier having received therein a semiconductor substrate in the form of a chip, the semiconductor substrate including at least a memory element and is provided with contact surfaces which are accessible on the surface of the card-like carrier to enable reading of the memory element therewith. The card-like carrier including a linear fold line configured for placing, on or close to a card part including the contact surfaces, a further card part situated on the side of the fold line remote from the card part.

Abstract: Various embodiments may relate to a semiconductor retrofit bulb, in particular a retrofit festoon bulb, having connecting elements that are arranged on two sides. The semiconductor retrofit bulb may include at least a tubular cooling body having at least one outer face support surface, wherein there is arranged on the support surface at least one semiconductor light source, in particular a light diode, a driver housing that is introduced into a hollow space of the tubular cooling body. At least one flow channel is provided between the driver housing and the cooling body.

Abstract: A semiconductor device includes: a block module which internally includes a power semiconductor element and a first heatsink, and from which a main circuit terminal and a control terminal are drawn; a control substrate connected to the control terminal; a package in which the block module and the control substrate are housed; and a second heatsink to which the package is fixed by a connection screw. The connection screw is inserted into the second heatsink so as to be inclined at an inclination angle ? relative to a normal to a surface of the second heatsink.

Abstract: A radiation-emitting device and a method for producing a radiation-emitting device are disclosed. In an embodiment, a radiation-emitting device comprises an optoelectronic semiconductor component and an optical element disposed downstream of the semiconductor component in an emission direction. The optical element is mechanically fixed to the semiconductor component by a clamp.

Abstract: An optical semiconductor device includes: a resonator end face; an optical waveguide; a window structure located between the resonator end face and the optical waveguide; and a vernier on the window structure and allowing measurement of length of the window structure along an optical axis direction.

Abstract: Systems, methods, and apparatus are provided for operating a cluster tool including receiving recipe time data; receiving transfer time data; receiving process programs and associated substrate lots wherein the process programs include a plurality of sequences; determining cluster tool chambers associated with sequences that are bottleneck sequences; setting equipment constant values for components of the cluster tool to implement transfer priorities wherein the chambers associated with bottleneck sequences are given highest priority; executing a next sequence based on the transfer priorities; and repeating the determining, setting and executing for each remaining sequence. Numerous additional aspects are disclosed.

Abstract: A matrix analyzer for determining the size and location of a conductive item placed thereon. The matrix analyzer includes plural row conductors and column conductors with a corresponding grid of conductive areas exposed on the surface of the matrix analyzer. When a conductive item, such as an ink droplet, is jetted onto the matrix analyzer, the intersection of various row conductors and column conductors exhibit a low resistance. The rows and columns of the matrix analyzer can be sequentially accessed to find those intersections where the low resistance exists. From such data, the size and location of the ink droplets can be determined.

Abstract: A semiconductor module includes a printed circuit board, a ceramic substrate and a semiconductor chip. The printed circuit board includes an insulating material, a cutout formed in the insulating material, and a first metallization layer, which is partly embedded into the insulating material. The first metallization layer includes a conductor track projection projecting into the cutout. The ceramic substrate includes a dielectric, ceramic insulation carrier, and an upper substrate metallization applied to a top side of the insulation carrier. The semiconductor chip is arranged on the upper substrate metallization, and the first metallization layer is mechanically and electrically conductively connected to the upper substrate metallization at the conductor track projection.