Barrier Layer Or Semiconductor Device Making Patents (Class 29/25.01)
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Publication number: 20130153277Abstract: An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed.Type: ApplicationFiled: March 22, 2011Publication date: June 20, 2013Inventors: Etienne Menard, Christopher Bower, Matthew Meitl, Philip Garrou
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Publication number: 20130145588Abstract: A woven mesh substrate with semiconductor elements and a method and a device for manufacturing such a substrate, and more particularly a technique that makes it possible to exploit a woven mesh substrate with semiconductor elements in which a plurality of spherical semiconductor elements having a light receiving function or a light-emitting function are installed on a woven mesh substrate in net form that is made up from a plurality of vertical strands that are insulating and a plurality of horizontal strands that are conductive.Type: ApplicationFiled: February 8, 2011Publication date: June 13, 2013Inventor: Josuke Nakata
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Publication number: 20130145587Abstract: A system for combinatorial processing is provided. The system includes a plurality of reactor cells. Each of the plurality of reactor cells includes a vertical recess extending along a length of the outer surface of the plurality of reactor cells. The vertical recess is operable to receive a vertical rail. The system also includes a plurality of horizontal rails extending between rows of the plurality of reactor cells. Each of the plurality of horizontal rails has a member slidably mounted thereon. The member is coupled to the vertical rail thereby enabling independent horizontal and vertical movement for each of the plurality of reactor cells.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Applicant: Intermolecular, Inc.Inventor: Edwin Adhiprakasha
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Patent number: 8451588Abstract: A solid electrolytic capacitor that includes an anode body, a dielectric overlying the anode body, a solid electrolyte overlying the dielectric, and a colloidal particle coating that overlies the solid electrolyte. The coating is formed from a colloidal particle dispersion. The particles of the dispersion contain at least two different polymer components—i.e., a conductive polymer and a latex polymer. One benefit of such a coating is that the presence of the latex polymer can help mechanically stabilize the capacitor during encapsulation due to its relatively soft nature. This helps limit delamination of the solid electrolyte and any other damage that may otherwise occur during formation of the capacitor. Furthermore, the latex polymer can also enhance the ability of the particles to be dispersed in an aqueous medium, which is desirable in various applications.Type: GrantFiled: March 11, 2011Date of Patent: May 28, 2013Assignee: AVX CorporationInventor: Martin Biler
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Publication number: 20130130425Abstract: The invention relates to a method for producing a semiconductor, of the photovoltaic cell type, or similar electronic components. According to the invention, at least one silicon wafer is cut from the cross-section of a silicon rod and, after doping, a substrate is assembled on either side of the silicon wafer and the latter is cut into two parts through the thickness of the silicon, so as to form two semiconductor units each comprising a substrate and a thin silicon film.Type: ApplicationFiled: March 25, 2010Publication date: May 23, 2013Inventor: Jean-Pierre Medina
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Publication number: 20130108204Abstract: When phases of lights passing through arms are adjusted, a first DC bias and a first modulation signal are applied to one arm from one modulating electrode, and a second DC bias and a second modulation signal are applied to the other arm from the other modulating electrode. The first and second DC biases are applied to the modulating electrodes such that a rate of a product of a length of one modulating electrode and the first DC bias and a product of a length of the other modulating electrode and the second DC bias is kept at a constant value. According to this constitution, it is possible to enable an optimum control of a phase difference between the arms and a precise control of wavelength chirp characteristics with a simple element constitution, and an optical modulation of which device size is small and having fine characteristics is enabled.Type: ApplicationFiled: October 22, 2012Publication date: May 2, 2013Applicant: FUJITSU LIMITEDInventor: FUJITSU LIMITED
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Publication number: 20130094843Abstract: A device may comprise an upper module cover, a lower module cover, an outer frame, and an actuator having a movable frame. The movable frame may be at least partially disposed intermediate the upper module cover and the lower module cover. A hinge flexure may interconnect the outer frame and the movable frame such that the movable frame is rotatable with respect to the outer frame. The upper module cover and/or the lower module cover may be adapted to limit a movement of the movable frame.Type: ApplicationFiled: December 6, 2012Publication date: April 18, 2013Applicant: DigitalOptics Corporation MEMSInventor: DigitalOptics Corporation MEMS
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Publication number: 20130095608Abstract: A method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component. A through-opening is in the lower jig and under the first package component. The underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening.Type: ApplicationFiled: October 12, 2011Publication date: April 18, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Tse Chen, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Peng Tsai, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
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Patent number: 8418358Abstract: A wiring board with a built-in component includes an insulating board, a first wiring pattern on an upper surface of the insulating board, plural electrodes on the upper surface of the insulating board, a solder resist on the upper surface of the insulating board, plural solders on the electrodes, respectively, an electronic component joined to the electrodes with the solders, a sealing resin provided between the insulating board and the electronic component, a component-fixing layer provided on the upper surface of the insulating board and the first wiring pattern and having an insulating property, a second wiring pattern on the component-fixing layer, and an interlayer wiring connecting the first wiring pattern to the second wiring pattern. The solder resist surrounds the electrodes. The sealing resin entirely covers the solders and the solder resist. This wiring board can be efficiently manufactured by simple processes.Type: GrantFiled: October 6, 2008Date of Patent: April 16, 2013Assignee: Panasonic CorporationInventor: Yoshiyuki Wada
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Patent number: 8414719Abstract: An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which is mechanically attached to a backing plate by a series of spaced apart cam locks. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release locking pins extending from the upper face of the electrode.Type: GrantFiled: June 19, 2012Date of Patent: April 9, 2013Assignee: Lam Research CorporationInventors: Roger Patrick, Gregory R. Bettencourt, Michael C. Kellogg
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Patent number: 8409967Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.Type: GrantFiled: June 6, 2011Date of Patent: April 2, 2013Assignee: STMicroelectronics (Tours) SASInventors: Vincent Jarry, Patrick Hougron, Dominique Touzet, José Mendez
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Publication number: 20130076486Abstract: An electronic device may include a housing and circuitry carried by the housing. The electronic device may also include a finger sensing device carried by the housing and coupled to the circuitry. The finger sensing device may include a mounting substrate, and a semiconductor interposer having a lower surface adjacent the mounting substrate. The finger sensing device may also include a plurality of semiconductor finger sensing die on an upper surface of the semiconductor interposer in side-by-side and abutting relation, and defining a finger sensing surface to receive at least one finger thereon.Type: ApplicationFiled: September 25, 2011Publication date: March 28, 2013Applicant: AuthenTec, Inc.Inventors: Robert H. Bond, Giovanni Gozzini
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Publication number: 20130069622Abstract: Disclosed herein are systems and methods for in-situ measurement of impurities on metal slugs utilized in electron-beam metal evaporation/deposition systems, and for increasing the production yield of a semiconductor manufacturing processes utilizing electron-beam metal evaporation/deposition systems. A voltage and/or a current level on an electrode disposed in a deposition chamber of an electron-beam metal evaporation/deposition system is monitored and used to measure contamination of the metal slug. Should the voltage or current reach a certain level, to the deposition is completed and the system is inspected for contamination.Type: ApplicationFiled: November 16, 2012Publication date: March 21, 2013Applicant: SKYWORKS SOLUTIONS, INC.Inventor: SKYWORKS SOLUTIONS, INC.
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Patent number: 8398725Abstract: When annealing of a semiconductor film is conducted using a plurality of lasers, each of the distances between laser irradiation regions is different. When a lithography step is conducted in accordance with a marker which is formed over a substrate in advance after the step, light-exposure is not correctly conducted to a portion crystallized by laser. By using a laser irradiation region obtained on a laser irradiation step as a marker, light-exposure is conducted by making a light-exposure position of a stepper coincide with a large grain size region in the laser irradiation region. A large grain size region and a poorly crystalline region are detected by utilizing a thing that scattering intensity of light is different between the large grain size region and the poorly crystalline region, thereby determining a light-exposure position.Type: GrantFiled: April 9, 2010Date of Patent: March 19, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koichiro Tanaka, Yoshiaki Yamamoto
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Publication number: 20130049916Abstract: A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die.Type: ApplicationFiled: August 26, 2011Publication date: February 28, 2013Inventors: Ann Gabrys, William French, Peter J. Hopper, Dok Won Lee, Peter Johnson
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Patent number: 8375892Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) preconditioning a process chamber with an aggressive plasma; (2) loading a substrate into the process chamber; and (3) performing plasma nitridation on the substrate within the process chamber. The process chamber is preconditioned using a plasma power that is at least 150% higher than a plasma power used during plasma nitridation of the substrate. Numerous other aspects are provided.Type: GrantFiled: March 25, 2011Date of Patent: February 19, 2013Assignee: Applied Materials, Inc.Inventors: Tatsuya Sato, Patricia M. Liu, Fanos Christodoulou
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Patent number: 8379367Abstract: Provided is a hybrid super capacitor using a composite electrode that may enhance equivalent series resistance (ESR) using a carbon nanotube chain. The hybrid super capacitor includes: an anode 11 including an anode oxide layer 11a and an activated carbon layer applied 11b on the anode oxide layer 11a; and a cathode 21 being disposed to face the anode 11. The cathode 21 may include a silicon oxide layer 21a, a lithium titanium oxide layer 21b disposed on the silicon oxide layer 21a, and a carbon nanotube chain CT formed to pass through the silicon oxide layer 21a and the lithium titanium oxide layer 21b to thereby be electrically connected to each other, thereby enhancing ESR and expanding an output density and a lifespan of the hybrid super capacitor.Type: GrantFiled: June 1, 2011Date of Patent: February 19, 2013Assignee: Samhwa Capacitor Co., Ltd.Inventors: Young Joo Oh, Jung Rag Yoon, Kyung Min Lee, Du Hee Lee
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Publication number: 20130032885Abstract: Gridded polysilicon semiconductor layouts implement double poly patterning to cut polylines of the layout into polyline segments. Devices are arranged on the polyline segments of a common polyline to reduce the area used to implement a circuit structure relative to conventional gridded polysilicon layout. Stacking of PMOS and NMOS devices is enabled by using double poly patterning to implement additional cuts which form additional polyline segments. Metal layer routing may connect nodes of separate polyline segments.Type: ApplicationFiled: August 3, 2011Publication date: February 7, 2013Applicant: QUALCOMM INCORPORATEDInventors: Chethan Swamynathan, Jay Madhukar Shah, Vijayalakshmi Ranganna, Foua Vang, Pratyush Kamal, Prayag B. Patel
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Publication number: 20130029476Abstract: A dicing process is provided for cutting a wafer along a plurality of predetermined scribe lines into a plurality of dies that are releasably adhered to a release film. The dicing process includes: (a) disposing a wafer-breaking carrier on a supporting device, the wafer-breaking carrier having a chipping unit; (b) disposing the wafer above the supporting device such that the chipping unit is at a position corresponding to the scribe lines; and (c) adhering a release surface of the release film to the wafer by applying a force to the release film to contact the chipping unit of the wafer-breaking carrier with the wafer, such that the wafer is split along the scribe lines into the dies.Type: ApplicationFiled: July 3, 2012Publication date: January 31, 2013Applicant: LEXTAR ELECTRONICS CORP.Inventors: Chien-Sen WENG, Mong-Yeng Xing, Yu-Ching Chang, Wei-Chang Yu, Yao-Hui Lin
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Patent number: 8363989Abstract: Provided is a semiconductor optical interconnection device capable of transmitting signals between laminated semiconductor chips in a structure where semiconductor chips highly functionalized by being bonded to an optical interconnection chip are laminated. The semiconductor optical interconnection device includes a semiconductor chip 1 and an optical interconnection chip 2. The optical interconnection chip 2 includes an optical element formed thereon (for instance, a photo-sensitive element, a luminous element, or an optical modulator) which has a function relating to signal conversion between light and electricity. The semiconductor chip 1 includes a transmission section 3 (for instance, a coil or an inductor) to transmit signals in a non-contact manner, and a connection section 4 (for instance, a bump) to electrically connect with the optical element.Type: GrantFiled: February 10, 2009Date of Patent: January 29, 2013Assignee: NEC CorporationInventors: Daisuke Okamoto, Kenichi Nishi, Junichi Fujikata, Jun Ushida
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Publication number: 20130014360Abstract: According to one embodiment, a stage apparatus includes a height control unit includes height control elements each which is drove in an upward/downward direction independently, a measuring unit which divides an upper surface of the substrate into areas, and measures a height of each of the areas. The control unit is configured to set the height of each of the areas independently by controlling a height of each of the height control elements based on a data value, determine using the measuring unit whether the height of each of the areas in the upper surface of the substrate is in a allowable range, and set the height of the area out of the allowable range again by the height control elements.Type: ApplicationFiled: March 23, 2012Publication date: January 17, 2013Inventors: Ryoichi INANAMI, Shinichi ITO, Hiroshi KOIZUMI, Akihiro KOJIMA
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Patent number: 8343239Abstract: The invention provides a group III nitride semiconductor manufacturing system which is free from interruption to rotation of a rotational shaft.Type: GrantFiled: October 23, 2008Date of Patent: January 1, 2013Assignee: Toyoda Gosei Co., Ltd.Inventors: Shiro Yamazaki, Koji Hirata
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Publication number: 20120326255Abstract: Disclosed is a method for manufacturing semiconductor devices. Said method includes: a supply step in which a process liquid (19) that oxidizes and dissolves a target substrate (20) to be treated is supplied to the surface of said substrate (20) to be treated; a positioning step in which a mesh-like transferring member (10b) provided with a catalyst material is positioned near or in contact with the surface of the substrate (20) to be treated; and a concave or convex forming step in which a concave or convex is formed on the surface of the substrate (20) to be treated via the aforementioned supply and positioning steps. As opposed to existing manufacturing methods, which manufacture semiconductor devices provided with semiconductor substrates with highly arbitrary (i.e.Type: ApplicationFiled: February 14, 2011Publication date: December 27, 2012Applicants: CANON MARKETING JAPAN KABUSHIKI GAISHAInventor: Hikaru Kobayashi
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Publication number: 20120319741Abstract: A buffer arrangement in wire lines in which at least one aggressor wire line is located adjacent and substantially parallel to a victim wire line has a plurality of alternately arranged inverting and noninverting buffers. The alternately arranged in a checkerboard pattern in which noninverting and inverting buffers are located in the victim wire line in locations corresponding to locations of the inverting and noninverting buffers in the at least one aggressor wire line.Type: ApplicationFiled: June 17, 2011Publication date: December 20, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Patrick Bosshart
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Publication number: 20120318331Abstract: Disclosed is a highly automated method of interconnecting flexible solar cells to form solar modules having a wide variety of sizes and electrical characteristics. The method is fast and economical, providing many attributes of a “pseudo monolithic integration” scheme that has previously been attainable only on rigid substrates.Type: ApplicationFiled: March 10, 2011Publication date: December 20, 2012Applicant: DOW GLOBAL TECHNOLOGIES LLCInventors: David Pearce, Bruce Hachtmann, Arthur Wall, Thomas Valeri, Dennis Hollars
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Publication number: 20120320517Abstract: An electronic module and method for updating an electronic device wherein the electronic module is connected to a circuit board having one or more memory interfaces which may be embodied as processors in the electronic device. One or more semiconductor devices electrically communicate with an electrical circuit within the module. A programmable memory device including non-volatile memory electrically communicates with the electrical circuit of the electronic module. The programmable memory device includes a program having code saved therein. The code defines a multiplicity of functions for the electronic module for communication between the electronic module and a memory interface or processor of the electronic device. Electrical connection elements are attached to a substrate on a bottom side of the electronic module for electrically connecting the electrical circuit of the electronic module to the circuit board for communication between the programmable memory device and the memory interface or processor.Type: ApplicationFiled: June 17, 2011Publication date: December 20, 2012Applicant: BAE SYSTEMS CONTROLS INC.Inventors: Andrew Berner, Kevin Hill
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Publication number: 20120314409Abstract: Embodiments of the invention provide an optical semiconductor-based tube type lighting apparatus capable of enlarging light distribution to have improved assembly characteristics. The lighting apparatus includes an elongated light-transmitting tube; a linear slit formed on the light-transmitting tube in a longitudinal direction thereof; and at least one bar-shaped optical semiconductor module secured to the light-transmitting tube, with edges of the slit fitted into side surfaces of the bar-shaped optical semiconductor module. Here, the optical semiconductor module includes a heat sink, a PCB attached to the heat sink, and an array of semiconductor optical devices arranged on the PCB. The heat sink is partially exposed from the light-transmitting tube through the slit.Type: ApplicationFiled: August 21, 2012Publication date: December 13, 2012Applicant: POSCO LED COMPANY LTD.Inventors: Kyung Rye KIM, Jae Young CHOI, Kyoung Onn KIM
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Publication number: 20120286406Abstract: A process for assembling a semiconductor device includes providing a lead frame having a native plane and a plurality of leads having a native lead pitch. The process includes trimming and forming a first subset of the plurality of leads to provide a first row of leads. The process includes trimming and forming a second subset of the plurality of leads to provide a second row of leads. At least one subset of leads is formed with an obtuse angle relative to the native plane such that lead pitch associated with the first or second subset of leads is greater than the native lead pitch.Type: ApplicationFiled: May 2, 2012Publication date: November 15, 2012Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Shunan QIU, Zhigang Bai, Xuesong Xu, Beiyue Yan, You Ge
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Publication number: 20120284977Abstract: A system produces devices that include a semiconductor part and a non-semiconductor part. A front end is configured to receive a semiconductor part and to process the semiconductor part. A back end is configured to receive the processed semiconductor part and to assemble the processed semiconductor part and a non-semiconductor part into a device. A transfer device is configured to automatically handle the semiconductor part in the front end and to automatically transfer the processed semiconductor part to the back end.Type: ApplicationFiled: July 25, 2012Publication date: November 15, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Oskar Neuhoff, Tobias Gamon, Norbert Martin Haueis, Dirk Pikorz, Michael Wolfgang Larisch, Franz Reithner
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Patent number: 8307437Abstract: A method and system for the classification of software in networked systems, includes: determining a software received by a sensor is attempting to execute on a computer system of the sensor; classifying the software as authorized or unauthorized to execute, and gathering information on the software by the sensor if the software is classified as unauthorized to execute. The sensor sends the information on the software to one or more actuators, which determine whether or not to act on one or more targets based on the information. If so, then the actuator sends a directive to the target(s). The target(s) updates its responses according to the directive. The classification of the software is definitive and is not based on heuristics or rules or policies and without any need to rely on any a priori information about the software.Type: GrantFiled: November 11, 2010Date of Patent: November 6, 2012Assignee: McAfee, Inc.Inventors: E. John Sebes, Rishi Bhargava
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Publication number: 20120266425Abstract: Embodiments of the invention provide a thermal processing system and methods for uniformly heating and/or cooling a semiconductor wafer. Embodiments of the invention may be applied to provide a more uniform temperature profile when processing 300 mm and larger wafers having different curvature profiles that occur at the same and/or different points in a manufacturing cycle. Wafer curvature can be dependent on the number and thickness of the metal layers.Type: ApplicationFiled: July 1, 2012Publication date: October 25, 2012Applicant: Tokyo Electron LimitedInventor: Andrew WALLMUELLER
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Publication number: 20120260719Abstract: A photo-acoustic gas sensor and methods for producing same, the gas sensor having a resonance body and a device for detecting a vibration of the resonance body, including a device for optically detecting the location of at least one partial surface of the resonance body, wherein the resonance body and the device for detecting a vibration are disposed on exactly one substrate, the resonance body is formed by at least one first recess of the substrate, and the substrate is a semiconductor material.Type: ApplicationFiled: October 7, 2010Publication date: October 18, 2012Inventor: Wolfgang Schade
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Publication number: 20120260477Abstract: One embodiment of an electrostatic protection diode in an integrated circuit includes a base area having at least two bends therein.Type: ApplicationFiled: June 14, 2012Publication date: October 18, 2012Inventors: Thomas R. Apel, Jeremy R. Middleton
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Publication number: 20120258564Abstract: The present disclosure provides one embodiment of a method. The method includes providing a semiconductor substrate having a front side and a backside, wherein the front side of the semiconductor substrate includes a plurality of backside illuminated imaging sensors; bonding a carrier substrate to the semiconductor substrate from the front side; thinning the semiconductor substrate from the backside; performing an ion implantation to the semiconductor substrate from the backside; performing a laser annealing process to the semiconductor substrate from the backside; and thereafter, performing a polishing process to the semiconductor substrate from the backside.Type: ApplicationFiled: April 5, 2011Publication date: October 11, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung Chien Wang, Yeur-Luen Tu, Chia-Shiung Tsai
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Patent number: 8279584Abstract: A capacitor assembly that includes a solid electrolytic capacitor element containing an anode body, a dielectric overlying the anode, and a solid electrolyte (e.g., conductive polymer) overlying the dielectric is provided. The anode body is in electrical contact with an anode termination and the solid electrolyte is in electrical contact with a cathode termination. The capacitor element and terminations are encapsulated within a resinous material so that at least a portion of the terminations remain exposed. In addition to enhancing mechanical robustness, the resinous encapsulating material acts in some capacity as a barrier to moisture and oxygen during use, which could otherwise reduce the conductivity of the solid electrolyte and increase ESR. To even further protect the capacitor element, especially at high temperatures, the encapsulated capacitor element is also enclosed and hermetically sealed within a ceramic housing in the presence of an inert gas.Type: GrantFiled: August 12, 2010Date of Patent: October 2, 2012Assignee: AVX CorporationInventor: Ivana Zednickova
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Publication number: 20120227229Abstract: A surface-mountable electrical circuit protection device includes layers defining a first PPTC resistive element, a second PPTC resistive element, and at least one heat-generating electrical component such as a planar zener diode chip positioned between, and in thermal contact with, the first and second PPTC elements, such that an electrical current above a threshold level passing through the component causes the component to heat, the heat being transferred to the PPTC resistive elements and tripping at least one, and preferably both of the first or second PPTC elements to a high resistance state. A series of edge-formed terminal electrodes enable surface-mount connection of the first and second PPTC elements and the electrical component to an electrical circuit substrate, such as a printed circuit board. A method for making the device is also disclosed.Type: ApplicationFiled: May 22, 2012Publication date: September 13, 2012Inventors: Wayne Montoya, Luis A. Navarro, Cecilia A. Walsh, Adrian P. Mikolajczak
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Publication number: 20120223442Abstract: During manufacture of an electronic device, an aerogel coating is applied to a first side of an IC substrate of a first IC. A bonding procedure is initiated, during which IC interconnects are either placed on the coated side of the substrate or on the opposite side of the substrate. The first IC is connected on a carrier to a second IC with the coated side of the first IC facing the second IC to reduce heat transmission to the second IC during operation of the first IC. The aerogel coating reduces thermal stress to the circuit board and surrounding components, reduces the risk of overheating of critical circuit components, provides chemical and mechanical insulation from contamination during subsequent wafer handling operations, and provides a thermal isolator between IC regions of dissimilar power dissipation, which isolator facilitates efficient thermal extraction from localized hotspots.Type: ApplicationFiled: May 11, 2012Publication date: September 6, 2012Applicant: IBM CORPORATIONInventors: Martin P. Goetz, Gary E. O'Neil
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Publication number: 20120225259Abstract: The present invention refers to a flat back plate, e.g. for MEMS capacitors e.g. for MEMS microphones. For that the back plate comprises a tensile element that exerts a horizontal tensile stress on its environment.Type: ApplicationFiled: March 2, 2011Publication date: September 6, 2012Applicant: EPCOS AGInventors: Dennis Mortensen, Pirmin Hermann Otto Rombach
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Publication number: 20120204653Abstract: Pressure sensors having components with reduced variations due to stresses caused by various layers and components that are included in the manufacturing process. In one example, a first stress in a first direction causes a variation in a component. A second stress in a second direction is applied, thereby reducing the variation in the component. The first and second stresses may be caused by a polysilicon layer, while the component may be a resistor in a Wheatstone bridge.Type: ApplicationFiled: February 16, 2011Publication date: August 16, 2012Applicant: Silicon Microstructures, Inc.Inventors: Richard J. August, Michael B. Doelle
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Publication number: 20120199988Abstract: Disclosed is a method of manufacturing an electronic device, that includes obtaining a stack of the first electronic component and the second electronic component, while placing a resin layer which contains a flux-active compound and a thermosetting resin, between the first terminals and the second terminals; bonding the first terminals and the second terminals with solder, by heating the stack at a temperature not lower than the melting point of solder layers on the first terminals, while pressurizing the stack using a fluid; and curing the resin layer. The duration from the point of time immediately after the start of heating of the stack, up to the point of time when the temperature of the stack reaches the melting point of the solder layers, is set to 5 seconds or longer, and 15 minutes or shorter.Type: ApplicationFiled: October 13, 2010Publication date: August 9, 2012Applicant: Sumitomo Bakelite Co., Ltd.Inventors: Toru Meura, Hiroki Nikaido, Kenzou Maejima, Yoji Ishimura, Kenji Yoshida
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Patent number: 8238079Abstract: A capacitor and a method for assembling a capacitor. A capacitor is assembled from a case, which contains an anode that is electrically coupled to the case and defines wells or slots receiving a plurality of cathode plates. A header is placed on the case. The header also supports a glass seal that insulates the lead tube and cathode lead coming from the cathode. Once assembled, the capacitor is filled with electrolyte. A weld extends around the header to secure the header to the case. A bent cathode configuration enables a plurality of cathode plates electrically coupled together from a common cathode plate.Type: GrantFiled: October 29, 2009Date of Patent: August 7, 2012Assignee: Tantalum Pellet CompanyInventor: Todd Knowles
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Publication number: 20120192392Abstract: The present invention relates to a method of clamping a semiconductor assembly with a desired compression force equally distributed across the opposing surfaces of the devices and associated components of the semiconductor assembly.Type: ApplicationFiled: March 9, 2012Publication date: August 2, 2012Applicant: INDUCTOTHERM CORP.Inventors: Oleg S. Fishman, Satyen N. Prabhu
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Patent number: 8231692Abstract: During manufacture of an electronic device, an aerogel coating is applied to a first side of an IC substrate of a first IC. A bonding procedure is initiated, during which IC interconnects are either placed on the coated side of the substrate or on the opposite side of the substrate. The first IC is connected on a carrier to a second IC with the coated side of the first IC facing the second IC to reduce heat transmission to the second IC during operation of the first IC. The aerogel coating reduces thermal stress to the circuit board and surrounding components, reduces the risk of overheating of critical circuit components, provides chemical and mechanical insulation from contamination during subsequent wafer handling operations, and provides a thermal isolator between IC regions of dissimilar power dissipation, which isolator facilitates efficient thermal extraction from localized hotspots.Type: GrantFiled: November 6, 2008Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Martin P. Goetz, Gary E. O'Neil
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Publication number: 20120186052Abstract: A system produces devices that include a semiconductor part and a non-semiconductor part. A front end is configured to receive a semiconductor part and to process the semiconductor part. A back end is configured to receive the processed semiconductor part and to assemble the processed semiconductor part and a non-semiconductor part into a device. A transfer device is configured to automatically handle the semiconductor part in the front end and to automatically transfer the processed semiconductor part to the back end.Type: ApplicationFiled: January 21, 2011Publication date: July 26, 2012Inventors: Oskar Neuhoff, Tobias Gamon, Norbert Martin Haueis, Dirk Pikorz, Michael Wolfgang Larisch, Franz Reithner
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Publication number: 20120187180Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.Type: ApplicationFiled: March 16, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas E. LOMBARDI, Donald MERTE, Gregg B. MONJEAU, David L. QUESTAD, Son K. TRAN
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Patent number: 8228664Abstract: A solid electrolytic capacitor with suppressed occurrence of short circuit is provided. The solid electrolytic capacitor includes an anode body having a surface on which a dielectric film is formed, and a conductive polymer layer formed on the dielectric film. The conductive polymer layer includes at least a first conductive polymer layer formed on the dielectric film and a second conductive polymer layer formed on the first conductive polymer layer. A silane compound in the first conductive polymer layer and the silane compound in the second conductive polymer layer have respective concentrations different from each other.Type: GrantFiled: August 24, 2010Date of Patent: July 24, 2012Assignees: SANYO Electric Co., Ltd., Saga Sanyo Industries Co., Ltd.Inventors: Nobuyuki Yamaguchi, Koji Fukuchi, Yasuhiro Tsunezumi
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Publication number: 20120174359Abstract: A semiconductor device includes a diode region having a plurality of protection diodes and a pad region overlapped with an upper part of the diode region. The pad region having a pad installed corresponding to an external connection terminal. The semiconductor device further includes a contact plug unit which connects at least one of a plurality of active regions constituting the diode region and the pad within the diode region.Type: ApplicationFiled: March 26, 2012Publication date: July 12, 2012Inventor: Hyang-Ja YANG
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Publication number: 20120179217Abstract: A relatively thin planar anode for use in a wet electrolytic capacitor is provided. Through a combination of specific materials and processing techniques, the present inventors have surprisingly discovered that the resulting anode may possess a high volumetric efficiency, and yet still be able to operate at a high voltage and capacitance, thus resulting in a capacitor with a high energy density. More particularly, the anode is a pressed pellet formed from an electrically conductive powder that contains a plurality of particles (including agglomerates thereof). The particles may have a flake-like morphology in that they possess a relatively flat or platelet shape. The present inventors have discovered that such a particle morphology can optimize packing density, and thus reduce the thickness of the anode and improve volumetric efficiency.Type: ApplicationFiled: January 12, 2011Publication date: July 12, 2012Applicant: AVX CORPORATIONInventors: James Steven Bates, Robert Hazen Pease
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Patent number: 8218291Abstract: A monomer and polycarbonate resin are provided, as are methods of making the monomer. The resin may be used to provide a thin film that has a higher dielectric constant and higher glass transition temperature, and similar breakdown strength and similar dissipation factor to films prepared from polycarbonate resins not so modified. The thin films, in turn, may advantageously be used to form, wholly or in part, articles such as capacitors, sensors, batteries, flexible printed circuit boards, keyboard membranes, motor/transformer insulations, cable wrappings, industrial tapes, interior coverage materials, and the like. In particular, a capacitor comprising the polycarbonate resin is also provided.Type: GrantFiled: March 31, 2010Date of Patent: July 10, 2012Assignee: General Electric CompanyInventors: Norberto Silvi, Gary Charles Davis, Patrick Joseph McCloskey, Sheldon Jay Shafer, Julia Lam Lee, Yang Cao, Patricia Chapman Irwin
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Patent number: 8218292Abstract: Solid electrolytic capacitors and related methods for forming such capacitors may variously involve forming at least one of a seed, grip, reference point and/or anode body by stencil printing of dry powder. In accordance with a method of forming anodic components for electrolytic capacitors, a stencil is positioned adjacent to a substrate, the stencil being formed to define a plurality of apertures therethrough. A plurality of printed powder portions are selectively printed on the substrate by placing dry powder into selected ones of the plurality of apertures defined in the stencil. The printed powder portions are then sintered to form respective anodic components for multiple respective electrolytic capacitors.Type: GrantFiled: July 31, 2009Date of Patent: July 10, 2012Assignee: AVX CorporationInventor: Majid Rezai-Kalantary