Barrier Layer Or Semiconductor Device Making Patents (Class 29/25.01)
  • Patent number: 8734536
    Abstract: A temperature-adjusted spectrometer can include a light source and a temperature sensor.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: May 27, 2014
    Assignee: First Solar, Inc
    Inventors: Markus E. Beck, Ming Lun Yu
  • Publication number: 20140138792
    Abstract: Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Chi Shun Lo, Je-Hsiung Lan, Mario Francisco Velez, Jonghae Kim
  • Publication number: 20140133211
    Abstract: Providing for a two-terminal memory architecture that can mitigate sneak path current in conjunction with memory operations is described herein. By way of example, a voltage mimicking mechanism can be employed to dynamically drive un-selected bitlines of the memory architecture at a voltage observed by a selected bitline. According to these aspects, changes observed by the selected bitline can be applied to the un-selected bitlines as well. This can help reduce or avoid voltage differences between the selected bitline and the un-selected bitlines, thereby reducing or avoiding sneak path currents between respective bitlines of the memory architecture. Additionally, an input/output based configuration is provided to facilitate reduced sneak path current according to additional aspects of the subject disclosure.
    Type: Application
    Filed: November 14, 2012
    Publication date: May 15, 2014
    Applicant: Crossbar, Inc.
    Inventor: Crossbar, Inc.
  • Publication number: 20140127880
    Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer.
    Type: Application
    Filed: October 18, 2013
    Publication date: May 8, 2014
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 8707796
    Abstract: A strain monitoring system including an array of semiconductor strain gauges. Each strain gauge in the array of strain gauges includes a lithographically fabricated 4-resistor bridge for providing a voltage potential corresponding to the strain in the bridge and thin film transistors to provide addressability to each 4-resistor bridge in the array. After completion of the array of strain gauges, in preferred embodiments the array of strain gauges are transferred to polyimide film which is in turn bonded to a surface region of the component to be tested for strains. Each bridge provides voltage signals corresponding to the strain to which the material under the bridge is being subjected. In preferred embodiments control and data acquisition function are separated from the semiconductor strain gage array. Preferred embodiments the system are utilized to monitor strains on components of aircraft, especially light weight robotic aircraft.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: April 29, 2014
    Inventors: Terrisa Duenas, Shiv Joshi, Cesar Del Solar
  • Patent number: 8711546
    Abstract: A method of fabricating a solid electrolytic capacitor of an aspect includes the steps of preparing an anode element with a dielectric layer formed on a surface thereof, forming a solid electrolytic layer on the dielectric layer, forming a carbon layer on the solid electrolytic layer, bringing an aqueous polymer into contact with the carbon layer, and forming a silver paste layer on the aqueous polymer. A method of fabricating a solid electrolytic capacitor and a solid electrolytic capacitor that can be improved in characteristics can thus be obtained.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: April 29, 2014
    Assignee: SANYO Electric Co., Ltd.
    Inventor: Keiko Matsuoka
  • Publication number: 20140106474
    Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.
    Type: Application
    Filed: December 17, 2013
    Publication date: April 17, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Long CHEN, Hui-Yun CHAO, Yen-Di TSEN, Jong-I MOU
  • Patent number: 8691327
    Abstract: Provided is a method of manufacturing a solid electrolytic capacitor, including the steps of: forming a capacitor element including an anode body having a dielectric coating film on a surface thereof; impregnating the capacitor element with a polymerization liquid containing a precursor monomer of a conductive polymer and an oxidant; impregnating the capacitor element impregnated with the polymerization liquid with a silane compound or a silane compound containing solution; and forming a conductive polymer layer by polymerizing the precursor monomer after impregnating the capacitor element with the silane compound or the silane compound containing solution.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 8, 2014
    Assignees: SANYO ELECTRIC Co., Ltd., SAGA SANYO INDUSTRIES Co., Ltd
    Inventors: Takeshi Furukawa, Yuichiro Inutsuka
  • Publication number: 20140082906
    Abstract: An accordion-structured welded bellows for a semiconductor-manufacturing device is characterized in that a plurality of annular bellows plates having curved surfaces in a radial direction are connected in an alternating fashion on the outside-diameter side and the inside-diameter side, wherein the annular bellows plates have a processing-side bellows plate and a non-processing-side bellows plate, a gas layer is interposed between the two bellows plates, the processing-side bellows plate is configured as a thick plate, and the non-processing-side bellows plate is configured as a thin plate. The welded bellows is less likely to be damaged by foreign matter and to be able to use the non-processing-side bellows plate to compensate for any damage to the processing-side bellows plate.
    Type: Application
    Filed: March 9, 2012
    Publication date: March 27, 2014
    Applicants: EAGLEBURGMANN JAPAN CO., LTD., EAGLE INDUSTRY CO., LTD.
    Inventors: Hidekazu Takahashi, Masahiko Inoue, Hiroyuki Ochiai
  • Publication number: 20140071666
    Abstract: An optical semiconductor-based tube type lighting apparatus capable of enlarging light distribution to have improved assembly characteristics. The lighting apparatus includes an elongated light-transmitting tube; a linear slit formed on the light-transmitting tube in a longitudinal direction thereof; and at least one bar-shaped optical semiconductor module secured to the light-transmitting tube, with edges of the slit fitted into side surfaces of the bar-shaped optical semiconductor module. The optical semiconductor module includes a heat sink, a PCB attached to the heat sink, and an array of semiconductor optical devices arranged on the PCB. The heat sink is partially exposed from the light-transmitting tube through the slit.
    Type: Application
    Filed: November 14, 2013
    Publication date: March 13, 2014
    Applicant: POSCO LED COMPANY LTD.
    Inventors: Kyung Rye KIM, Jae Young Choi, Kyoung Onn Kim
  • Publication number: 20140072876
    Abstract: Embodiments of the present invention generally relate to methods and apparatus for forming an energy storage device. More particularly, embodiments described herein relate to methods of forming electric batteries and electrochemical capacitors. In one embodiment a method of forming a high surface area electrode for use in an energy storage device is provided. The method comprises forming an amorphous silicon layer on a current collector having a conductive surface, immersing the amorphous silicon layer in an electrolytic solution to form a series of interconnected pores in the amorphous silicon layer, and forming carbon nanotubes within the series of interconnected pores of the amorphous silicon layer.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 13, 2014
    Inventors: Victor L. PUSHPARAJ, Omkaram NALAMASU, Steven VERHAVERBEKE
  • Publication number: 20140070777
    Abstract: A band gap reference voltage generator has first and second current conduction paths between a first node and a second node. The first current conduction path has first resistive elements in series with a first forward-biased PN junction element. A tap is connected selectively to the first resistive elements through switches that are controllable to select a voltage divider ratio at the tap. The second current conduction path includes a second resistive element in series with a second PN junction element of greater current density than the first PN junction. A voltage error amplifier has inputs connected to the tap and the second PN junction element, and an output for providing a thermally compensated output voltage VREF. A feedback path applies the output voltage VREF through a third resistive element to the first node.
    Type: Application
    Filed: December 14, 2012
    Publication date: March 13, 2014
    Inventors: Jianzhou Wu, Yang Wang
  • Publication number: 20140062641
    Abstract: A semiconductor transformer includes a first coil inductor and a second coil inductor. The first coil inductor has a first port, a second port and a first coil inductor wall, the first coil inductor wall having a height substantially equal to a thickness of the substrate. The second coil inductor has a third port, a first extension wall connected to the third port, a fourth port, a second extension wall connected to the fourth port and a second coil inductor wall.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Inventors: Chi-Han Chen, Pao-Nan Lee, Chi Tsung Chiu, Chien Hua Chen
  • Publication number: 20140061486
    Abstract: A spectrometer can include a plurality of semiconductor nanocrystals. Wavelength discrimination in the spectrometer can be achieved by differing light absorption and emission characteristics of different populations of semiconductor nanocrystals (e.g., populations of different materials, sizes or both). The spectrometer therefore can operate without the need for a grating, prism, or a similar optical component. A personal UV exposure tracking device can be portable, rugged, and inexpensive, and include a semiconductor nanocrystal spectrometer for recording a user's exposure to UV radiation. Other applications include a personal device (e.g. a smartphone) or a medical device where a semiconductor nanocrystal spectrometer is integrated.
    Type: Application
    Filed: February 21, 2013
    Publication date: March 6, 2014
    Inventor: Massachusetts Institute of Technology
  • Publication number: 20140053382
    Abstract: This invention relates to slicing a thin semiconductor substrate from side wall into two substrates of half thickness. The substrate slicing process involves a laser irradiation step. The apparatus for substrate slicing comprises two opposite-facing substrate chucks, with a gap in between for the substrate to pass through. The present invention is further directed to methods and apparatus of separating a continuous thin layer of materials from side wall of a rotating ingot. It can be accomplished by a laser irradiation on the ingot side wall from a tangential direction. A film can be deposited on/bonded to the ingot side wall prior to the separation of the thin film layers. The resulting thin layer of materials can be pulled away from the ingot by a substrate chuck.
    Type: Application
    Filed: December 10, 2012
    Publication date: February 27, 2014
    Inventor: Michael Xiaoxuan Yang
  • Patent number: 8657889
    Abstract: An arrangement (1) for holding a substrate (10) in a material deposition apparatus, which substrate (10) has a deposition side (10a) upon which material (M) is to be deposited, and which arrangement (1) comprises: a shadow mask (20) comprising a number of deposition openings (Di); a support structure (30) comprising a number of surround openings (Si); and a support structure holding means (6) for holding the support mask (30) and/or a substrate holding means (5) for holding the substrate (10), such that the support structure (30) is on the same side as the deposition side (10a) of the substrate (10), and the shadow mask (20) is positioned between the substrate (10) and the support structure (30) such that at least one deposition opening (Di) of the shadow mask (10) lies within a corresponding surround opening (Si) of the support structure (30).
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: February 25, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Johannes Krijne, Erwin Eiling, Karl-Heinz Hohaus, Wolfgang Goergen, Andreas Lovich, Marc Philippens, Richard Scheicher, Ansgar Fischer, Martin Mueller
  • Publication number: 20140041173
    Abstract: An electronic device comprises first, second and third inductors connected in series and formed in a metal layer over a semiconductor substrate. The first and second inductors have a mutual inductance with each other. The second and third inductors having a mutual inductance with each other. A first capacitor has a first electrode connected to a first node. The first node is conductively coupled between the first and second inductors. A second capacitor has a second electrode connected to a second node. The second node is conductively coupled between the second and third inductors.
    Type: Application
    Filed: September 4, 2013
    Publication date: February 13, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung YEN, Yu-Ling LIN, Ying-Ta LU, Chin-Wei KUO, Ho-Hsiang CHEN
  • Publication number: 20140036468
    Abstract: A display device includes an upper substrate on a lower substrate, a driver integrated chip (IC) on the lower substrate, the driver IC and upper substrate contacting different parts of the lower substrate, a plurality of bumper units along edges of the driver IC, and a deformation preventing bumper unit between the bumper units, the deformation preventing bumper unit being configured to prevent the driver IC from being deformed.
    Type: Application
    Filed: December 12, 2012
    Publication date: February 6, 2014
    Inventors: Joon-Sam KIM, Jong-Hwan KIM, Sang Won YEO, Sang-Urn LIM, Suk-Ho CHOI
  • Publication number: 20140035095
    Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.
    Type: Application
    Filed: December 20, 2012
    Publication date: February 6, 2014
    Applicant: Media Tek Inc.
    Inventors: Tzu-Hung LIN, Wen-Sung HSU, Ta-Jen YU, Andrew C. CHANG
  • Publication number: 20140028537
    Abstract: A liquid crystal panel includes an array substrate. The array substrate forms a peripheral circuit area including a COF module crimping area and a shorting bar area located outside the COF module crimping area, the shorting bar area forming at least one detecting circuit being connected to scan lines or data lines on the array substrate and being removed after the liquid crystal panel is detected. In the present disclosure, the at least one detecting circuit formed in the shorting bar area is removed after the liquid crystal panel is detected, thus, a safe area and a laser cutting area located outside the COF module crimping area can be omitted to improve the utilization rate of the liquid crystal panel.
    Type: Application
    Filed: August 10, 2012
    Publication date: January 30, 2014
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tao Song, Guodong Zhao, Ming Liu
  • Publication number: 20140013556
    Abstract: A fab can be constructed as a round or rectangular annular tube with a primary cleanspace located in-between its inner and outer tubes. The fab can be encircled with levels upon which tools can be densely packed while preserving unidirectional air flow. If only tool ports are inside, and robotics are used, primary cleanspace size can be minimized. Highly simplified robotics can be used. Tools can be removed and repaired centrally. A secondary cleanspace can be added for tool bodies. Multilevel construction enhances use of prefabricated units for fab build or maintenance. Curves or folds, applied to a conventional planar cleanroom, can construct a wide range of fab geometries, including a tubular non-annular fab. A fab can also be constructed according to a curved or non-curved sectional cut of an annular tube. A novel fab, of a non-curved section, can include a non-segmented cleanspace or have its tools vertically stacked.
    Type: Application
    Filed: September 11, 2013
    Publication date: January 16, 2014
    Inventor: Frederick A. Flitsch
  • Publication number: 20130344629
    Abstract: A method of processing IC units comprising the steps of: dicing said IC units from a substrate; delivering said IC units to a idle block; inspecting a face of said units as exposed during the dicing step using an inspection device whilst said units are on said idle block, then; engaging said units with a picker assembly; passing said units over a second inspection device to inspect an opposed face of said units.
    Type: Application
    Filed: March 2, 2012
    Publication date: December 26, 2013
    Applicant: ROKKO SYSTEMS PTE LTD
    Inventors: Seung Ho Baek, Jong Jae Jung, Tae Jin Kim
  • Publication number: 20130335676
    Abstract: The present invention disclose a backlight module comprising: a back frame, a light guide plate disposed in the back frame, a plurality of semiconductor light sources, a plurality of light source circuit boards, and a plurality of attachment members. Part of each of the light source circuit boards is disposed between the back frame and the light guide plate, and the other part of each of the light source circuit boards is exposed outside the side edge of the light guide plate, and each of the semiconductor light sources is disposed on the light source circuit boards which are exposed outside the side edge of the light guide plate. The number of the light source circuit boards, the number of the semiconductor light sources, and the number of the attachment members are all at least two, and are arranged along the direction of the side edge of the light guide plate. The present invention also discloses a manufacture method for a backlight module and a LCD device.
    Type: Application
    Filed: June 18, 2012
    Publication date: December 19, 2013
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: GuoFu Tang, Shih Hsiang Chen
  • Publication number: 20130333174
    Abstract: A semiconductor workpiece processing system including at least one substrate processing tool that has a common housing with a first side having a first substrate holding container interface and a second side having a second substrate holding container interface having a different orientation than the first substrate holding container interface, a first transport section disposed corresponding to the first side of the tool, a second transport section being separate and distinct from the first transport section and interfacing with the first transport section and being configured to transport the substrate holding container between the first transport section and the tool and between the first side and the second side of the tool, the second transport section including at least one overhead gantry disposed above the tool, where the second transfer section is capable of interfacing with at least the second substrate holding container interface.
    Type: Application
    Filed: December 3, 2012
    Publication date: December 19, 2013
    Applicant: BROOKS AUTOMATION, INC.
    Inventor: Daniel Babbs
  • Publication number: 20130320295
    Abstract: A vacuum encapsulated, hermetically sealed cathode capsule for generating an electron beam of secondary electrons, which generally includes a cathode element having a primary emission surface adapted to emit primary electrons, an annular insulating spacer, a diamond window element comprising a diamond material and having a secondary emission surface adapted to emit secondary electrons in response to primary electrons impinging on the diamond window element, a first high-temperature solder weld disposed between the diamond window element and the annular insulating spacer and a second high-temperature solder weld disposed between the annular insulating spacer and the cathode element.
    Type: Application
    Filed: May 17, 2013
    Publication date: December 5, 2013
    Applicant: Brookhaven Science Associates, LLC
    Inventors: Triveni Rao, John Walsh, Elizabeth Gangone
  • Publication number: 20130283579
    Abstract: An exemplary assembly device includes a first loading plate, a movable pole, a driving element, a first camera module, a transparent fetching element, a first processor, a first adjusting element, and a controller. The first loading plate loads a first workpiece. The movable pole is positioned above the first loading plate. The driving element drives the movable pole. The first camera module is positioned on the movable pole, and captures an image of the first workpiece to obtain a first pre-compared image. The fetching element is positioned on the movable pole. The first processor determines whether the first workpiece deviates from a standard position through comparing the first pre-compared image with a first standard image. The first adjusting element adjusts the first workpiece to the standard position. The controller controls the fetching element and the driving element cooperatively to assemble the first workpiece to a second workpiece.
    Type: Application
    Filed: September 14, 2012
    Publication date: October 31, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: KUO-FONG TSENG
  • Publication number: 20130288424
    Abstract: A fabrication line includes a texturizing module configured to texture a substrate, an emitter module configured to form an emitter region, a passivation layer module configured to form a passivation layer, a barrier contact module configured to form a barrier contact region, a firing module configured to anneal the barrier contact region, a top metal contact module configured to form a top metal contact region, and a soldering module configured to solder the barrier contact region to the top metal contact region. The modules are integrated by one or more automated substrate handlers into a single fabrication line. A method for fabricating a solar cell includes sequentially, in an automated fabrication line: doping a dopant in a substrate; disposing a passivation layer; disposing and annealing a barrier metal paste to form a barrier contact; and disposing and annealing a metal contact paste to form a top metal contact region.
    Type: Application
    Filed: March 8, 2013
    Publication date: October 31, 2013
    Inventors: Suketu Arun PARIKH, Jen SHU, James M. GEE
  • Patent number: 8551193
    Abstract: A target includes nickel and a secondary metal. The secondary metal has a volume percentage between about 1 percent and about 10 percent. The secondary metal has a density between about 5,000 kg/m3 and about 15,000 kg/m3.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: October 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Ying-Lang Wang, Kei-Wei Chen
  • Publication number: 20130259076
    Abstract: An optically pumped semiconductor laser is assembled in an enclosure comprising a base, a first mounting frame attached to the base, a second mounting frame attached to the first mounting frame and a cover attached to the second mounting frame. The assembly base, frames, and cover forms an undivided enclosure, with the frames contributing to walls of the enclosure. Components of the laser are assembled sequentially on the base and the frames. The frames are irregular in height to permit flexibility in the mounting-height of components. This reduces the extent to which compactness of the enclosure is limited by any one component.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 3, 2013
    Applicant: Coherent, Inc.
    Inventor: Matthias ROTH
  • Publication number: 20130260556
    Abstract: According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Troy L. Graves-Abe
  • Publication number: 20130252175
    Abstract: The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.
    Type: Application
    Filed: March 26, 2012
    Publication date: September 26, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Hsiung Huang, Heng-Hsin Liu, Heng-Jen Lee, Chin-Hsiang Lin
  • Publication number: 20130247342
    Abstract: A capping system includes: a moving portion moving a stem, on which an optical semiconductor element is mounted, horizontally; a fixer fixing a cap having a window, on the stem; a camera taking an image of the cap and the stem from above the cap and the stem; a detector detecting whether the optical semiconductor element is present within a visual field of the camera; and a searching action controller controlling the moving portion to move the stem so the detector searches the optical semiconductor element. The searching action controller causes searching radially and outwardly from a search starting point.
    Type: Application
    Filed: November 29, 2012
    Publication date: September 26, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Nobuyuki Kitajima
  • Patent number: 8535393
    Abstract: A method, structure, system of aligning a substrate to a photomask. The method includes: directing incident light through a pattern of clear regions transparent to the incident light in an opaque-to-the-incident-light region of a photomask, through a lens and onto a photodiode formed in a substrate, the photodiodes electrically connected to a light emitting diode formed in the substrate, the light emitting diode emitting light of different wavelength than a wavelength of the incident lights; measuring an intensity of emitted light from light emitting diode; and adjusting alignment of the photomask to the substrate based on the measured intensity of emitted light.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Axel Aguado Granados, Benjamin Aaron Fox, Nathaniel James Gibbs, Andrew Benson Maki, John Edward Sheets, II, Trevor Joseph Timpane
  • Publication number: 20130230273
    Abstract: A method for aligning an opto-electronic component in an IC die with an optical port is disclosed. This is achieved, in various embodiments, by forming alignment features in the IC die that can mate with complementary alignment features of the optical port. The formation of alignment features can be performed at the wafer level during fabrication of the IC die. An optical signal carrier may be optically coupled to the optical port such that the signal carrier may communicate optically with the opto-electronic component.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Applicant: ANALOG DEVICES, INC.
    Inventors: James Doscher, Shrenink Deliwala
  • Publication number: 20130226110
    Abstract: The disclosure relates to a semiconductor device comprising an array of containment cells, wherein each containment cell is configured to contain a medicament and each containment cell comprises a cell activation element configured to release the medicament within the containment cell upon receipt of an activation trigger.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 29, 2013
    Applicant: Johnson & Johnson Vision Care, Inc.
    Inventor: Johnson & Johnson Vision Care, Inc.
  • Patent number: 8520366
    Abstract: An improved solid electrolytic capacitor and method of forming a solid electrolytic capacitor is described. The method includes forming an anode comprising a valve metal or conductive oxide of a valve metal wherein an anode lead extension protrudes from the anode. A dielectric is formed on the anode and a cathode layer is formed on the dielectric. The anode, dielectric, and cathode layer are encased in a non-conducting material and the anode lead extension is exposed outside of the encasement at a side surface. A conductive metal layer is adhered to the anode lead extension which allows termination preferably by electrically connecting a preformed solid metal terminal, most preferably an L shaped terminal, to the conductive metal layer at the side surface.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: August 27, 2013
    Assignee: Kemet Electronics Corporation
    Inventors: Brandon Summey, Jeffrey Poltorak, Philip M. Lessner, Yongjian Qiu, Randolph S. Hahn, David Jacobs, Keith R. Brenneman, Albert Harrington, Chris Stolarski
  • Patent number: 8516906
    Abstract: A sensor substrate includes a plurality of piezoresistance elements. The electrical resistance of each piezoresistance element changes in accordance with an amount of displacement of a displacement portion displaced by an external load applied through a pressure receiving unit. A base substrate supports the sensor substrate. The sensor substrate and the base substrate each include a support supporting the displacement portion such that the displacement portion can be displaced and a plurality of electrically connecting portions electrically connected to the plurality of piezoresistance elements. The supports of the sensor and base substrates are joined to each other and the plurality of electrically connecting portions of the sensor and base substrates are joined to each other. Furthermore, in each of the sensor and base substrates, either the support or the plurality of electrically connecting portions or both extend to the periphery of the sensor substrate or the base substrate.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: August 27, 2013
    Assignee: Alps Electric Co., Ltd.
    Inventors: Eiji Umetsu, Masahiko Ishizone, Motoki Hirayama, Hideki Gochou
  • Publication number: 20130201347
    Abstract: A user presence detection device includes a camera module with a silicon-based image sensor adapted to capture an image and a processing device configured to process the image to detect the presence of a user. The camera module further includes a light filter having a lower cut-off wavelength of between 550 nm and 700 nm and a higher cut-off wavelength of between 900 nm and 1100 nm.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 8, 2013
    Applicants: STMICROELECTRONICS, INC., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: STMicroelectronics (Rousset) SAS, STMicroelectronics, Inc.
  • Publication number: 20130187724
    Abstract: The invention relates to a temperature compensated micromechanical resonator and method of manufacturing thereof. The resonator comprises a resonator element comprising a semiconductor crystal structure, which is doped so as to reduce its temperature coefficient of frequency, transducer means for exciting to the resonator element a vibrational mode. According to the invention the crystal orientation and shape of the resonator element are chosen to allow for a shear mode having a saddle point to be excited to the resonator element, and said transducer means are adapted to excite said shear mode to the resonator element. Accurate micromechanical resonators with now temperature drift can be achieved by means of the invention.
    Type: Application
    Filed: August 11, 2011
    Publication date: July 25, 2013
    Applicant: TEKNOLOGIAN TUTKIMUSKESKUS VTT
    Inventors: Antti Jaakkola, Tuomas Pensala
  • Publication number: 20130181110
    Abstract: Technologies generally described herein relate to multilayer circuit boards with optical vias for data transmission between the layers. One or more regions may be created on a multilayer circuit board for optical vias. A transparent conducting oxide (TCO) layer can be deposited on a top and/or bottom layer of the circuit board. P-N junctions can be created over the TCO layer about the one or more regions to form optical vias as photo-emitting and/or photo-detecting components. The photo-emitting and/or photo-detecting components may be coupled to electronic components on the multilayer circuit board.
    Type: Application
    Filed: October 7, 2010
    Publication date: July 18, 2013
    Applicant: Empire Technology Development LLC
    Inventor: Michael Sievers
  • Publication number: 20130178017
    Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.
    Type: Application
    Filed: March 4, 2013
    Publication date: July 11, 2013
    Applicant: STMicroelectronics (Tours) SAS
    Inventor: STMicroelectronics (Tours) SAS
  • Publication number: 20130167338
    Abstract: Disclosed herein is a device for reducing noise generated by an electrical component, the device including a stiffening component secured to an electrical component, wherein the stiffening component provides rigidity to the electrical component, thereby reducing the mechanical resonance of the electrical component during operation. The electrical component has at least one end face and a flange portion that includes a flange face that extends about a perimeter of the end face. The flange face is substantially parallel to the end face, wherein the stiffening component is secured to the flange face of the electrical component such that it does not extend into a plane of the end face. Further, the stiffening component can include a stiffening portion and a securing portion, wherein the stiffening portion is secured to the flange face of the electrical component by the securing portion. Further, the electrical component can be a power semiconductor device.
    Type: Application
    Filed: October 5, 2012
    Publication date: July 4, 2013
    Applicant: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventor: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
  • Publication number: 20130167339
    Abstract: A device manufacturing method and a device manufacturing apparatus in a single wafer processing system with wafers in 0.5 inch size. A large number of sealed-type unit process apparatuses are arranged to form a manufacturing line. The unit process apparatus is portable and processes a single process in the manufacturing process. When the number of a unit of manufacturing is more than the number of the unit process apparatuses, the unit process apparatuses are arranged as a flow shop system, corresponding to the order of processes for the device. When the number of the units is nearly equal to the number of processes, the apparatuses are arranged as a class shop system for classified arrangement at every major division of orders of processes. When the number of the units is far less than the number of processes, the apparatuses are arranged as a multicell shop system.
    Type: Application
    Filed: August 30, 2011
    Publication date: July 4, 2013
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro Hara, Satoshi Haraichi, Akira Ishibashi
  • Publication number: 20130160260
    Abstract: A device and method for processing wafer-shaped articles comprises a process chamber and a rotary chuck located within the process chamber. The rotary chuck is adapted to be driven without physical contact through a magnetic bearing. The rotary chuck comprises a series of gripping pins adapted to hold a wafer shaped article in a position depending downwardly from the rotary chuck. The rotary chuck further comprises a plate that rotates together with the rotary chuck. The plate is positioned above an area occupied by the wafer-shaped article, and shields upper surfaces of the process chamber from liquids flung off of a wafer-shaped article during use of the rotary chuck.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Applicant: LAM RESEARCH AG
    Inventors: Dieter Frank, Robert Rogatschnig, Andreas Gleissner
  • Publication number: 20130164939
    Abstract: Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which a second area of the semiconductor wafer can rest, wherein the second surface area protrudes with respect to the first surface area.
    Type: Application
    Filed: February 22, 2013
    Publication date: June 27, 2013
    Applicant: Infineon Technologies AG
    Inventor: Infineon Technologies AG
  • Publication number: 20130160261
    Abstract: The present invention provides an apparatus for manufacturing semiconductor wafer comprising at least two manipulators, at least one set of chemical gas/liquid distribution unit and an air circulating and filtering unit. The air circulating and filtering unit is separated into three regions, including the front region, the middle region, and the side region, which are controlled by respective control electric motors to achieve uniform air flow and uniform pressure in the respective regions. The cleaning degree in the internal of the apparatus can be improved by the regional control of the air circulating and filtering unit; the wafer transport efficiency can be enhanced by the double-armed manipulators having multiple degrees of freedom; and the product yield per unit area can be increased by the chemical gas/liquid distribution unit providing stable and uniform gas/liquid flow and pressure.
    Type: Application
    Filed: June 13, 2012
    Publication date: June 27, 2013
    Applicant: BEIJING SEVENSTAR ELECTRONICS CO.,LTD.
    Inventors: Hongyu Zhao, Xiaohong Zhang, Likun Pei, Bao Zhang, Ruiting Wang
  • Patent number: 8470389
    Abstract: Provided is a method of manufacturing a solid electrolytic capacitor, including the steps of: forming a capacitor element including an anode body having a dielectric coating film on a surface thereof; impregnating the capacitor element with a polymerization liquid containing a precursor monomer of a conductive polymer and an oxidant; impregnating the capacitor element impregnated with the polymerization liquid with a silane compound or a silane compound containing solution; and forming a conductive polymer layer by polymerizing the precursor monomer after impregnating the capacitor element with the silane compound or the silane compound containing solution.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: June 25, 2013
    Assignees: SANYO Electric Co., Ltd., SAGA SANYO INDUSTRIES Co., Ltd.
    Inventors: Takeshi Furukawa, Yuichiro Inutsuka
  • Publication number: 20130152349
    Abstract: There is disclosed a method for making a nano-composite gas sensor. At first, there is provided a substrate. Then, electrodes are provided on the substrate in an array. Finally, a gas-sensing membrane is provided on the electrodes. The gas-sensing membrane includes a nano-conductive film and a peptide film.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Chung-Shan Institute of Science and Technology, Armaments, Bureau, Ministry of National Defense
    Inventors: Li-Chun Wang, Tseng-Hsiung Su, Shang-Ren Yang, Cheng-Long Ho, Han-Wen Kuo, Kea-Tiong Tang
  • Publication number: 20130154748
    Abstract: An apparatus (20) for use as an amplifier has a transistor (26) for providing signal amplification, a heat pipe or circulated fluid heat sink (22) and a thermal interface device (24) for providing mechanical and thermal connection between the transistor (26) and the heat sink (22). In use, to facilitate efficient transfer of heat/thermal energy from the transistor (26) to the heat sink (22), the plate (24) is provided between the heat sink (22) and the transistor (26). The plate (24) connects the heat sink (22) to the transistor (26) and provides a thermal conduit therebetween.
    Type: Application
    Filed: July 15, 2011
    Publication date: June 20, 2013
    Applicant: EMBLATION LIMITED
    Inventors: Gary Beale, Eamon McErlean
  • Publication number: 20130153277
    Abstract: An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed.
    Type: Application
    Filed: March 22, 2011
    Publication date: June 20, 2013
    Inventors: Etienne Menard, Christopher Bower, Matthew Meitl, Philip Garrou