Abstract: Apparatus and associated methods relate to implementing an auto-inductance-detection architecture to reconstruct current monitor output (IMON) when a low-side switch in a power stage is on. In an illustrative example, an IMON generation circuit may include a variable resistor. A close loop control (e.g., OTA, switches, and variable resistor) may be configured to adjust a resistance value of the variable resistor automatically. The IMON generation circuit may also include a low pass filter coupled to a switching node of the power stage to receive a corresponding signal and provide a DC value. The difference between the corresponding signal and the DC value may be configured to enable or disable the close loop control. By providing the close loop control, the IMON generation circuit may advantageously perform auto-inductance detection (AID) and provide a more accurate IMON reconstruction method.

Abstract: In one form, a multiphase controller for controlling a plurality of phases using a corresponding plurality of phase controllers includes a plurality of inputs, each for receiving a respective current monitor signal, an averaging circuit for generating an averaged signal representative of an average of current monitor signals received from said plurality of inputs, wherein each phase controller generates an error voltage in response to said averaged signal and said respective current monitor signal, controls a drive signal in response to said error voltage and a control voltage, and provides a digital signal representative of a difference between said error voltage and said control voltage. The multiphase controller provides an adjustment signal representative of said digital signal divided by a corresponding output current for each phase controller, and said adjustment signal adjusts a corresponding error voltage.

Abstract: A photomultiplier pixel cell includes a photon detector coupled to detect an incident photon. A quenching circuit is coupled to quench an avalanche current in the photon detector. An enable circuit is coupled to the photon detector to enable and disable the photon detector in response to an enable signal. A buffer circuit is coupled to the photon detector to generate a digital output signal having a pulse width interval in response to the avalanche current triggered in the photon detector. A first one of a plurality of inputs of a digital-to-analog converter is coupled to the buffer circuit to receive a digital output signal. The digital-to-analog converter is coupled to generate an analog output signal having a magnitude that is responsive to a total number of digital output signals received concurrently within the pulse width interval at each one of the plurality of inputs of the digital-to-analog converter.

Abstract: An apparatus comprises a rectifier configured to convert an alternating current voltage into a direct current voltage, wherein the alternating current voltage is generated by a receiver coil configured to be magnetically coupled to a transmitter coil of a wireless power transfer system, a high efficiency power converter connected to the rectifier, the high efficiency power converter comprising a first stage and a second stage connected in cascade and a controller configured to detect a plurality of operating parameters and generate a control signal applied to a control loop of the first stage.

Abstract: A current balance circuit including a current sensing front end for sensing an output signal from each of a plurality of switching regulators and a current sensor for receiving the sensed output signal and converting the sensed signal into a sensed current signal. The current balance circuit further includes a current averaging circuit for receiving the sensed output signals and determining an average current output for the plurality of switching regulators and a current difference circuit for receiving the average current value and the sensed current signals and determining a current difference for each of the plurality of switching regulators. A calibration circuit is included for receiving the current differences and calculating a calibration value corresponding to each of the plurality of switching regulators which provides an indication of how to adjust a current output of the plurality of switching regulators to balance the current across the plurality of switching regulators.

Abstract: An interleaved power converter includes a control circuit and multiple phase-shifted subconverters each having at least one power switch. The control circuit is coupled to the subconverters for controlling the power switches to balance currents in the subconverters over multiple periods. The control circuit includes a current compensator configured to determine a first duty cycle multiple times over the multiple periods, generate a PWM control signal having a present value of the first duty cycle for controlling the power switch of one of the subconverters during a period, determine a second duty cycle based on the present value of the first duty cycle and a previous value of the first duty cycle, and generate another PWM control signal having the second duty cycle for controlling the power switch of another one of the subconverters during the period. Other example power converters and control circuits are also disclosed.

Abstract: Multi-sense point voltage regulator systems are provided for usage in conjunction with power-regulated devices, such as system-on-chip and microcontroller unit devices. In embodiments, the multi-sense point voltage regulator system includes a multiplexer selector circuit and a voltage regulator. The multiplexer selector circuit is configured to: (i) monitor a local voltages at multiple sense points within an integrated circuit (IC) die circuit structure; and (ii) generate a feedback voltage indicative of a lowest one of the monitored local voltages. The voltage regulator is configured to generate a regulated power supply output voltage as a function of a differential between the feedback voltage and the reference voltage, with the regulated power supply output voltage provided to the IC die circuit structure to drive operation thereof.

Abstract: A method of controlling a switching converter having a plurality of interleaved parallel branches, can include controlling conduction phases of power switches of the plurality of interleaved parallel branches to be overlapped when a load changes from a light load to a heavy load, in order to improve dynamic response performance of the switching converter. A control circuit for a switching converter with a plurality of interleaved parallel branches, can control conduction phases of power switches of the interleaved parallel branches to be overlapped when a load changes from a light load to a heavy load, in order to improve dynamic response performance of the switching converter.

Abstract: A power conversion system has a plurality of power tracking converters connected in parallel to an output of an energy source such as a solar system. A communication system between the converters implements a sequence of operation of the converters, such that in response to a communication signal from a preceding converter in the sequence, each converter performs tuning of its power tracking function and then provides a communication signal to the next converter in the sequence. Each converter for example functions as a maximum power point tracking system. The system may be made from a set of smaller units so that different systems may be formed from a small set of standard components. By operating the converters in a sequence, conflict between the converters and instability is avoided.

Abstract: A system includes a first input line for a first voltage source, wherein the first input line is connected to a first output. A second input line is included for a second voltage source, wherein the second input line is connected to a second output and is in parallel with the first input line. A first series pass element is connected in series with the first input line, and a second series pass element is connected in series with the second input line. A controller is operatively connected to the first series pass element and to the second series pass element to throttle at least one of the first series pass element and the second series pass element to balance output current in the first and second outputs.

Abstract: A multi-phase switch-mode power supply to control an output in two possible modes is disclosed. A first mode can be applied for normal load conditions. In the first mode, control is achieved using an error signal based on a difference between an output voltage and a set voltage level. In heavy load conditions a load attempts to draw too more power than the switch-mode power supply can provide. As a result, control of the output voltage is lost and the current of each phase becomes saturated at a limit. When this condition is detected, a second mode can be applied. In the second mode, control is achieved using an error signal based on a difference between an output current and a set current level. The set current level is chosen so that the current of each phase is no longer saturated and control of the output current is maintained.

Abstract: A power combining technique includes receiving a first voltage at a first input and a second voltage at a second input. The power combining technique further includes combining, with at least two power converters, power received from the first and second inputs into a single power rail. A power balancing technique further includes controlling the at least two power converters such that a first one of the power converters outputs an amount of current to the single power rail that is proportional to and/or equal to the amount of current output by another of the power converters.

Abstract: A power MOS stage includes a first power MOS device and a second power MOS devices connected in parallel between a first node and a second node, the first power MOS device having a first voltage rating and the second power MOS device having a second voltage rating that is lower than the first voltage rating. A driver circuit is configured to drive control nodes of the first and second power MOS devices in a sequential manner when actuating the power MOS stage by actuating the first power MOS device before actuating the second power MOS device. The control nodes of the first and second power MOS devices are further driven in a sequential manner when deactuating the power MOS stage by deactuating the second power MOS device before deactuating the first power MOS device.

Abstract: In a current equalization circuit, where a first inductor is connected to a first resistor, a second inductor is connected to both the first inductor and a second resistor, the input end of the first resistor and the input end of the second resistor are respectively connected to a first input end and a second input end of an error detection sub-circuit, a first output end of the error detection sub-circuit is connected to a first error adjustment sub-circuit, a second output end of the error detection sub-circuit is connected to a second error adjustment sub-circuit, the first error adjustment sub-circuit adjusts an input current of the first inductor based on a voltage signal from the error detection sub-circuit, and the second error adjustment sub-circuit adjusts an input current of the second inductor based on a voltage signal from the error detection sub-circuit.

Abstract: An apparatus comprises a plurality of voltage sources, one or more processors embedded with the plurality of voltage sources, and memory storing processor executable instructions that, when executed by the one or more processors, cause the apparatus to modify duty cycles of the voltage sources, and to modify timing for each phase of a multiphase cycle. In some cases, the apparatus: transfers, for each phase of the multiphase cycle, power from a different source of a plurality of sources to a load; determines, for each phase of the multiphase cycle, an input voltage associated with the transferred power, an output voltage associated with the transferred power, and current from the source associated with the transferred power; determines a duty cycle associated with the source; modifies duty cycles of the voltage sources; and modifies timing for each phase of the multiphase cycle.

Abstract: In an embodiment, a system for balancing input current for power supplies a voltage detector configured to detect an input voltage to a power supply of a plurality of different power supplies. The system further includes one or more circuit elements configured to adjust one or more properties of the one or more circuit elements based at least in part on the detected input voltage in an attempt to maintain a consistent current input across the plurality of different power supplies.

Abstract: A computer device configured to monitor control signals from more than one adjustment system indicating a need to adjust operation of at least one energy storage; convert the control signals into current values; compare the control signals and select the one with the smallest current value; and control operation of at least one control device configured to regulate the current of the energy storage based on the selection by dispatching an adjustment signal by internet based communication.

Abstract: A dual mode switching regulator includes a PWM/PFM control architecture with PFM frequency foldback based on extending switching cycle off time TOFF. A controller includes a PWM/PFM clock generator that, in response to assertion of a TOFF control signal, extends the nominal PWM switching cycle off-time TOFFnom for an extended off-time TOFFext (variable), so that switching cycle off-time is [TOFFnom+TOFFext]. A TOFF modulator generates the TOFF control signal based on generating a TOFF control voltage from an ITOFF control current equal to [IPWM-IPFM], generated by sourcing an IPWM reference current, and, in response to a PFM load condition, sinking an IPFM control current. The TOFF control signal is asserted when the TOFF control voltage is not substantially equal to a TOFF reference voltage at the end of TOFFnom, to cause the PWM/PFM clock generator to extend switching cycle off-time to [TOFFnom+TOFFext], with the duration of TOFFext determining PFM switching frequency.

Abstract: A switching regulator configured to generate a level-controlled output voltage from an input voltage, the switching regulator includes an inductor, an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor, at least two flying capacitors, and a plurality of switches configured to form electrical connections when the switching regulator operates in a first operating mode to, alternately charge each of the at least two flying capacitors using the input voltage, and provide a first boosted voltage to the inductor using a charged flying capacitor among the at least two flying capacitors.

Abstract: The present disclosure provides an alternatingly-switched parallel circuit, an integrated power module and an integrated power package. The alternatingly-switched parallel circuit includes a first bridge arm and a second bridge arm at least partly formed in a chip containing a plurality of first cell groups and a plurality of second cell groups. The plurality of first cell groups are configured to form the first upper bridge-arm switch and the plurality of second cell groups are configured to form the second upper bridge-arm switch, or the plurality of first cell groups are configured to form the first lower bridge-arm switch and the plurality of second cell groups are configured to form the second lower bridge-arm switch. The plurality of first cell groups and the plurality of second cell groups are switched on and off alternatingly.

Abstract: Provided is multi-phase interleaving control in a power supply device. In power control by the power supply device where the dead beat control is applied to the multi-phase interleaving, combined current of the multi-phase current values is used as control current in the multi-phase control based on the multi-phase interleaving, thereby achieving control independent of the number of the detectors and the control system independent of the number of phases, and further, this control current is used to perform constant current control, so as to prevent overshooting and undershooting. The power supply device has multi-phase interleaving control that performs multi-phase control using a plurality of phase current values, provided with an LC chopper circuit constituting a step-down chopper circuit that operates according to the multi-phase control of multi-phase interleaving, and a controller for performing step response control according to the multi-phase control of the LC chopper circuit.

Abstract: A DC-DC power converter including switched inductance circuits arranged in parallel is described. Operation includes determining a commanded current and activation commands for the switched inductance circuits based upon the commanded current. This includes executing the activation commands and monitoring current in the switched inductance circuits. An average measured current is determined for each of the switched inductance circuits, and a modified activation command is determined for each of the switched inductance circuits based upon the average measured current. A time portion of the modified activation command that exceeds an end time point of a subsequent time period is determined, and the modified activation commands for the switched inductance circuits are executed, including forward-shifting that time portion of the modified activation command for each of the switched inductance circuits that exceeds the end time point.

Abstract: A phase-redundant voltage regulator can include multiple regulator phases connected in parallel between a common regulator input and a common regulator output. Each regulator phase includes a voltage regulator that receives an input voltage and drives a respective output voltage. The voltage regulator also includes a plurality of linear regulators, each having a linear ORing device electrically connected between the regulator output of a respective regulator and an output of the linear regulator. The voltage regulator also includes an amplifier having inputs electrically connected to a remote voltage sense input and to a reference voltage input. An output of the voltage regulator is electrically connected to an input of the linear ORing device. The amplifier controls the linear ORing device to drive a voltage on the output of the linear regulator equivalent to a voltage on the reference voltage input.

Abstract: A voltage regulator circuit included in a computer system may include multiple phase circuits each coupled to a regulated power supply node via a corresponding inductor. The phase circuits may modify a voltage level of the regulated power supply node using respective control signals generated by a digital control circuit that processes multiple data bits. An analog-to-digital converter circuit may compare the voltage level of the regulated power supply node to multiple reference voltage levels and sample the resultant comparisons to generate the multiple data bits.

Abstract: An autozeroed comparator controls a frequency fsw of the input voltage inputted to a DC/DC converter. A digital frequency synchronization circuit is connected to the autozeroed comparator so as to form a phase locked loop, wherein the DES circuit controls the hysteretic window of the autozeroed comparator so as to lock fsw to a clock reference frequency. A plurality of slave phase circuits may be connected to the master phase circuit including the DFS circuit and the autozeroed comparator. Duty cycle calibration circuits adjust a duty cycle signal applied to each of the slave phase circuits, in response to average current measured in the slave phase circuits, so that each slave phase circuit is synchronized with the master phase circuit. A 6 A 90.5% peak efficiency 4-phase hysteretic quasi-current-mode buck converter is provided with constant frequency and maximum ±1.5% current mismatch between the slave phases and the master phase.

Abstract: An accelerating discharge device includes a first parallel inductive element, a second parallel inductive element, a first capacitor, a noise suppression element, a one-way element, a first discharge circuit, a second discharge circuit, a first switch element, and a second switch element. The first parallel inductive element generates a first control voltage according to a first input voltage. The second parallel inductive element generates a second control voltage according to a second input voltage. The first switch element selectively couples the first parallel inductive element through the second discharge circuit to a ground according to the first control voltage. The second switch element selectively couples the second parallel inductive element through the second discharge circuit to the ground according to the second control voltage.

Abstract: Provided is a power circuit in which a first input terminal is connected to a first end of a second inductor, a second end of the second inductor is connected to a first end of a first reactor, the second end of the second inductor is connected to a first end of a second reactor, the first input terminal is connected to a first end of a first inductor, a second end of the first inductor is connected to a first end of a bypass capacitor, a second end of the bypass capacitor is connected to a second output terminal, the first inductor and the second inductor are magnetically coupled to each other, and a control circuit performs switching control over first and second switching elements, using an interleaving method.

Abstract: A voltage converter circuit comprises a charge pump circuit, a pulse width modulation (PWM) filter stage circuit, and a control circuit. The charge pump circuit includes multiple switching transistors arranged as a switching bridge including a first bridge portion connected to a second bridge portion; a midpoint capacitor connected to a circuit node coupling the first bridge portion and the second bridge portion; and a first flying capacitor coupled to the first bridge portion and the second bridge portion. The PWM filter stage circuit is coupled to the charge pump circuit and a first input/output terminal and includes a first inductor coupled to the first flying capacitor and the second bridge portion of the switching bridge. The control circuit is configured to control activation of switching transistors of the switching bridge to generate a regulated voltage at the first input/output terminal.

Abstract: A voltage conversion apparatus includes a power supply circuit with a first switch, a voltage conversion circuit, and a protective circuit with a detection circuit. The first switch transmits a power to generate an input voltage. The voltage conversion circuit generates a first voltage. A second switch of the voltage conversion circuit receives the input voltage. A third switch of the voltage conversion circuit is coupled between the second switch and a ground terminal. The detection circuit generates a first control signal based on the first voltage, a second voltage that corresponds to the first voltage, and a reference voltage. When a voltage value of an error signal is less than the reference voltage, the detection circuit outputs the first control signal to turn off the first switch. The voltage value of the error signal corresponds to a voltage difference between the first voltage and the second voltage.

Abstract: A switching control circuit for controlling a multi-channel switching circuit having switching circuits, input terminals coupled to input voltage signals, and an output terminal for providing an output voltage signal, can include: a logic control circuit configured to receive an external operation signal and a first single pulse signal, and to generate an enable signal, a trigger signal, and feedback control signals; a reference voltage regulation circuit configured to receive the enable signal, the trigger signal, and a maximum one of the input voltage signals, and to generate a reference voltage signal; and feedback circuits corresponding to the switching circuits, where the plurality of feedback circuits are configured to receive the feedback control signals, a minimum one of two input voltage signals that are participating in the switching operation, the reference voltage signal, and the output voltage signal, and to generate switching control signals for controlling the switching circuits.

Abstract: Provided is a power supply circuit in which a first input terminal is connected to a first end of a first reactor, the first input terminal is connected to a first end of a second reactor, a first end of a first inductor is connected the first input terminal, a second end of the first inductor is connected to a first end of a second inductor, a second end of the second inductor is connected to a first end of a bypass capacitor, a second end of the bypass capacitor is connected to a second output terminal, the first reactor and the first inductor are magnetically coupled to each other, the second reactor and the second inductor are magnetically coupled to each other, and a control circuit performs switching control over first and second switching elements, using an interleaving method.

Abstract: Current regulating techniques utilizing buck-boost circuitries are disclosed. A buck switching device is used in an input stage of a buck-boost circuitry of some embodiments for regulating an input current thereof, and a boost switching device is used in an output stage thereof. A control system is used to set the buck switching device into a closed state at a beginning of each cycle of a periodic timing signal, and open the buck switching device to cause the input current to converge towards a defined target current value, while an unrelated controller changes in each cycle the boost switching device into an open state based on an input/output dependent force-on duty cycle value, and thereafter change the boost switching device back into the closed state whenever the output current of the boost circuit drops below a determined threshold current value.

Abstract: A semiconductor device has a drive transistor coupled to a load and a current detection circuit. The current detection circuit includes: an operational amplifier amplifying a potential difference between voltage of a first terminal and voltage of a second terminal; a sense transistor passing sense current between the first terminal and the drive transistor; a voltage supply circuit having a first current source and supplying voltage higher than voltage supplied to the grounding voltage terminal to the second terminal; a third terminal outputting current based on the sense current; a second current source coupled between the third terminal and the grounding voltage terminal; and a current source control circuit controlling current of the first and second current sources. Detection current detected by the current detection circuit is current obtained by subtracting the current of the second current source from the current based on the sense current.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a signal supply controller to supply a signal, which allows a level of a resistance value of one of the first and second switching elements to be a predetermined level, to the elements via shared signal wire, and to set a current flowing through the higher-potential side terminal in the one of the first and second switching elements to a value which causes the level of the resistance value to be the predetermined level. In a state where the level of the resistance value of the one of the first and second switching elements is set to the predetermined level, another of the first and second switching elements is brought into a conducting state.

Abstract: A power converter, a control circuit and a control method for the same. Ground references of a first controller and a second controller are different to isolate drive signals of a first transistor and a second transistor. Thus the first transistor and the second transistor are controlled to be switched between on and off alternatively to achieve power conversion. The circuit is simple in structure and easy to implement with a low cost. The ground reference of the first controller is an intermediate node of a bridge arm of the power converter, so as to facilitate sampling and acquiring a feedback signal, thereby achieving closed-loop control of the power converter.

Abstract: A testing device includes a switch, a sensing circuit, and a control circuit. The switch is coupled to a power supply circuit, and the power supply circuit is configured to output a supply voltage to a device under-test via the switch. The sensing circuit is coupled to the device under-test, and the sensing circuit is configured to receive an input voltage from the device under-test and to output a sensing signal according to the input voltage. The control circuit is coupled to the sensing circuit, the power supply circuit, and the switch. The control circuit is configured to control the power supply circuit to stop outputting the supply voltage at a first time and to turn off the switch at a second time according to the sensing signal.

Abstract: A power source switching circuit for powering an electronic component includes a soft-start circuit, a first input connected to a standby power source, a second input connected to a main power source, and an output. The output provides a voltage to the electronic component and is configured to be alternatively electrically connected to the first input or the second input. When the power source switching circuit is in a standby mode, the output is connected to the first input and the standby power source. When the power source switching circuit is in a main mode, the output is connected to the second input and the main power source. When the power source switching circuit is initially activated to the standby mode, the soft-start circuit is enabled. When the power source switching circuit subsequently switched from the main mode to the standby mode, the soft-start circuit is disabled.

Abstract: A controller for a multi-phase switching regulator includes an error amplifier configured to generate an error signal indicative of the difference between a feedback voltage and a reference voltage; a loop calculator configured to generate control signals in response to the error signal to drive the power stages; and a dynamic phase management control circuit configured to generate a power efficiency value in response to the input current, the input voltage, the output current, and the output voltage. The dynamic phase management control circuit generates a phase selection signal indicating a first number of power stages to be activated in response to the first current signal and the power efficiency value. The phase selection signal is provided to the loop calculator to activate the first number of power stages.

Abstract: Implementations of voltage sensing systems may include: a high side current mirror coupled to a reference current source coupled to at least one diode. The at least one diode may be coupled to a resistor and to a comparator. The resistor may be coupled to the ground. The comparator may be coupled with a reference voltage. The comparator may be configured to receive a comparison voltage from the diode and output whether the comparison voltage is higher or lower than the reference voltage.

Abstract: A system and method of wireless power transfer using a power converter with a bypass mode includes a power converter. The power converter includes a pulsed switch, a capacitor configured to supply a drive voltage to the pulsed switch, a first circuit configured to charge the capacitor when the power converter operates in a switched mode of operation, and, a second circuit configured to charge the capacitor when the power converter operates in a bypass mode of operation.

Abstract: A multi-phase DC-DC power converter includes an error amplifier, a comparator, a phase selection circuit, a plurality of phase circuits and a width detecting circuit. The plurality of phase circuits are each associated with a phase of the multi-phase DC-DC power converter, each including a turn-on clock generation circuit, a first switching transistor, a second switching transistor, an output inductor, and a control logic. In a load transition state, when the width detecting circuit detects that a comparison output signal exceeds a predetermined width, the phase selection circuit adjusts one of the plurality of phase signals based on a force trigger signal, and outputs, corresponding to a force trigger signal, one of the plurality of on-signals.

Abstract: A diagnostic system is provided. A first monitoring application sets a first voltage regulator status flag equal to a first fault value when a first voltage value is greater than a first maximum voltage value. A first diagnostic handler application transitions each of a high voltage switch and a low voltage switch to an open operational state when the first voltage regulator status flag is equal to the first fault value. A second monitoring application sets a second voltage regulator status flag equal to a second fault value when the second voltage value is less than a first minimum voltage value. A second diagnostic handler application transitions the high voltage switch and the low voltage switch to the open operational state when the second voltage regulator status flag is equal to the second fault value.

Abstract: The invention relates to control of a DC converter having multiple parallel-connected DC converter modules. Here, a common variable for the voltage control is formed for the control of all the DC converter modules. In addition, a separate current controller is provided for each DC converter module. For each DC converter module, a control variable can be formed from the individually determined current control and the jointly determined voltage control.

Abstract: The disclosure discloses a power conversion device and a power conversion system. The power conversion device comprises a plurality of conversion branches, each comprising an input terminal and an output terminal. The input terminals of the plurality of conversion branches are connected in parallel, and the output terminals of the plurality of conversion branches are connected in series. An output voltage of the power conversion device is a sum of voltages at the output terminals of the plurality of conversion branches.

Abstract: A control circuit of a multi-phase converter can include: an inductor current sampling circuit configured to generate a plurality of sampling signals corresponding to a plurality of channels of the multi-phase converter, where each of the sampling signals characterizes an inductor current of a corresponding channel; an error circuit configured to generate a plurality of error signals corresponding to the plurality of channels, where each of the error signals characterizes an error between the inductor current of the corresponding channel and a reference current; and a modified circuit configured to modify the sampling signals of the corresponding channels according to the plurality of error signals to generate a plurality of modified sampling signals, where the control circuit balances the inductor currents between the plurality of channels according to the plurality of modified sampling signals.

Abstract: A DC-DC converting controller is disclosed. The DC-DC controller includes a current sensing unit, a parameter setting pin, a parameter setting unit and an error amplifier. The current sensing unit provides a sensing current. The parameter setting pin is coupled to an external parameter setting unit. The parameter setting unit is coupled to the current sensing unit and the parameter setting pin. The parameter setting unit has an internal parameter setting unit. The parameter setting unit generates a droop current according to the external parameter setting unit and the sensing current. The error amplifier includes a first input terminal and a second input terminal. The first input terminal receives an output feedback voltage and the second input terminal receives a first reference voltage. The second input terminal is coupled to a terminal of the internal parameter setting unit.

Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

Abstract: The present invention proposes a hybrid converter branch operating mode for a Modular Multilevel power Converter MMC with MMC cells in distinct subsets operating according to a “pulse blocked” cell operation mode with DC cell voltage increase or according to a “bypass” cell operation mode without DC cell voltage increase. Repeated cell subset assignment and corresponding alternation of cell operating mode allows to reduce or at least manage a mean deviation of the cell capacitor DC voltages of the converter cells. The invention also reduces no-load losses of the MMC in standby mode and a charging voltage in an MMC charging mode.

Abstract: A load control device for regulating an average magnitude of a load current conducted through an electrical load may operate in different modes. The load control device may comprise a control circuit configured to activate an inverter circuit during an active state period and deactivate the inverter circuit during an inactive state period. In one mode, the control circuit may adjust the average magnitude of the load current by adjusting the inactive state period while keeping the active state period constant. In another mode, the control circuit may adjust the average magnitude of the load current by adjusting the active state period while keeping the inactive state period constant. In yet another mode, the control circuit may keep a duty cycle of the inverter circuit constant and regulate the average magnitude of the load current by adjusting a target load current conducted through the electrical load.

Abstract: An apparatus for determining the occurrence of a leakage current between a series connected electrochemical battery cells, comprising: a first cell connection terminal for connection to a first cell's first terminal via first filter circuitry; a second cell connection terminal for connection, via second filter circuitry, to a connection between the first cell's second terminal and a second cell's first terminal, the first and second cell adjacent in the series arrangement; a first cell balancing terminal for connection to the first cell's first terminal bypassing the first filter circuitry; a second cell balancing terminal for connection to the connection between the first cell's second terminal and the second cell's first cell terminal; balancing circuitry for providing a connection between the cell balancing terminals; the apparatus configured to provide for identification of a leakage current based at least on a voltage between the cell connection terminals and the cell balancing terminals.