Abstract: An analog circuit arrangement (1) to variably set a voltage Uout, within defined voltage limits, has a non-inverting adder (10) with a positive input (11). A voltage divider (20), with at least a first stage (21) and a second stage (22), is connected to the positive input (11) of the adder (10). At least one stage has a parallel circuit of n resistors (R1, R2, . . . , Rn) that are each connected in series in a conduction path (L1, L2, . . . , Ln) to an overcurrent protection device (F1, F2, . . . , Fn). At least one device (30) actively changes one or more of the overcurrent protection devices (F1, F2, . . . , Fn) into a state that interrupts the respective affected conduction path (L1, L2, . . . , Ln).

Abstract: A power converter includes a switched-capacitor circuit that forms different capacitor networks out of a set of capacitors. It does so in a way that avoids losses that can arise when capacitors are connected together.

Abstract: A semiconductor device includes a first transistor; a first resistor; a second resistor; a first circuit configured to apply a first voltage to the first transistor. The first voltage is based on a difference between a reference voltage and an output voltage divided by the first and second resistors. A first current through the first circuit in a first mode is less than a second current through the first circuit in a second mode. The semiconductor device includes a capacitor connected to the output terminal; and a second circuit connected to the capacitor that: (a) disconnects the first circuit from the capacitor and apply a second voltage to the capacitor in a first mode, and (b) electrically connects the first circuit to the capacitor in the second mode.

Abstract: Disclosed is an integrated user programmable slew-rate controlled soft-start for a low-dropout regulator that includes a current steering stage and an integrator stage. The current steering stage may also be denoted as an error amplifier. A Miller compensation capacitor couples between an input node to the integrator stage and an output node for an output voltage of LDO. During a power up period of the LDO, the current steering stage generates an input current that charges the Miller compensation capacitor. This controlled charging of the Miller compensation capacitor controls the slew rate of the output voltage as it rises to its regulated value at a completion of the power up period.

Abstract: A voltage regulator circuit can include two feedback loops, such as to reduce or suppress an unwanted transient condition in an output voltage during transient conditions such as during startup or during load current demand transients. One of the two feedback loops can include a shunt device arranged to provide a temporary current pathway during the transient condition to change current provided to a load connected to an output of the voltage regulation circuit. In addition, or instead, the voltage regulator circuit can include an open-loop regulation circuit separate from a loop corresponding to the first error amplifier. The open-loop regulator circuit can operate in a lower-power mode as compared to a closed-loop regulator circuit. A portion or an entirety of the voltage regulator circuit can be implemented in an integrated circuit, such as monolithically.

Abstract: A magnetic junction memory device is provided. The magnetic junction memory device including a sensing circuit including a sensing node, the sensing node being connected to a first end of a transistor and configured to change a voltage of the sensing node in accordance with a resistance of a magnetic junction memory cell, a gating voltage generator circuit configured to generate a gating voltage of the transistor using a reference resistor and a reference voltage, and a read circuit configured to read data from the magnetic junction memory cell using the reference voltage and the voltage of the sensing node.

Abstract: A low-dropout voltage regulator is provided. The low-dropout voltage regulator includes a differential amplifier pair, a secondary amplification circuit that is self-stabilized, an output circuit, and a frequency compensation circuit. The secondary amplification circuit includes a first amplification transistor and a second amplification transistor. The first amplification transistor includes a first terminal, a second terminal, and a third terminal. The second amplification transistor includes a first terminal, a second terminal, and a third terminal. The second terminal of the first amplification transistor is electrically connected to the second terminal of the second amplification transistor to form an input terminal of the secondary amplification circuit to be connected to an output terminal of the differential amplifier pair.

Abstract: A low drop-out (LDO) linear regulator includes: a pass transistor coupled between an input terminal and an output terminal; an error amplifier suitable for amplifying and outputting a difference between a feedback voltage corresponding to an output voltage of the output terminal and a predetermined reference voltage; a buffer including an input terminal which is coupled to an output node of the error amplifier and an output terminal which is coupled to a gate of the pass transistor; a first compensation circuit suitable for driving an equivalent resistance of the output node of the error amplifier to be in inverse proportion to a load current; and a second compensation circuit suitable for driving an equivalent resistance of an output node of the buffer to be in inverse proportion to the load current.

Abstract: An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.

Abstract: A method for regulating a voltage reference signal includes providing a first output current during a first interval and a boosted output current during a second interval to generate a low-dropout voltage reference signal based on a first power supply voltage, a second power supply voltage, and a reference voltage level. The method includes, during the second interval, compensating for a voltage drop caused by providing the boosted output current. The first output current may be provided in a first mode of operation. The boosted output current and voltage drop compensation may be provided in a boosted mode of operation.

Abstract: The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.

Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.

Abstract: Power supply noise reduction methods and low drop out (LDO) voltage regulators with capacitively coupled supply noise-reducing components are disclosed. One illustrative voltage regulator includes: a pass transistor having an n-type conduction channel that couples a supply voltage to an output node; an operational amplifier that derives a control signal for the pass transistor from a difference between a reference voltage and a scaled or unscaled voltage of the output node, the control signal being supplied to a gate or base of the pass transistor; a buffer that derives a ripple cancellation signal from the supply voltage; and a coupling capacitor that couples the buffer to the base or gate of the pass transistor to impose the ripple cancellation signal on the control signal.

Abstract: In an example, an apparatus includes an error amplifier, a buffer, a transistor, and a current-mode feedforward ripple canceller (CFFRC). The error amplifier has an amplifier output, a first input, and a second input, the error amplifier second input configured to receive a reference voltage. The buffer has a buffer input and a buffer output, the buffer input coupled to the error amplifier output. The transistor has a gate, a source, and a drain, the gate coupled to the buffer output, the drain coupled to the first input. The transistor is configured to receive an input voltage (VIN) at the source and provide an output voltage at the drain. The CFFRC has a CFFRC input and a CFFRC output, the CFFRC output coupled to the gate, and the CFFRC input configured to receive VIN.

Abstract: Circuitry for ultrasound devices is described. A multilevel pulser is described, which can provide bipolar pulses of multiple levels. The multilevel pulser includes a pulsing circuit and pulser and feedback circuit. Symmetric switches are also described. The symmetric switches can be positioned as inputs to ultrasound receiving circuitry to block signals from the receiving circuitry.

Abstract: Systems and methods are provided for controlling power down of an overdrive low drop out regulator circuits. The system is designed with a low dropout regulator circuit configured to operate in a safe operating area range of operation with very low current. The circuit contains a regulator, a current boost, and a power down switch. The current boost is responsive to a power down signal, generally from a power distribution board. The circuit is fabricated such that the low dropout regulator circuit with the current boost operates with minimum current pull while maintaining safe operating area range of operation. The safe operating area range of operation is maintained during various design operations, normal operations, and power down. This regulator circuit may be designed without a middle level voltage or high-ground.

Abstract: One or more sampling parameters of an application associated with a downstream voltage regulator may be determined. A power supply rejection ratio (“PSRR”) and a switching frequency of an upstream voltage regulator may be dynamically adjusted based on the sampling parameters of the application associated with the downstream voltage regulator. The sampling parameters may include a noise level and a workload of the selected application.

Abstract: A motor controller circuit having a stable speed controlling mechanism is provided. A duty cycle determining circuit determines duty cycles of the plurality of waveforms respectively of the first waveform signals within each of a plurality of time intervals to output a duty cycle instructing signal, according to a target working period corresponding to a target rotational speed. A signal generating circuit outputs the plurality of first waveform signals according to the duty cycle instructing signal, and outputs a second waveform signal. A motor control circuit outputs a plurality of on-time signals according to the plurality of first waveform signals and the second waveform signal. A motor driving circuit is controlled to operate and drive a motor to rotate according to the plurality of on-time signals.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first device die and a second device die. The first device die includes first bonding pads at a front surface of the first device die. The second device die is bonded on the first device die, and includes die regions and a scribe line region connecting the die regions with one another. The die regions respectively comprise second bonding pads at a front surface of the second device die. The second bonding pads are respectively in contact with one of the first bonding pads.

Abstract: According to one embodiment, a constant voltage circuit includes: a first gain stage that outputting a first voltage amplifying a difference voltage between a divided voltage of an output voltage and a reference voltage; a second gain stage outputting a second voltage amplifying the first voltage; a second transistor, one end of which is coupled to the input voltage terminal, and other end of which is coupled to an output voltage terminal, controlling the output voltage to be constant in accordance with the second voltage applied to the gate; and a first circuit selecting one of a first operation mode and a second operation mode. When the first operation mode is selected, a first current flows to the first node, and when the second operation mode is selected, a second current flows to the first node.

Abstract: A second semiconductor switching element is connected in series with a first semiconductor switching element, and is at least partially stacked on the first semiconductor switching element in the thickness direction. A first control element controls the first semiconductor switching element and the second semiconductor switching element, and performs an overcurrent protection operation with reference to a shunt voltage. The first control element is arranged outside the first semiconductor switching element and the second semiconductor switching element in the in-plane direction.

Abstract: A power supply circuit, includes: an N-channel depletion type output transistor connected between an input terminal of an input voltage and an output terminal of an output voltage; and an operational amplifier configured to control a gate of the output transistor so that a feedback voltage corresponding to the output voltage matches a reference voltage.

Abstract: A voltage regulator and a corresponding method of regulating a voltage are presented. The voltage regulator includes an N-type power switch, an error amplifier, and a switch capacitor circuit. The switch capacitor circuit includes a first capacitor coupled to a network of switches, the switch capacitor circuit has a first port coupled to an output the error amplifier, a second port coupled to an output terminal of the power switch, and a third port coupled to a control terminal of the power switch. The switch capacitor circuit is iteratively operable between a first phase and a second phase. In the first phase the first port is coupled to ground via a path comprising the first capacitor, and in the second phase the second port is coupled to the third port via a path comprising the first capacitor. The voltage regulator may be implemented as a low dropout regulator.

Abstract: A voltage regulator is provided. The voltage regulator includes a level shifter, a low-pass filter, and a voltage regulating circuit. The level shifter shifts a voltage value of a reference voltage signal to generate a set voltage signal. The low-pass filter filters the set voltage signal to generate a filtered voltage signal. The voltage regulating circuit outputs an output voltage signal according to the filtered voltage signal and adjusts a voltage value of the filtered voltage signal according to a change of the output voltage signal to stabilize a voltage value of the output voltage signal.

Abstract: A voltage regulator that includes a first amplifier, a second amplifier, a summer, and a transistor is presented. The first amplifier has a first gain and a first frequency bandwidth, and is configured to generate a first voltage output. The second amplifier has a second gain that is lower than the first gain and a second frequency bandwidth that is higher than the first frequency bandwidth, and is configured to generate a second voltage output. The summer is configured to generate a summed voltage output. The transistor is connected to the summer and configured to generate a regulated voltage based on the summed voltage output of the summer.

Abstract: The present disclosure describes systems and methods for identifying defective components in a power integrated circuit. In one such system, a voltage regulator circuit is embedded in an integrated circuit device, wherein the voltage regulator circuit includes a control feedback loop having a compensation capacitor that is configured to maintain a stable output voltage of the voltage regulator voltage at a set value or range. Additionally, a test circuitry is embedded in the integrated circuit device, wherein the test circuitry comprises a voltage source that is configured to generate a cyclical test input signal that passes through the control feedback loop. Accordingly, the test circuitry is configured to provide a test output signal to an output pin of the integrated circuit device that indicates a performance level of the compensation capacitor in the control feedback loop of the voltage regulator circuit. Other systems and methods are also included.

Abstract: A regulator circuit according to one embodiment includes a first transistor, a filter, and a differential amplifier. The first transistor is provided between an input terminal on a power supply side and an output terminal on an output side. The differential amplifier includes an output node connected to the first transistor, and controls the first transistor on the basis of a result of comparison between a reference voltage and a feedback voltage according to an output voltage applied to the output terminal. The filter is connected to a control node that makes a differential pair with the output node, in the differential amplifier.

Abstract: In a transistor turnoff system, a transistor control circuit is configured to adjust a control voltage at a transistor control output responsive to a comparison signal at a control input. The control voltage has a slew rate. A comparator has a comparator output and first and second comparator inputs. The first comparator input is coupled to the transistor control output. The comparator is configured to: provide the comparison signal at the comparator output based on a reference voltage at the second comparator input; and deactivate the transistor control circuit by changing a state of the comparison signal responsive to the control voltage falling below the reference voltage. A slew-rate compensator is configured to increase the reference voltage by a compensation voltage that compensates for a time delay of the comparator or the transistor control circuit. The compensation voltage is proportional to the slew rate.

Abstract: A PWM (Pulse Width Modulation) controller includes a current detector, a current emulator, a voltage-to-current converter, and a current adder. The current detector detects a first current, and generates a second current according to the first current. The current detector receives an input voltage and outputs an output voltage. The current emulator obtains the relative information of a lower-gate current. The voltage-to-current converter draws a third current from the current emulator according to the input voltage and the output voltage. The current emulator generates a fourth current according to the relative information and the third current. The current adder adds the fourth current to the second current, so as to generate a sum current.

Abstract: Circuits and methods that provide for fast power up and power down times in a multi-stage LDO regulator. In one embodiment, a multi-stage LDO regulator circuit includes, for each stage for which fast power up and/or power down times are desired, at least one transconductance amplifier coupled and configured to compare a primary reference voltage to one of a secondary reference voltage for the stage or an output voltage of the stage, and coupling and configuring the at least one transconductance amplifier to charge and/or discharge an associated capacitor to achieve a desired charge level within a specified time independently of the value of the associated capacitor. In general, the transconductance amplifiers of each stage are configured to charge and/or discharge an associated capacitor in synchronism with a voltage present on the primary reference voltage input.

Abstract: An integrated circuit including a comparator having a first input to receive a reference voltage, a second input, and an output to provide an under-voltage indicator. Sense points are configured to provide a plurality of sense point voltages, each sense point providing a corresponding sense point voltage of the plurality of sense point voltages; and a minimum voltage tracking circuit configured to receive the plurality of sense point voltages and provide an output voltage which tracks whichever sense point voltage of the plurality of sense point voltages is currently a minimum sense point voltage. The comparator receives the output voltage at the second input and asserts the under-voltage indicator when the output voltage is below the reference voltage.

Abstract: A voltage regulator circuit is disclosed. The voltage regulator includes a feedback circuit configured to generate a feedback signal based on a voltage level present on a regulated power supply node. A comparison circuit is arranged to generate an error signal based on the feedback signal and a reference voltage level. A compensation circuit is configured to modify the error signal, based on a routing impedance coupled between the regulated supply voltage node and a load circuit, to generate a control circuit. An output circuit of the voltage regulator is configured to source current to the regulated power supply node based on the control signal.

Abstract: An amplifier includes an input circuit that amplifies a difference between a first input voltage and a second input voltage to generate a first current and a second current. A positive feedback circuit amplifies a difference between the first current and the second current to generate a third current and a fourth current and outputs a difference between the third current and the fourth current through an output node. A temperature compensation circuit adjusts an amplification factor of the positive feedback circuit in response to a change of temperature.

Abstract: A voltage-to-current converter includes a first transistor having a drain coupled to a first node, a second transistor having a drain coupled to the first node, an operational amplifier having a first input terminal configured to receive a reference voltage and a second input terminal coupled to a source of the first transistor or a source of the second transistor, a control circuit having an input terminal coupled to an output terminal of the operational amplifier, a first output terminal coupled to a gate of the first transistor, and a second output terminal coupled to a gate of the second transistor, a first resistor coupled between the source of the first transistor and a ground, and a second resistor coupled between the source of the second transistor and the ground. An output current of the voltage-to-current converter is generated from the first node.

Abstract: A voltage regulator includes an operational amplifier, a first transistor, a second transistor, a capacitor and a current sink circuit. The operational amplifier outputs a control voltage according to an amplified differential voltage between a first input terminal and a second input terminal of the operational amplifier. The first transistor includes a control terminal receiving the control voltage, a first terminal coupled to a supply terminal, a second terminal providing an output voltage, and a bulk terminal. The second transistor includes a second terminal coupled to the bulk terminal of the first transistor, and a bulk terminal coupled to the supply terminal. The capacitor includes a first terminal coupled to the bulk terminal of the first transistor, and a second terminal receiving the output voltage. The current sink circuit generates a feedback voltage according to the output voltage and output the feedback voltage to the operational amplifier.

Abstract: According to an aspect a low noise electronic voltage regulator comprises a regulating transistor operative to regulate an input DC voltage to provide a regulated DC output voltage, an error amplifier configured to generate an error signal based on a reference voltage and a feedback voltage, wherein the error amplifier receiving the feedback voltage through a feedback loop formed between the regulated DC output voltage and the feedback voltage, and a first amplifier in the feedback loop providing a gain of greater than unity from the regulated DC output voltage and the feedback voltage.

Abstract: An electronic device includes a hysteresis circuit, a voltage divider circuit, a control circuit, and a discharge resistor. The hysteresis circuit has a first threshold voltage and a second threshold voltage. The hysteresis circuit generates a hysteresis voltage according to an output voltage at an output node. The voltage divider circuit generates a divided voltage according to the output voltage and the hysteresis voltage. The control circuit has a reference voltage and monitors the divided voltage. If the divided voltage is lower than the reference voltage, the control circuit will use the discharge resistor to perform a discharging operation to the output voltage at the output node.

Abstract: A system includes: an input voltage source; a power stage coupled to the input voltage source; a load coupled to an output of the power stage; and an error amplifier circuit coupled to the power stage. The error amplifier circuit includes an error amplifier; a transconductance stage coupled to an output of the error amplifier; an internal compensation switch; an external compensation switch; and control logic coupled to the internal compensation switch and the external compensation switch. The control logic is configured to selectively operate the internal compensation switch and the external compensation switch in one of an internal compensation mode and an external compensation mode.

Abstract: Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage VOFFSET as a function of load current to substantially cancel out variations in VOUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use VOFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage VOUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage VOUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.

Abstract: A Low Dropout Regulator (LDO) with Less Quiescent Current in the Dropout Region is described, including an error amplifier configured to compare a reference voltage to an LDO output voltage across a resistive divider, a current mirror configured to mirror a first output of the error amplifier to a first and second output of the current mirror, and a comparator configured to compare the LDO output voltage to a second output of the error amplifier, which has been compared to the second output of the current mirror, and configured to output a control voltage to the error amplifier, where a low quiescent current is maintained when an LDO input voltage is near or less than the LDO output voltage.

Abstract: A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.

Abstract: A linear voltage regulator includes a voltage input and a voltage output. The linear voltage regulator includes a buffer having a voltage node, an input node, an output node and a control node and a power transistor having a control node coupled to the output node of the buffer, an input node coupled to the voltage input and an output node coupled to the voltage output. The linear voltage regulator includes a dropout detection module having a control node coupled to the control node of the power transistor, a voltage input node coupled to the voltage input, a voltage output node coupled to the voltage output and an output node. The linear voltage regulator includes a feedforward module having an input node coupled to the output node of the dropout detection module and an output node coupled to the control node of the buffer.

Abstract: A device is disclosed. The device includes an operational amplifier, an output circuit and a first feedback circuit. The operational amplifier includes an input terminal that is configured to receive a feedback signal. The output circuit is coupled to an output terminal of the operational amplifier and is configured to generate an output signal in response to an output of the operational amplifier. The first feedback circuit is coupled to the output circuit and is configured to couple at least one first ripple signal in the output signal to the input terminal of the operational amplifier that is configured to receive the feedback signal, for adjusting the output signal. A method also is disclosed herein.

Abstract: In some examples, a circuit comprises a first field effect transistor (FET) having a first gate adapted to couple to a reference voltage source, a first source coupled to a first current source, and a first drain coupled to a second current source. The circuit comprises a second FET having a second gate coupled to the first drain, a second drain coupled to the first current source, and a second source coupled to a first resistor. The circuit comprises a third FET having a third gate adapted to couple to a feedback loop of a voltage converter, a third source coupled to a third current source, and a third drain coupled to a fourth current source. The circuit comprises a fourth FET having a fourth gate coupled to the third drain, a fourth drain coupled to the third current source, and a fourth source coupled to a second resistor.

Abstract: According to one embodiment, a power supply circuit includes a smoothing capacitor that is charged with a charge current from an output transistor and outputs a voltage as an output voltage; a control loop that controls a conduction state of the output transistor depending on a difference value between the output voltage and a reference voltage; and a gain adjustment circuit that adjusts a gain of the control loop depending on magnitude of the charge current after the charge starts.

Abstract: A linear regulator includes a pass transistor, a buffer transistor, and a low-pass filter circuit. The pass transistor is configured to pass a current from an input terminal to an output terminal. The buffer transistor is coupled to the input terminal and the pass transistor, and is configured to control the pass transistor. The low-pass filter circuit is coupled to the input terminal and the buffer transistor, and is configured to modulate a threshold voltage of the buffer transistor responsive to a transient at the input terminal.

Abstract: A method for regulating a voltage reference signal includes providing a first output current during a first interval and a boosted output current during a second interval to generate a low-dropout voltage reference signal based on a first power supply voltage, a second power supply voltage, and a reference voltage level. The method includes, during the second interval, compensating for a voltage drop caused by providing the boosted output current. The first output current may be provided in a first mode of operation. The boosted output current and voltage drop compensation may be provided in a boosted mode of operation.

Abstract: In an example, an apparatus includes an error amplifier, a buffer, a transistor, and a current-mode feedforward ripple canceller (CFFRC). The error amplifier has an amplifier output, a first input, and a second input, the error amplifier second input configured to receive a reference voltage. The buffer has a buffer input and a buffer output, the buffer input coupled to the error amplifier output. The transistor has a gate, a source, and a drain, the gate coupled to the buffer output, the drain coupled to the first input. The transistor is configured to receive an input voltage (VIN) at the source and provide an output voltage at the drain. The CFFRC has a CFFRC input and a CFFRC output, the CFFRC output coupled to the gate, and the CFFRC input configured to receive VIN.

Abstract: A solid-state circuit is presented which may comprise a pass device, a control circuit, and a leakage current compensation circuit. The pass device may have a first terminal, a second terminal and a drive terminal, wherein the first terminal of the pass device is coupled with an input terminal of the solid-state circuit, and wherein the second terminal of the pass device is coupled with an output terminal of the solid-state circuit. The control circuit may be coupled with the drive terminal of the pass device and may be configured to drive the pass device with a driving voltage. The leakage current compensation circuit may be configured to receive a leakage current of the pass device and may be configured to forward said leakage current as a bias current to said control circuit.

Abstract: Aspects of the disclosure include a device comprising an energy storage device configured to provide first power having a first voltage level, a voltage regulator coupled to the energy storage device and configured to receive the first power and regulate the first power to generate regulated power having a set output regulated voltage level, and bias circuitry coupled to the voltage regulator and including an output branch to output a bias current, and a feedback branch to control the bias current, the feedback branch including a bias-boosting component configured to be in an active mode responsive to the first voltage level being below the set output regulated voltage level and to be in an inactive mode responsive to the first voltage level being at or above the set output regulated voltage level.