With A Specific Feedback Amplifier (e.g., Integrator, Summer) Patents (Class 323/280)
  • Patent number: 8884604
    Abstract: A current mirror for generating a substantially identical current flow in two parallel current paths, each current path comprising a switching device and each switching device comprising first and second active terminals and a control terminal for controlling current flow between the first and second active terminals, the current mirror comprising a first switching device arranged such that its first active terminal is arranged to receive a first voltage, its second active terminal is arranged to receive a variable voltage that varies independently of the first voltage and its control terminal is arranged to receive a control voltage, a second switching device connected such that its first active terminal is arranged to receive the first voltage and its control terminal is arranged to receive the control voltage and a voltage control device connected to the second switching device such that an input of the voltage control device is connected to the second active terminal of the second switching device, the vo
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: November 11, 2014
    Assignee: Cambridge Silicon Radio Limited
    Inventor: Jens Bertolt Zolnhofer
  • Publication number: 20140320097
    Abstract: A negative voltage regulation circuit includes an operational amplifier configured to receive a feedback voltage and an input voltage, a pull-up element configured to pull-up drive a first node based on output voltage of the operational amplifier, a load element coupled between the first node and a negative voltage terminal, a pull-down element configured to pull-down drive a final negative voltage output terminal using a voltage of the negative voltage terminal based on a voltage level of the first node, and a voltage division unit coupled between the final negative voltage output terminal and a pull-up voltage terminal, and configured to generate the feedback voltage by voltage division.
    Type: Application
    Filed: July 10, 2014
    Publication date: October 30, 2014
    Inventor: Jae-Kwan KWON
  • Patent number: 8872492
    Abstract: Systems and method for a capacitor-less Low Dropout (LDO) voltage regulator. An error amplifier is configured to amplify a differential between a reference voltage and a regulated LDO voltage. Without including an external capacitor in the LDO voltage regulator, a Miller amplifier is coupled to an output of the error amplifier, wherein the Miller amplifier is configured to amplify a Miller capacitance formed at an input node of the Miller amplifier. A capacitor coupled to the output of the error amplifier creates a positive feedback loop for decreasing a quality factor (Q), such that system stability is improved.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: October 28, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Junmou Zhang, Lew G. Chua-Eoan
  • Publication number: 20140312866
    Abstract: A linear regulator integrated circuit may be formed having four external terminals including a voltage input (Vin) terminal, a voltage output (Vout) terminal, a Set terminal, and an operational amplifier (op amp) power terminal. A user connects an external resistor to the Set terminal for creating a reference voltage. An op amp controls a pass (or series transistor) to cause an output voltage at the Vout terminal to equal the reference voltage. The op amp has a first power supply terminal internally coupled to the Vin terminal and a second power supply terminal coupled to the op amp power terminal. The op amp power terminal allows a user to externally couple the op amp second power supply terminal to either the Vout pin (for high voltage applications), system ground (for medium voltage applications), or another voltage (to provide additional headroom in very low voltage applications).
    Type: Application
    Filed: August 19, 2013
    Publication date: October 23, 2014
    Applicant: Linear Technology Corporation
    Inventors: Robert Dobkin, Amitkumar Pravin Patel
  • Publication number: 20140312867
    Abstract: A low drop out voltage regulator includes an operational transconductance amplifier configured to be supplied with a supply voltage of the regulator, receive as inputs a reference voltage and a feedback voltage, and generate an intermediate current based upon a difference between the reference voltage and the feedback voltage. A current-to-voltage amplification stage is configured to be supplied with a boosted voltage greater than the supply voltage from a high voltage line, receive as input the intermediate current, and generate a driving voltage that is changed based upon the intermediate current. A pass transistor is controlled with the driving voltage to keep constant on a second conduction terminal thereof a regulated output voltage. A feedback network generates the feedback voltage based on the regulated output voltage.
    Type: Application
    Filed: December 5, 2013
    Publication date: October 23, 2014
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Francesco PULVIRENTI, Santo Ilardo
  • Patent number: 8866457
    Abstract: A voltage regulator has a phase compensation circuit which changes consumption current according to load current thereby to reduce consumption current. The phase compensation circuit includes: a first transistor having a drain connected to an output terminal of an error amplifier circuit; a second transistor having a drain connected to a gate of the first transistor and a gate connected to the gate of the first transistor; a current mirror circuit connected to the output terminal of the error amplifier circuit, a drain of the first transistor, and the drain of the second transistor; and a capacitor connected between the gate of the second transistor and a drain of an output transistor. Thereby, current consumed by the phase compensation circuit can be changed according to the load current, resulting in that the voltage regulator consumes less current.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: October 21, 2014
    Assignee: Seiko Instruments Inc.
    Inventors: Daiki Endo, Socheat Heng
  • Patent number: 8866456
    Abstract: In one embodiment, a method of forming a power supply controller may include configuring the power supply controller to control a pass transistor to form an output current responsively to a control signal and independently of the value of the output voltage until the control signal is less than a deviation from a desired value of the output voltage.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Petr Kadanka, Pavel Londak
  • Patent number: 8866460
    Abstract: A power supply uses a power converter to generate a regulated voltage by referencing to a first DC voltage, a low dropout (LDO) regulator to generate an output voltage from the regulated voltage by referencing to a second DC voltage, and a reference voltage generator to dynamically adjust the first DC voltage according to the input voltage and the control voltage of the output transistor of the LDO regulator. The dropout voltage of the LDO regulator can be minimized to maintain the high efficiency of the power supply at different loading or selected output voltages.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: October 21, 2014
    Assignee: Richtek Technology Corp.
    Inventors: Tsung-Wei Huang, Shui-Mu Lin
  • Publication number: 20140306676
    Abstract: A compensation module for a voltage regulation device having a gain stage, an output stage and a miller compensation module includes a low-output-impedance non-inverting amplifier unit coupled to a gain output of the gain stage and an output-stage input of the output stage.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 16, 2014
    Applicant: NOVATEK Microelectronics Corp.
    Inventors: Min-Hung Hu, Pin-Han Su, Chun-Wei Huang, Chen-Tsung Wu, Chiu-Huang Huang
  • Patent number: 8860389
    Abstract: A fast load transient response circuit includes a feedback loop that senses a load transient; a first driver and a second driver responsive to a feedback signal from the feedback loop; and a first pass transistor and a second pass transistor with sources and drains being coupled to each other, and a gate of the first pass transistor being driven by the first driver and a gate of the second pass transistor being driven by the second driver. A width of the channel to length of the channel (W/L) ratio of the first pass transistor is different than that of the second pass transistor such that second pass transistor reacts faster than the first pass transistors to a load transient.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: October 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Vikram Gakhar, Preetam Charan Anand Tadeparthy
  • Patent number: 8854023
    Abstract: Various embodiments of the present invention provide apparatuses and methods for regulating an output voltage. For example, an apparatus is discussed that includes a low dropout regulator having a pass transistor and an amplifier and being operable to regulate the output voltage based on a feedback signal and a feedforward signal. The apparatus also includes an auxiliary low dropout regulator having an auxiliary pass transistor and an auxiliary amplifier. The auxiliary dropout regulator is operable to generate the feedforward signal and is substantially matched with the amplifier.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: October 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Sungmin Ock
  • Patent number: 8847678
    Abstract: A frequency compensation circuit for a voltage regulator is provided in embodiments of the present invention.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: September 30, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Liang Chen
  • Publication number: 20140285166
    Abstract: In one embodiment a low-dropout regulator comprises a first differential amplifier (Nmos1) to receive an input voltage (Vin), a power transistor (T1) coupled to the first differential input pair (Nmos1), the power transistor having an output (OUT) forming an output terminal of the low-dropout regulator to provide an output voltage (Vout) as a function of the input voltage (Vin), a second differential amplifier (Pmos1) coupled to the first differential amplifier (Nmos1), and a switching element (Mncut1, Mncut2) coupled between first and second differential amplifier (Nmos1, Pmos1), said switching element (Mncut1, Mncut2) being operated as a function of a feedback signal (Sfb) derived from the output voltage (Vout). The second differential amplifier (Pmos1) is complementary to the first differential amplifier (Nmos1).
    Type: Application
    Filed: March 20, 2014
    Publication date: September 25, 2014
    Applicant: ams AG
    Inventors: Carlo FIOCCHI, Alessandro CARBONINI
  • Patent number: 8841893
    Abstract: Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: John F. Bulzacchelli, Carrie E. Cox, Zeynep Toprak-Deniz, Daniel J. Friedman, Joseph A. Iadanza, Todd M. Rasmus
  • Publication number: 20140266104
    Abstract: A method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The method includes determining, during a power-up phase and by a capacitance sensing circuit, an estimated output capacitance value at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output capacitance value, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is inversely proportional to the estimated output capacitance value.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: VIDATRONIC, INC.
    Inventors: Mohamed Ahmed Mohamed El-Nozahi, Mohamed Mostafa Saber Aboudina, Sameh Assem Ibrahim, Faisal Abdellatif Elseddeek Ali Hussien, Moises Emanuel Robinson
  • Publication number: 20140266107
    Abstract: A voltage regulator comprises a large gm current buffer driver added between a first stage of an operation amplifier and a last stage power transistor. This current buffer allows a significant reduction in the maximum internal and external compensation capacitances needed for regulator stability. The current buffer compensation circuit allows a wide range of external capacitor sizes that increases the flexibility in choosing the external capacitor types (with low to high ESR ratings).
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Inventors: Huamin Zhou, Woowai Martin, Cristian Albina, Fritz Schlunder, Minh Le
  • Publication number: 20140266106
    Abstract: A novel architecture and method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The architecture and method also support optionally determining, during a power-up phase and by a capacitance sensing circuit, an estimated output capacitance value at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output capacitance value, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is inversely proportional to the estimated output capacitance value.
    Type: Application
    Filed: June 12, 2013
    Publication date: September 18, 2014
    Inventors: Mohamed Ahmed Mohamed El-Nozahi, Mohamed Mostafa Saber Aboudina, Sameh Assem Ibrahim, Faisal Abdellatif Elseddeek Ali Hussien, Moises Emanuel Robinson
  • Publication number: 20140266105
    Abstract: A regulator comprises an amplifier, a bias circuit, and a current trimming circuit. The bias circuit is coupled to the amplifier and supplies a first bias current to the amplifier in a first mode of a system including the regulator. The current trimming circuit is coupled to the bias circuit to adjust the first bias current.
    Type: Application
    Filed: April 15, 2013
    Publication date: September 18, 2014
    Applicant: Macronix International Co., Ltd.
    Inventors: CHIA-CHING LI, HSIEN-HUNG WU, HSIN-YI HO, HAN-SUNG CHEN, CHUN-HSIUNG HUNG, TZUNG-SHEN CHEN
  • Publication number: 20140253071
    Abstract: In accordance with an embodiment, a method of controlling a power supply node includes measuring a voltage of the power supply node, determining a first current based on the measuring, determining a first current and a second current based on the measuring, and summing the first current and the second current at the power supply node. Determining the first current includes operating a first controller having a first bandwidth, and determining the second current includes operating a second controller having a second bandwidth greater than the first bandwidth.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Inventor: Dirk Hammerschmidt
  • Patent number: 8810220
    Abstract: A power supply device, a processing chip for a digital microphone and related digital microphone are described herein. In one aspect, a power supply device includes: at least two cascaded low-dropout linear regulators. In another aspect, a processing chip for digital microphone includes a processing module and a power supply module, wherein the power supply modules includes at least two cascaded low dropout linear regulators. In another aspect, a digital microphone includes a microphone and a processing chip, wherein the processing chip includes a processing module and a power supply module, wherein the power module includes at least two cascaded low-dropout linear regulators. Embodiments described herein provide a power supply device with higher PSRR.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: August 19, 2014
    Assignee: Beijing KT Micro, Ltd.
    Inventors: Rongrong Bai, Jianting Wang, Duanduan Jian, Wenjing Wang, Jing Cao
  • Patent number: 8810218
    Abstract: A voltage regulator includes a pass transistor, an operational amplifier and a voltage divider circuit. The pass transistor receives a supply voltage to generate a regulated output voltage according to a control signal. The operational amplifier generates the control signal according to a feedback voltage. The voltage divider circuit generates the feedback voltage at a feedback node according to the regulated output voltage, and includes a string of resistors and a stabilization element. The string of resistors is coupled to the pass transistor and includes multiple resistors. The stabilization element is coupled to the resistors and receives the regulated output voltage.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: August 19, 2014
    Assignee: Mediatek Singapore Pte. Ltd.
    Inventors: Yingyi Liu, Kun Lan, Chih-Chien Huang, Yu-Kai Chou
  • Patent number: 8810224
    Abstract: A system and method to regulate voltage is disclosed. In a particular embodiment, a voltage regulator includes an error amplifier, a voltage buffer responsive to the error amplifier, and a first transistor responsive to the voltage buffer and coupled to a voltage supply source. A second transistor is coupled to the voltage supply source and further coupled to an output node. A third transistor is coupled to the first transistor and has a gate coupled to a capacitor. The capacitor is coupled to a node between the error amplifier and the voltage buffer.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: August 19, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Junmou Zhang, Yuan-Cheng Pan, Mikhail Popovich
  • Publication number: 20140225580
    Abstract: A low-dropout regulator (1) comprises a differential amplifier (3) with a reference input (5) for applying a reference voltage (VIN), a feedback input (7) and an amplifier output (9). An output transistor (11) has a control connection (13) connected to the amplifier output (9), and a control section connected between a first supply potential terminal (VDD) and a voltage output (15) of the low-dropout regulator (1). A feedback branch (17) with an RC-parallel connection (19) is coupled between the voltage output (15) and the feedback input (7). A precharge circuit (30) includes a first field effect transistor (31) with a gate (32) coupled to the feedback input (7) and is configured to precharge the RC-parallel connection (19) to a threshold voltage (VTH) of the first field effect transistor (31).
    Type: Application
    Filed: July 6, 2012
    Publication date: August 14, 2014
    Applicant: ams AG
    Inventors: Alessandro Carbonini, Paolo Draghi
  • Publication number: 20140210440
    Abstract: Circuits and methods to achieve a clean start-up process and power saving of pulsed enabled electronic devices having an output capacitor and components requiring biasing during normal operating conditions are disclosed. These electronic devices could be e.g. LDOs, amplifiers or buffers. A set of switches are enabling bias currents from the output capacitor to internal nodes requiring biasing under normal operational conditions as e.g. output nodes of amplifying means.
    Type: Application
    Filed: February 1, 2013
    Publication date: July 31, 2014
    Applicant: DIALOG SEMICONDUCTOR GMBH
    Inventors: Ambreesh Bhattad, Ludmil Nikolov
  • Patent number: 8779736
    Abstract: A linear voltage regulator includes a Miller frequency compensation having a movable zero, which tracks the frequency of the load pole as the load condition changes. The compensated voltage regulator maintains stability under variable load conditions. Because of the Miller effect, DC open-loop gain and bandwidth are not sacrificed for stability. The compensated voltage regulator can therefore maintain high power supply rejection ratio (PSRR).
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics R&D (Shanghai) Co., Ltd.
    Inventors: Sarah Gao, David Peng
  • Publication number: 20140191739
    Abstract: Exemplary embodiments disclose a low drop-out regulator including an error amplification unit which includes a zero compensation circuit configured to compensate a plurality of poles which are generated by an output terminal and a buffer, the error amplification unit is configured to generate a first comparison signal in response to a reference voltage and a feedback voltage, the buffer is configured to generate a second comparison signal in response to the first comparison signal and an input voltage, a pass unit configured to provide an output voltage and a load current to the output terminal in response to the second comparison signal and the input voltage, and a feedback unit configured to provide the feedback voltage to the error amplification unit in response to the output voltage. A driving current of the buffer is independently adjusted with respect to the load current.
    Type: Application
    Filed: January 7, 2014
    Publication date: July 10, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyoungrae KIM, Dongjin KEUM
  • Patent number: 8773096
    Abstract: A voltage regulator includes an amplifier to generate a difference voltage responsive to a comparison of a reference voltage and a feedback voltage. An output driver is coupled to the amplifier and drives a regulated output voltage responsive to the difference voltage. An impedance circuit is coupled between the output driver and a low power source and establishes the feedback voltage responsive to a current through the impedance circuit. A variation detector is operably coupled between the regulated output voltage and the difference voltage and is configured to modify the difference voltage. In some embodiments, the difference voltage is modified responsive to a rapid change of the regulated output voltage capacitively coupled to the variation detector. In other embodiments, the difference voltage is modified responsive to a rapid change of the feedback voltage capacitively coupled to the variation detector.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: July 8, 2014
    Assignee: Integrated Device Technology, inc.
    Inventors: Shawn Wang, Yumin Zhang, Jeffrey G. Barrow
  • Patent number: 8766610
    Abstract: Provided is a voltage regulator capable of reducing an influence of an offset to obtain an accurate output voltage. The voltage regulator includes: a first stage amplifier for amplifying and outputting a difference between a reference voltage and a divided voltage obtained by dividing a voltage output by an output transistor, to thereby control a gate of the output transistor; and a cascode amplifier circuit, in which the first stage amplifier includes: a first high breakdown voltage NMOS transistor as an input transistor; and an NMOS transistor as a tail current source, and in which the cascode amplifier circuit includes a second high breakdown voltage NMOS transistor as a cascode transistor.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: July 1, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Imura
  • Publication number: 20140176098
    Abstract: A voltage regulator includes a pass element having a control input coupled to a control node and operable to generate an output voltage at an output node, a negative feedback amplifier operable to receive a reference voltage and the output voltage and generate a signal at the control node based on a difference between the reference voltage and the output voltage, and a noise cancellation circuit coupled to the control node and the output node and operable to generate a bias current at the control node based on the output voltage.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Emerson S. Fang, Alvin Leng Sun Loke
  • Patent number: 8760133
    Abstract: According to one aspect of the embodiment, a linear regulator circuit includes an output transistor outputting an output current based on a input voltage, an error amplifier outputting a control signal based on an electric potential difference between an output voltage based on the output current and a reference voltage, a buffer circuit coupled between the error amplifier and the output transistor, and a drive capability adjustment circuit adjusting a load drive capability of the buffer circuit in synchronization with the output current.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: June 24, 2014
    Assignee: Spansion LLC
    Inventors: Morihito Hasegawa, Hidenobu Ito, Kwok Fai Hui, Yat Fong Yung
  • Patent number: 8754620
    Abstract: Described herein are principles for designing and operating a voltage regulator that will function stably and accurately without an external capacitance for all or a wide range of load circuits and characteristics of load circuits. In accordance with some of these principles, a voltage regulator is disclosed having multiple feedback loops, each responding to transients with different speeds, that operate in parallel to adjust an output current of the regulator in response to variations in the output current/voltage due to, for example, variations in a supply voltage and/or variations in a load current. In this way, a voltage regulator can respond quickly to variations in the output current/voltage and can avoid entering an unstable state.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: June 17, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Bansal, Kallol Chatterjee
  • Patent number: 8754621
    Abstract: A method to maintain stability of a low drop-out linear voltage regulator (LDO) includes sensing, by a voltage controlled variable resistor, a node voltage in a feedback network of the LDO linear voltage regulator, wherein the feedback network includes an error amplifier configured to regulate an output voltage level of the LDO based on a reference voltage, wherein the node voltage has a dependency on a resistive load current of the LDO, and adjusting, by the voltage controlled variable resistor and based on the sensed node voltage, a resistance value of a RC network in the feedback network, wherein the adaptive RC network produces an adaptive zero in a transfer function of the feedback network, wherein the adaptive zero reduces phase margin degradation due to an output non-dominant pole in the transfer function, and wherein a frequency of the adaptive zero is inversely proportional to the resistance value.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 17, 2014
    Assignee: Vidatronic, Inc.
    Inventor: Mohamed Ahmed Mohamed El-Nozahi
  • Publication number: 20140159683
    Abstract: An LDO/HDO circuit adds a supplementary current source to supply the output node. The current boosting section includes a digital comparator with a first input connected to the LDO's feedback loop and a second input connected to a reference level. The comparator then generates a digital output used to control the supplementary current source. This approach also can be used in a far-side implementation, where the local supply level for the load is boosted by the current source based a comparison of this local level and the output of the LDO. Miller capacitive compensation is also considered. Current in shunted to ground from a node in the Miller loop, where the level is controlled by the output of a digital comparator base on a comparison of the circuit's output voltage and a reference level.
    Type: Application
    Filed: January 25, 2013
    Publication date: June 12, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Feng Pan, Sung-En Wang, Jiang Yin
  • Publication number: 20140159682
    Abstract: An LDO/HDO circuit adds a supplementary current source to supply the output node. The current boosting section includes a digital comparator with a first input connected to the LDO's feedback loop and a second input connected to a reference level. The comparator then generates a digital output used to control the supplementary current source. This approach also can be used in a far-side implementation, where the local supply level for the load is boosted by the current source based a comparison of this local level and the output of the LDO. Miller capacitive compensation is also considered. Current in shunted to ground from a node in the Miller loop, where the level is controlled by the output of a digital comparator base on a comparison of the circuit's output voltage and a reference level.
    Type: Application
    Filed: January 25, 2013
    Publication date: June 12, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Feng Pan, Sung-En Wang, Jiang Yin
  • Publication number: 20140139197
    Abstract: A bypass low dropout regulator has a pass gate coupled to a voltage rail. The pass gate receives a pass gate control signal on a pass gate control line and controllably drops a voltage from a rail to a regulated output in accordance with the pass gate control signal. A differential amplifier generates the pass gate control voltage using a reference and feedback from the regulated output. A bypass switch selectively bypasses the regulator control signal, in response to a bypass signal, by placing a pass gate ON voltage on the pass gate control line. Optionally, and ON-OFF mode circuit selectively disables the pass gate in response to a system ON-OFF signal.
    Type: Application
    Filed: March 7, 2013
    Publication date: May 22, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Burt L. Price, Dhaval R. Shah, Yeshwant Nagaraj Kolla
  • Patent number: 8717003
    Abstract: A voltage regulator circuit includes: a first pulse generator configured to output a pulse whose level remains unchanged when an input signal of a first circuit is in a first period, and whose level changes from a second level to a first level when an edge of the input signal of the first circuit is detected after the first period; a second pulse generator configured to output a pulse from a time that the pulse output by the first pulse generator becomes the first level until a second period elapses; a first field-effect transistor having a source connected to a power supply potential node, and a drain connected to a power supply potential terminal of the first circuit; and a first switch configured to cause a potential at a gate of the first field-effect transistor to be a first potential.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Limited
    Inventors: Tetsutaro Hashimoto, Tetsuyoshi Shiota
  • Patent number: 8716993
    Abstract: A low dropout (LDO) regulator includes a voltage regulation loop for providing an output voltage to an output terminal, where the output voltage is proportional to a reference voltage. The voltage regulation loop includes a current bias input for receiving a bias current. The LDO regulator also includes a bias current control circuit for providing the bias current at a first value when the reference voltage is greater than a feedback voltage and at a second value higher than the first value when the reference voltage is less than the feedback voltage.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: May 6, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Petr Kadanka
  • Publication number: 20140117957
    Abstract: A voltage regulator includes an operational amplifier that compares a feedback voltage that is proportional to an output voltage and a predetermined reference voltage that corresponds to a desired output voltage. The operational amplifier controls the conduction state of an output transistor according to the comparison. A detecting circuit monitors the operating state of the operational amplifier, and in the case that the operational amplifier is not operating, outputs a signal which causes the output transistor to be placed in a non-conductive state.
    Type: Application
    Filed: August 30, 2013
    Publication date: May 1, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masayuki USUDA
  • Patent number: 8710811
    Abstract: A voltage regulator includes an output drive device configured to provide an output voltage to an output terminal; an error amplifier configured to control the output drive device by taking into consideration a feedback signal from the output voltage; a first compensation unit configured to provide a first compensation signal to compensate an output signal of the error amplifier; and a second compensation unit configured to provide a second compensation signal to compensate an input signal of the error amplifier, wherein second compensation unit comprises at least two capacitors and at least one transistor configured to control the coupling of the two capacitors.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: April 29, 2014
    Assignee: Nan Ya Technology Corporation
    Inventors: Yuan Zhong Wan, Dong Pan
  • Patent number: 8704501
    Abstract: A current regulating circuit includes a transistor and an operational amplifier. The transistor receives a load current and generates a feedback voltage corresponding to the load current. The operational amplifier receives a reference voltage and the feedback voltage to control the transistor. The operational amplifier further includes an input stage and an output stage. The input stage includes amplifier inputs each for alternately receiving the reference voltage and the feedback voltage so that the input stage generates operating voltages corresponding to the reference voltage and the feedback voltage. The output stage receives the operating voltages alternately to control the transistor. A driver and a method of current regulation are also disclosed herein.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: April 22, 2014
    Assignee: Himax Analogic, Inc.
    Inventors: Kuan-Jen Tseng, Ching-Wei Hsueh
  • Patent number: 8692529
    Abstract: A low dropout (LDO) voltage regulator includes a scaling amplifier for receiving a bandgap voltage, Vbg, and outputting a scaled Vbg. A reference MOSFET device is included for reducing the scaled Vbg by a first voltage Vgs formed across gate and source nodes of the reference MOSFET device. This forms a reduced level of the scaled Vbg. An RC network filters the reduced level of the scaled Vbg and outputs a filtered voltage. An output buffer is included for receiving and increasing the filtered voltage by a second voltage Vgs in order to recover the scaled Vbg. The scaled Vbg is used as the desired regulated voltage output. The second voltage Vgs, which is produced by the output buffer, is equal to the first voltage Vgs, which is produced by the reference MOSFET device.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: April 8, 2014
    Assignee: Exelis, Inc.
    Inventor: Michael A. Wyatt
  • Patent number: 8692528
    Abstract: The present invention relates to a low dropout regulator, and more particularly to a low dropout regulator without load capacitor and ESR (equivalent series resistance) designed in response to the discharge curve of a Li-ion battery, includes an input terminal, a reference circuit, a power transfer element, a level regulating device, a regulating circuit, and a first N-type MOSFET. The regulating circuit detects a load change at an output terminal, amplifies the load change, and couples it to the level regulating device. The level regulating device receives and boosts a received signal and transmits the received signal to the power transfer element, so as to achieve the effect of controlling the power of a power supply.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: April 8, 2014
    Assignee: Acer Incorporated
    Inventors: Chua-Chin Wang, Shao-Fu Yen
  • Publication number: 20140091775
    Abstract: Aspects of the present invention include a low-dropout (LDO) linear power supply system. The system includes a pass-element configured to generate an output voltage at an output based on an input voltage. The system also includes a compensation amplifier stage coupled to the output and configured to provide frequency compensation and provide a desired frequency response of the output voltage. The system further includes a gain amplifier stage interconnecting the compensation amplifier stage and the pass-element and configured to provide DC gain scaling to generate the output voltage substantially proportional to the input voltage within a given range of the input voltage.
    Type: Application
    Filed: October 2, 2012
    Publication date: April 3, 2014
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: FANG DONG TAN, JEFF ZEE
  • Patent number: 8686801
    Abstract: In an embodiment of a converter, a first oscillator provides switching signals for switching between charging and discharging of a capacitor, and a second oscillator is configured to add an offset voltage or a feedback-current-dependent voltage to a sawtooth waveform generated by the second oscillator switched in synchronism with the first oscillator.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: April 1, 2014
    Inventors: Ralf Beier, Gerhard Osterloh, Michael Gattung
  • Patent number: 8680829
    Abstract: A Low-dropout (LDO) voltage regulator (1) includes: —a Ballast Transistor PBaI (3) of the P-channel MOS or Bipolar type, having a gate (34) and a main conduction path (D-S) connected in a path between the input VDD (4) and the output VOUT (5) of the regulator—an Operational Transconductance Amplifier (OTA) (2) being implemented as an adaptative biasing transistor amplifier and having an inverting input coupled to the output VOUT (5) through a voltage divider R1-R2 (61), a non-inverting input coupled to a voltage reference circuit (7) and having an output connected to the gate (34) of the Ballast transistor (3). To stabilize the output (5) and to increase the power supply rejection ratio (PSRR) of the LDO voltage regulator (1), OTA (2) includes a resistance RS, which enables to stabilize the output (5) and to increase the Power Supply Rejection Ratio (PSRR).
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: March 25, 2014
    Assignee: CSEM Centre Suisse d'Electronique et de Microtechnique SA—Recherche et Developpement
    Inventor: Frederic Giroud
  • Patent number: 8680827
    Abstract: The voltage at a spurious frequency is decreased while maintaining as much as possible the voltage at a resonance frequency of a piezoelectric transformer, thus controlling a wide voltage range with a comparatively low cost configuration. A high-voltage power supply apparatus includes a piezoelectric transformer that outputs a highest voltage at a predetermined resonance frequency, and a generating unit that generates a signal that oscillates at a drive frequency that drives the piezoelectric transformer, throughout a frequency range that includes the resonance frequency. Furthermore, the high-voltage power supply apparatus includes an output terminal connected to the piezoelectric transformer, and a constant-voltage element inserted in a path that couples the piezoelectric transformer and the output terminal.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: March 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Osamu Nagasaki, Hiroshi Mano
  • Publication number: 20140077777
    Abstract: Aspects are directed to low dropout regulation. In accordance with one or more embodiments, an apparatus includes a charge pump that generates an output using a reference voltage, a low dropout (LDO) regulator circuit, current-limit and a voltage-limit circuit. The LDO circuit includes an amplifier powered by the charge pump and that provides an LDO voltage output. The voltage-limit circuit includes a transistor coupled between a voltage supply line and the LDO regulator circuit and a gate driven by the charge pump. The voltage-limit circuit limits voltage coupled between the voltage supply line and the LDO regulator circuit based upon the output of the charge pump, such as by coupling the voltage at the voltage supply line via source/drain connection of the transistor under low-voltage conditions, and by providing a limited voltage to the LDO regulator circuit under high voltage conditions on the voltage supply line.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Inventor: Madan Mohan Reddy Vemula
  • Patent number: 8674672
    Abstract: A power supply includes a source signal generating circuit, an output stage, and a feedback stage. The power supply further includes a replica stage configured to replicate a response of the output stage to the source signal, and an output regulator coupling the replica stage to the output stage, configured to adjust a feedback signal to the source signal generating circuit by shunting the feedback stage when a loaded output stage response does not match a response of the replica stage to the source signal.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: March 18, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jaskarn Johal, Erhan Hancioglu
  • Publication number: 20140070782
    Abstract: A low-power-mode unit connected in parallel with a low-dropout regulator to provide a low-power mode includes a power P-MOS transistor, a differential amplifier, and an analog synchronization loop. The analog synchronization loop is configured to add a variable voltage offset depending on a total current at the output such that, in a high-power mode, the low-power unit current flowing through the P-MOS transistor is not zero, while being substantially smaller than the low-dropout regulator current flowing through the low-dropout regulator, and smaller than a predetermined value.
    Type: Application
    Filed: April 18, 2013
    Publication date: March 13, 2014
    Applicant: ST-Ericsson SA
    Inventors: Alexandre PONS, Gilles CHEVALIER
  • Patent number: 8648582
    Abstract: The present invention provides a programmable low dropout linear regulator using a reference voltage to convert an input voltage into a regulated voltage according to a control signal. The programmable low dropout linear regulator includes an operational amplifier having a negative input coupled to receive the reference voltage, a first transistor having a gate coupled to an output terminal of the operational amplifier and a first source/drain coupled to an output terminal of the regulated voltage, a first impedance coupled between a positive input of the operational amplifier and the output terminal of the regulated voltage, and a second impedance coupled between the positive input of the operational amplifier and a ground. The second impedance includes a second transistor having a gate coupled to receive the control signal.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: February 11, 2014
    Assignee: National Chung Cheng University
    Inventors: Chung-Hsun Huang, Ke-Ming Su