Abstract: A method is provided. A low dropout regulator (LDO) is disabled during a first mode, and a first reference voltage is selected and applied to a switched-mode converter during the first mode. Also during the first mode, a first output voltage is generated by the switched-mode converter from a power supply, and a first capacitor is overcharged with the first output voltage. The LDO is then enabled during a second mode. During a first portion of a startup period for the second mode, a second capacitor is charged from the first capacitor, and a second reference voltage is selected and applied to the switched-mode converter. Then, during a second portion of the startup period for the second mode, the second capacitor is charged with the switched-mode converter.

Abstract: A method is provided. A first reference voltage during an idle mode is selected, and the first reference voltage is applied to a switched-mode converter. A first output voltage is then generated by the switched-mode converter from a power supply, and a capacitor is overcharged with the first output voltage. The first output voltage is regulated to generate a second output voltage during the idle mode. Then, a second reference voltage during a quiet mode, where the second reference voltage to the buck converter. During the quiet mode, a third output voltage is generated from the switched-mode converter and from discharging the overcharged capacitor, and the third output voltage is regulated to generate the second output voltage.

Abstract: An over-current protection device for multiple high-voltage motive devices is provided. The over-current protection device includes a comparison module and a logic operation module. The comparison module receives a plurality of voltages generated from a plurality of operating currents of a plurality of high-voltage motive devices and respectively compares the voltages with at least one reference voltage to generate a plurality of comparison results, wherein the high-voltage motive devices are solenoids, electronic clutches, or a combination of solenoids and electronic clutches. The logic operation module receives the comparison results and generates at least one control signal for a plurality of high-voltage motive device driving circuits according to the comparison results. The high-voltage motive device driving circuits respectively drive the high-voltage motive devices according to the control signal.

Abstract: The present invention discloses a linear regulator and a control circuit therefor. The linear regulator includes: a power device coupled between an input voltage and an output voltage; a first error amplifier including a depletion NMOS differential circuit comparing a feedback signal related to the output voltage with a reference signal; a second error amplifier including a native NMOS differential circuit comparing the feedback signal with the reference signal; and a start-up circuit which enables the first error amplifier to dominate control and drive the power device when the linear regulator is at a first stage of a start-up period and enables the second error amplifier to dominate control and drive the power device when the linear regulator is at a second stage after the first stage.

Abstract: An output circuit includes a bias circuit that operates when a power supply voltage equal to or larger than a predetermined voltage is applied, a differential amplifier circuit that outputs signals according to input differential signals upon receiving a bias current or bias voltage generated when the bias circuit is operated, an output stage circuit that receives differential signals according to an output from the differential amplifier circuit and outputs output signals according to the differential signals, the output stage circuit having fewer number of stages of elements connected in series than the bias circuit, and a pull-down circuit that forcibly sets a level of one of the differential signals received by the output stage circuit to a ground voltage to fix the level of the output signals output from the output stage circuit when the bias current or the bias voltage generated by the bias circuit is not supplied.

Abstract: A voltage controlled current source circuit is utilized to clamp the internal compensation node of a low dropout (LDO) regulator with an NMOS output during load transients. The circuit senses a voltage drop of the internal node and mirrors its current to the internal node to hold the internal node voltage when the voltage starts to drop low enough to turn off the output transistor.

Abstract: Circuits and methods for paralleling voltage regulators are provided. Improved current sharing and regulation characteristics are obtained by coupling control terminals of the voltage regulators together which results in precise output voltages and proportional current production. Distributing current generation among multiple paralleled voltage regulators improves heat dissipation and thereby reduces the likelihood that the current produced by the voltage regulators will be temperature limited.

Abstract: A power source apparatus includes: a switch circuit to receive an input voltage; a control circuit to switch the switch circuit from a second state to a first state at a timing corresponding to a comparison result between a feedback voltage generated based on a first voltage corresponding to an output voltage and a reference voltage generated based on a standard voltage set in accordance with the output voltage; and a voltage generation circuit to add a compensation voltage generated by voltage-converting a time period in which the switch circuit switches from the second state to the first state to one of the first voltage and the standard voltage, to generate the feedback voltage, to add a slope voltage which changes at a slope to one of the first voltage and the standard voltage, and to generate the reference voltage.

Abstract: Area-efficient voltage regulators are provided in which a first transistor has a first breakdown voltage and a first on-state resistance and a second transistor has a second breakdown voltage that exceeds the first breakdown voltage and a second on-state resistance that exceeds the first on-state resistance. With this arrangement, the second transistor can be biased to raise an output voltage. When the difference between an input voltage and the output voltage is less than a predetermined voltage, the second transistor is disabled and the first transistor is controlled to provide the output voltage at a wherein the controlling is preferably performed with a feedback control loop. The die area of the first transistor can be reduced because its on-state breakdown need only exceed the predetermined voltage rather than the substantially-higher input voltage.

Abstract: Various embodiments of the present invention provide apparatuses and methods for regulating an output voltage. For example, an apparatus is discussed that includes a low dropout regulator having a pass transistor and an amplifier and being operable to regulate the output voltage based on a feedback signal and a feedforward signal. The apparatus also includes an auxiliary low dropout regulator having an auxiliary pass transistor and an auxiliary amplifier. The auxiliary dropout regulator is operable to generate the feedforward signal and is substantially matched with the amplifier.

Abstract: An electronic device with a power switch capable of regulating power dissipation includes a power supply device; a power switch, for providing an output voltage; and a current regulating circuit, which includes an adaptive control unit, for outputting a regulating signal, according to the voltage difference between the power supply device and the output voltage; and a switch control unit, for outputting a switch control signal to control the magnitude of the current through the power switch, according to the regulating signal.

Abstract: A voltage regulator includes a current bridge and first and second current paths coupling a current mirror to respective first and second voltage-to-current converters. The current mirror controls a second current dependent on a first current. The first voltage-to-current converter controls the first current dependent on either a reference voltage or a feedback voltage derived from the regulator's output voltage, and the second voltage-to-current converter controls the second current dependent on the other of the feedback and reference voltages. Voltage-to-current conversion by the first converter is independent of voltage-to-current conversion by the second converter. An output transistor stage coupled to the second current path controls the output voltage dependent on the voltage in the second current path indicative of a deviation of the second current from a target current value dependent on the reference voltage.

Abstract: A linear regulator and a method of regulating a supply voltage are provided. Embodiments include a linear regulator with a first feedback loop and a second feedback loop. The first feedback loop is characterized by a first bandwidth and a first gain. The first feedback loop includes a first amplifier characterized by an output impedance which is significantly reduced in order to maximize the bandwidth of the first feedback loop when driving the capacitance of a control input of a series pass element. The second feedback loop is characterized by a second bandwidth and a second gain. The second feedback loop includes a second amplifier that controls the current in the first amplifier in the first feedback loop.

Abstract: Circuits and methods for power efficient generation of supply voltages and currents in an integrated circuit by reducing the power consumption of all core analog circuit blocks by a pulsed operation mode are disclosed. In a preferred embodiment of the invention the invention has been applied to a power management chip. Pulsed Mode of Operation of ALL core analog blocks—internal LDO/s, VREF an IBIAS generators, results in significantly reduced power consumption. New circuit realizations and control algorithms to improve the ON/OFF ratio of the Pulsed Mode Operation yield in better power efficiency. Innovative circuit implementation consisting of an additional Top Up Buffer Amplifier stage ensures a fast recharge of VREF output, thus allowing shorter ON times and respectively even better power efficiency. Bypassing a low bandwidth and slow to start LDO with a fast Bypass Comparator supplies a LDO rail in Pulsed Mode of operation.

Abstract: A voltage down converter includes a voltage comparator for comparing a first reference voltage and an internal voltage to provide a first driving signal; a driving signal controller coupled with the voltage comparator, the driving signal controller configured to generate a second driving signal in response to an external voltage and selectively providing any one of the first and second driving signals; and a voltage supply coupled with the driving signal controller, the voltage supply configured to receive the selectively provided first and second driving signals, wherein the voltage supply is activated in accordance with the first or second driving signal, thereby providing the internal voltage.

Abstract: A power supply circuit for south bridge chip includes a voltage conversion chip, a control circuit, and a voltage increasing circuit coupled electrically to the voltage conversion chip and the control circuit. The voltage conversion chip is configured for outputting a driving signal. The control circuit is configured for receiving the driving signal and a first voltage, and converting the first voltage to a second voltage according to the driving signal. The voltage increasing circuit is configured for increasing voltage level of the second voltage, wherein the second voltage is supplied to the south bridge chip via the voltage increasing circuit.

Abstract: A load driving apparatus is provided. The load driving apparatus is configured to output an electrical signal to a load. The load driving apparatus includes a driver and an average voltage/current detector. The driver receives an input voltage and a control signal. The driver tunes the electrical signal according to the control signal. The average voltage/current detector receives the electrical signal outputted to the load and generates the control signal by comparing the electrical signal and a reference signal.

Abstract: A low drop-out (LDO) voltage regulator with a wide bandwidth power supply rejection ratio (PSRR) is described. In one aspect, the LDO voltage regulator includes two individual voltage regulator circuit stages. A first stage voltage regulator circuit output is at an intermediate voltage (VINT) between an input supply voltage (VDD) and a final regulated output voltage (VREG). A second stage voltage regulator circuit output is at the final regulated output voltage (VREG) and is optimized for noise-sensitive analog circuits across a wide operating bandwidth. The first stage voltage regulator circuit has a zero frequency while the second stage voltage regulator circuit has a matching pole frequency to minimize the AC response from VDD to VREG across all frequencies.

Abstract: A voltage regulator includes first and second closed-loop amplifiers and a N-type transistor. The first amplifier receives a first reference voltage and a feedback voltage. The second amplifier is responsive to the first amplifier and to the regulated output voltage of the regulator. Both amplifiers are biased by a biasing voltage. The second amplifier has a bandwidth greater than the bandwidth of the first amplifier and a gain smaller that the gain of the first amplifier. The N-type transistor has a first terminal responsive to the output of the second amplifier, a second terminal that receives the input voltage being regulated, and a third terminal that supplies the regulated output voltage. The feedback voltage is generating by dividing the regulated output voltage. An optional fixed or dynamically biased current source biases the first terminal of the N-type transistor. The voltage regulator optionally includes an overshoot correction circuit.

Abstract: A voltage regulator includes an amplifier, a power device, a delay signal generator, and a voltage-generating circuit. The amplifier generates a control signal according to a reference voltage and a feedback voltage. The power switch generates the output voltage by regulating the output current according to the switch control signal. The delay signal generator generates a plurality of sequential delay signals each having distinct delay time with respect to an externally applied power-on burst signal. The voltage-generating circuit provides an equivalent resistance for generating the feedback voltage corresponding to the output voltage, and regulates the output voltage by adjusting the equivalent resistance according to the plurality of sequential delay signals.

Abstract: An apparatus includes at least one filter configured to filter a reference voltage to generate a filtered reference voltage. The apparatus also includes an amplifier configured to amplify a difference between the filtered reference voltage and a feedback voltage to generate a drive signal. The apparatus further includes a first transistor configured to generate an output voltage based on the drive signal, where the feedback voltage is based on the output voltage. The apparatus also includes a second transistor configured to generate a first bias current for the amplifier based on the drive signal. In addition, the apparatus includes a voltage-to-current converter configured to generate a second bias current for the amplifier based on the reference voltage and the feedback voltage. The second transistor can generate higher first bias currents during higher load currents, and the voltage-to-current converter can generate higher second bias currents during faster load current variations.

Abstract: Embodiments of a system and method to control the overlap times—and deadtime delays—in power converters may support both overlapping and non-overlapping gate control signals, which may provide improved efficiency optimization across a wider range of applications. Various embodiments may be configured to provide careful partitioning between hardware implementation and software control, in order to better accommodate microprocessor-based power converters. Software algorithms may be used to avoid restrictions such as high gate impedance and changing load effects, and protection against errant operation may be provided using an overlap watchdog circuit. Various control circuits may be operated according to one or more algorithms configured to optimize both the HS-to-LS and LS-to-HS deadtime delays for obtaining minimum possible PWM duty cycle values to achieve improved power efficiency.

Abstract: Provided is a voltage regulator that is capable of improving a transient response characteristic while suppressing current consumption. A fluctuating output voltage is detected without increasing the current consumption of a differential amplifier, and a phase compensation resistor (60) is temporarily short-circuited, to thereby decrease a time constant determined by a parasitic capacitance of an output transistor (40) and the phase compensation resistor (60) to improve the transient response characteristic. Alternatively, a voltage divider circuit (50) is short-circuited to temporarily increase the current consumption and correct the output voltage, with the result that the current consumption during a normal operation is relatively low, and the transient response characteristic is improved by increasing a current only during a transient response.

Abstract: Embodiments of circuits, apparatuses, and systems for a voltage regulator with a control loop for avoiding hard saturation are disclosed. Other embodiments may be described and claimed.

Abstract: A low dropout voltage regulator (LDO) includes first and second amplifiers and a current mirror. The first amplifier includes a first input receiving a reference voltage and a second input receiving a voltage proportional to an output of the LDO. The current mirror includes an input current at a first end of the current mirror to an output current at a second end of the current mirror, the input current controlled by an output of the first amplifier and the output current being supplied to the output of the LDO. The second amplifier includes a first input coupled to the first end of the current mirror and a second input coupled to the second end of the current mirror.

Abstract: A switching regulator is disclosed that includes a switching element; an inductor; a rectifier element; an error amplifier circuit portion; a PWM pulse generating circuit portion; a current sensing circuit portion; an output voltage decrease detecting circuit portion; a current pulse generating circuit portion; a phase detecting circuit portion; a VFM pulse generating circuit portion; and a switching control circuit portion configured to generate a control signal based on a PWM signal or a VFM signal and to switch a control status of the switching element from a PWM control to a VFM control in accordance with a third signal output from the phase detecting circuit portion, and to switch the control status from the VFM control to the PWM control in accordance with a second signal output from the output voltage decrease detecting circuit portion.

Abstract: A voltage regulator may include an input terminal for receiving an input voltage and an output terminal for providing a respective output voltage, a regulation transistor having a first conduction terminal coupled to the input terminal for receiving the input voltage, a second conduction terminal coupled to the output terminal, and a control terminal coupled to the output of a first operational amplifier. The first operational amplifier may have a non-inverting input terminal for receiving a first reference voltage, and an inverting input terminal coupled to a first terminal of a divider circuit for receiving a second reference voltage.

Abstract: A low dropout voltage regulator (LDO) is presented that takes into consideration short channel effects of the pass transistor in suppressing ripples that are present at the input node of the LDO from appearing at the output node of the LDO. A sum of the input ripple voltage and the input ripple voltage multiplied by a gain equal to the reciprocal of the intrinsic gain provided by the pass transistor is fed to the gate of the pass transistor. In one embodiment an adaptive stage is utilized to provide the sum to the gate of the pass transistor. The adaptive stage gain adapts to change changing load currents such that the gate voltage is maintained substantially equal to the sum. In another embodiment, the LDO is provided stability by using only on-chip capacitors. The LDO provides stable operation even at small load currents.

Abstract: A low-dropout linear regulator includes an error amplifier comprising a cascaded arrangement of a differential amplifier and a gain stage having interposed therebetween a frequency compensation network for a loading current to flow therethrough. The regulator includes a current limiter inserted the flow-path of the loading current for the compensation network to increase the slew rate of the output of the differential amplifier by dispensing with the capacitive load in the frequency compensation network during load transients in the regulator.

Abstract: To improve noise rejection, a native (or undoped) NMOS transistor is used as a source follower in place of a conventional common source PMOS transistor in a voltage regulator circuit. The native transistor has a threshold voltage of approximately 0 volts which allows the maximum voltage output of the regulator to be higher by one threshold voltage of a conventional NMOS transistor than might be obtained from a voltage regulator that used a conventional NMOS transistor. Alternatively, a depletion transistor can be used to provide even higher output. In another illustrative embodiment, a conventional bandgap reference circuit is modified by replacing a common source transistor connected to the output of an op amp with a native MOS transistor connected as a source follower.

Abstract: A current sensing circuit includes a first resistor, a second resistor and a sense amplifier. The first resistor converts a current flowing through the first resistor to a voltage drop between positive and negative sides of the first resistor. The second resistor is coupled to the negative side of the first resistor. The sense amplifier is coupled to the positive side of the first resistor via a first pin of the sense amplifier, and coupled to the negative side of the first resistor through the second resistor via a second pin of the sense amplifier. The sense amplifier employs a negative feedback to generate a sensing current proportional to the current flowing through the first resistor.

Abstract: A constant-voltage power supply circuit which limits the consumption current inside at startup or when overloaded and suppresses the occurrence of an overshoot at startup, comprises an error amplifying part; an output part having an outputting PMOS; a load current monitoring part that monitors a load current flowing through the PMOS and increases the bias current of the error amplifying part according to the load current; and a gain adjusting part having a current limiting resistor and that monitors the load current and decreases a gain of the error amplifying part according to this load current. Hence, at startup or when overloaded, the gain adjusting part operates as a limiter circuit. Hence, at startup or when overloaded, the consumption current inside can be limited. Further, at startup, the response is made slower by this limiter operation, thus suppressing the occurrence of an overshoot.

Abstract: A low-dropout linear regulator includes an error amplifier which includes a cascaded arrangement of a differential amplifier and a gain stage. The gain stage includes a transistor driven by the differential amplifier to produce at a drive signal for an output stage of the regulator. The transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce a drive signal for the output stage of the regulator. The second resistive load is a non-linear compensation element to render current consumption linearly proportional to the load current to the regulator. The first resistive load is a non-linear element causing the frequency of said zero created by the RC network to decrease as the load current of the regulator decreases.

Abstract: A linear regulator and methods of regulation are provided. In one implementation, a linear regulator is provided. The linear regulator can receive an input voltage, generate an internal bias voltage in response to the received input voltage. The linear regulator can determine if the input voltage meets one or more first criteria and second criteria, and adjust an output voltage based on the internal bias voltage if the input voltage meets the one or more first criteria. The linear regulator also can supply the input voltage directly to the load if the input voltage meets the one or more second criteria. In some implementations, the linear regulator can generate an internal bias voltage that is clamped within a desired operating range if the input voltage meets the one or more first criteria, and adjusts one or more electronic circuits using the internal bias voltage to provide the adjusted output voltage.

Abstract: A boost DC/DC converter has a voltage dividing circuit connected between the output terminal and the ground, that outputs a divided voltage obtained by dividing the output voltage; a reference voltage generating circuit that generates a reference voltage based on the input voltage; an error amplifier that outputs a first signal corresponding to the difference between the divided voltage and the reference voltage; a feedforward circuit that detects the input voltage and outputs a second signal corresponding to a current inversely proportional to the input voltage; a multiplier that multiples the first signal by the second signal and outputs a third signal obtained; and a control circuit that outputs, based on the third signal, a control signal for controlling on/off of the switching transistor so that the divided voltage is equal to the reference voltage.

Abstract: A low voltage drop out (LDO) regulator is disclosed. The LDO regulator has a voltage buffer for receiving an input voltage containing a DC component and an AC component, converting the input voltage into a converted voltage having a lower DC component and an AC component following that of the input voltage; a control stage applied with the converted voltage; and an output stage applied with the input voltage. The output stage is controlled by the control stage to output an output voltage of a specific level. In the LDO regulator, elements of small sizes can be used to save a layout area thereof. In the meanwhile, the LDO regulator can maintain a high power supply rejection ratio (PSRR) characteristic.

Abstract: A voltage regulator (10) comprises a first transistor (13) which couples an input terminal (11) of the voltage regulator (10) to an output terminal (12) of the voltage regulator (10) and a second transistor (16). The first and the second transistors (13, 16) form a current mirror structure. Further on, the voltage regulator (10) comprises a control node (17) which is coupled to the input terminal (11) of the voltage regulator (10) via the second transistor (16) and which is coupled to the output terminal (12) of the voltage regulator (10) via a feedback circuit (28). Furthermore, the voltage regulator (10) comprises an amplifier (22) with an input terminal (23) which is coupled to the control node (17) and an output terminal (24) which is coupled to a control terminal (21) of the second transistor (16).

Abstract: A power extractor suitable for locations proximate to the sink of a signal channel is disclosed. The power extractor can generate power from the signal channel without substantially disturbing a quality of signals within the channel. In one embodiment, the power extraction circuit can include: a current source coupled to a sink side of a signal channel, where the signal channel is independent of any power supply signal, the current source being high impedance to maintain signal quality within the signal channel; a first regulator configured to generate a first regulated supply from a current derived from the signal channel using the current source; and a second regulator coupled to the first regulator, where the second regulator is configured to generate a second regulated supply from the first regulated supply.

Abstract: A regulated voltage is generated at an output terminal of a voltage regulator circuit having at least one input terminal. A feedback signal is coupled from a first transistor coupled in parallel with a first resistor between the output terminal and the input terminal. The feedback signal is coupled to the input terminal to regulate the stability of the voltage regulator circuit. In a method of operation, the stability of a circuit is regulated by generating a feedback signal in the circuit to add a zero to a transfer function and raise an open loop phase curve of the circuit to result in a better power signal rejection ratio over a frequency range for the circuit.

Abstract: A regulator circuit includes an output transistor that generates an output current in accordance with a control voltage that is applied to a control terminal of the output transistor. A differential amplifier provides feedback control of the control voltage in accordance with a level of the output current. A phase compensation circuit is connected to the differential amplifier and the control terminal of the output transistor. The phase compensation circuit adjusts an output impedance of the differential amplifier. The phase compensation circuit includes a variable resistor that decreases the output impedance of the differential amplifier when the output current increases.

Abstract: A power supply device, a processing chip for a digital microphone and related digital microphone are described herein. In one aspect, a power supply device includes: at least two cascaded low-dropout linear regulators. In another aspect, a processing chip for digital microphone includes a processing module and a power supply module, wherein the power supply modules includes at least two cascaded low dropout linear regulators. In another aspect, a digital microphone includes a microphone and a processing chip, wherein the processing chip includes a processing module and a power supply module, wherein the power module includes at least two cascaded low-dropout linear regulators. Embodiments described herein provide a power supply device with higher PSRR.

Abstract: In one embodiment the present invention includes a voltage regulator circuit comprising a voltage to current converter. The voltage to current converter is coupled to provide a current to maintain an output voltage under changing load conditions. A transconductance of the voltage to current converter is independent of the output current and therefore improves stability for the voltage regulator across load conditions.

Abstract: A low-dropout linear regulator includes an error amplifier which includes a cascaded arrangement of a differential amplifier and a gain stage. The gain stage includes a transistor driven by the differential amplifier to produce at a drive signal for an output stage of the regulator. The transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce a drive signal for the output stage of the regulator. The second resistive load is a non-linear compensation element to render current consumption linearly proportional to the load current to the regulator. The first resistive load is a non-linear element causing the frequency of said zero created by the RC network to decrease as the load current of the regulator decreases.

Abstract: A voltage generator is provided. The voltage generator includes a voltage pump and a voltage controller. The voltage pump generates a target voltage using a clock signal. The voltage controller compares a temporary voltage input from the voltage pump with a reference voltage to generate a control signal controlling the voltage pump. The voltage controller includes a string of a plurality of resistors connected in series to change a level of the temporary voltage to a voltage level of a corresponding comparison voltage. When the plurality of resistors are in a string, a resistance of a resistor closest to one end of the string is greater than resistances of other resistors of the string. The voltage controller may further include a jumping unit controlling connection or disconnection of two arbitrary nodes among first to n-th nodes (where n is a natural number) defined as connection points of the adjacent resistors of the string.

Abstract: A voltage regulator circuit and control method therefor. The circuit includes input and output terminals, an output transistor to pass a current from the input terminal to the output terminal according to a control signal, a reference voltage generator unit to generate and output a reference voltage, an output voltage detector unit to detect an output voltage output from the output terminal and generate and output a proportional voltage proportional to a detected voltage, a first error amplifier unit to control the output transistor to make the proportional voltage equal to the reference voltage, and a second error amplifier unit to respond to fluctuation in the output voltage faster than the first error amplifier unit and increase the output current from the output transistor for a period of time when the output voltage rapidly drops. Current consumption of the second error amplifier unit is changed according to the output current.

Abstract: A voltage regulator includes an amplifier and a regulation loop. The regulator includes a first PMOS transistor connected to a terminal supplying an input voltage, a second PMOS transistor connected in series with the first PMOS transistor. A node between those two transistors defines an output terminal. A first source of a first polarization current of fixed value is connected to the gate of the first transistor, and a second source of a second polarization current of fixed value connects the second transistor to ground. A third NMOS transistor is connected between the two current sources. A circuit is provided to modify automatically at least one of the polarization currents in relation to the load current.

Abstract: The present invention discloses an integrated circuit for system calibration, applicable to a power supply, comprising: a comparison module, having a feedback input end coupled to a feedback signal and a reference input end coupled to an analog reference signal for delivering a status signal; a detection and control module, for generating a reference signal and a calibration value according to the status signal, wherein the calibration value is derived from the reference signal at an instant when the status signal changes state, and the calibration value is stored into a calibration value register; a memory module, for receiving, storing and outputting the calibration value; and a reference signal generator, receiving the calibration value to provide the analog reference signal. The present invention can therefore be used to automatically calibrate a system with fewer external components to provide qualified systems.

Abstract: A LED display system includes multiple LEDs, a power converter to produce a supply voltage for the LEDs, and multiple drivers to drive the LEDs. According to the maximum one of the forward voltages of the LEDs, the drivers provides a feedback signal for the supply voltage control, and the feedback signal is amplified or digitized to reduce the voltage drop in the global power line.

Abstract: A low drop out (LDO) voltage regulator (10) includes a pass transistor (MPpass) having a source coupled by an output conductor (4) to a load and a drain coupled to an input voltage to be regulated. An error amplifier (2) has a first input coupled to a reference voltage, a second input connected to a feedback conductor (4A), and an output coupled to a gate of the pass transistor. A parallel path transistor (MPpa) has a source coupled to the input voltage, a gate coupled to the output (3) of the error amplifier (2), and a drain coupled to the feedback conductor. A feedback resistor (Rf) is coupled between the feedback conductor and the output conductor.

Abstract: Disclosed is a low dropout current source that includes a first field effect transistor (FET), a second FET having a drain that is an output for an output voltage and an output current, and a third FET, wherein a gate of the first FET is coupled to both a gate of the second FET and a drain of the third FET, and wherein a drain of the first FET is coupled to a source of the third FET. A differential amplifier has an inverting input coupled to the drain of the first FET, a non-inverting input coupled to the drain of the second FET and an amplifier output coupled to the gate of the third FET. A current reference is coupled between the drain of the third FET and a fixed voltage node. The current reference provides a reference current that is multiplied and output from the third FET.