By Capacitance Measuring Patents (Class 324/519)
  • Patent number: 5744964
    Abstract: For a print-circuit board 10 of a good product, probes 31 and 32 are made to be electrically continuous with a ground plate 13 and a wiring pattern i respectively to measure a capacitance Cgi, which is then stored in a storage device 44. A capacitance Ci of a print-circuit board 10, the object of testing, is measured in a similar manner and a ratio .mu.=(average value Ca of a several measured capacitance value of the object of testing/(average value Cga of the corresponding measured capacitance values of the good product) is calculated. If Ci<Cgj(1-.DELTA.e0) or Ci>Cgj(1+.DELTA.e0), the measured capacitance values Ci and Cgjare excluded from the objects of calculation of the average values. If Cj<.mu..Cgj(1-.DELTA.e) or Cj>.mu..Cgj(1+.DELTA.e), a wiring j is judged to be defective and the resistance measuring method is employed to judge the details of the defect. The tolerance rate .DELTA.e0 and .DELTA.e are 0.15 and 0.02 respectively.
    Type: Grant
    Filed: July 25, 1996
    Date of Patent: April 28, 1998
    Assignee: Fujitsu Automation Limited
    Inventors: Morishiro Sudo, Masaru Ishijima, Kazuo Yamazaki
  • Patent number: 5677634
    Abstract: A plurality of electrical circuit components having capacitance, e.g. ceramic capacitors, are tested simultaneously in a corresponding plurality of test channels. They are stressed by a variable voltage source that can produce an electrical potential selected from a wide range from low potential to high potential. For example the range of selectable potentials can be 1000 volts with a resolution of 1 volt. The charge current by which a component accumulates a charge is controlled to a selected linear rate by a current controller. Voltage sensors and current sensors measure accumulated charges and leakage current, respectively. The current sensor can be selectively sensitized to a plurality of anticipated leakage current ranges. In addition, the selected potentials can each be applied to the components in a single step or can be applied over time in ramp fashion.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: October 14, 1997
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Peter A. Cooke, David M. Ivancic, Naom Chaplik, Michael C. Steinmeyer, Chia-mu Chang, Vernon P. Cooke
  • Patent number: 5602486
    Abstract: An apparatus and method for sensing impedances of materials placed in contact therewith. The invention comprises a plurality of drive electrodes and one or more sense electrodes. Both rotating electric fields and differently shaped electric fields are provided for, as are analysis of structure and composition at different orientations and depths.
    Type: Grant
    Filed: November 10, 1994
    Date of Patent: February 11, 1997
    Assignee: Sandia Corporation
    Inventor: James L. Novak
  • Patent number: 5559427
    Abstract: An instrument and method for the troubleshooting and verification of copper-wire local area network (LAN) cable systems provides a series of resistance and capacitance measurements between all possible wire pairs using a pair of switch matrices and a software method for evaluating the measurements which are stored in a two-dimensional matrix. The stored measurements are evaluated against predetermined figures of merit and the decision pattern in matrix form is compared to that of a known good LAN cable system. Error messages responsive to mismatches are generated and presented to the operator via a user interface. Near-end cross talk (NEXT) isolation is evaluated using a mathematically calculated differential capacitance technique. Error messages are generated responsive to difference capacitance values larger than a figure of merit correlated to an acceptable level of NEXT isolation.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: September 24, 1996
    Assignee: Fluke Corporation
    Inventors: Mark E. Hinds, Robert J. Lewandowski, Thomas P. Locke, Tzafrir Sheffer
  • Patent number: 5554981
    Abstract: A number wheel assembly (10) for a counter mechanism has a plurality of number wheels (13-18), each number wheel (13-18) having a sleeve (48) around its circumference with a plurality of positions representing successive increments in a count, a substrate (26-31) opposite one surface of the number wheel (13-18), the substrate (26-31) carrying an electrode (42) that is spaced from the number wheel (13-18) to form an air gap for a variable capacitor, and wherein the number wheel (13-18) carries at least one dielectric element (46) that is rotated with the number wheel (13-18) to vary the capacitance of the variable capacitor according to the position of the number wheel (13-18). Circuitry for detecting the capacitance and the position of the number wheels (13-18) is provided on a circuit board (39) that is electrically connected to the number wheels (13-18).
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: September 10, 1996
    Assignee: Badger Meter, Inc.
    Inventors: Ronald N. Koch, Richard H. Koch, Ray J. Thornborough
  • Patent number: 5529754
    Abstract: An analyzer has a horizontally disposed baseplate on which primary containers and secondary containers are disposed; a pipetting needle of an electrically conductive material connected to a metering device by a tubing, for transferring a predetermined volume of liquid each time from a primary container to a secondary container; a transport device for the controlled transport of the pipetting needle in three directions at right angles to one another, two of the transport directions extending horizontally and the third transport direction extending vertically; an electrically conductive reference body rigidly connected to baseplate and which in each of the horizontal transport directions has two outer surfaces disposed perpendicularly to the transport direction; and a control device for controlling the metering device and the transport is device.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: June 25, 1996
    Assignee: Hoffmann-La Roche Inc.
    Inventors: Guido Bonacina, Thomas Caratsch, Rolf Moser
  • Patent number: 5512247
    Abstract: An analyzer has a horizontally disposed baseplate on which primary containers and secondary containers are disposed, a pipetting needle, a transport device, and a control device. The pipetting needle is formed of an electrically conductive material and is connected to a metering device by a tubing, and is for transferring a predetermined volume of liquid each time from a primary container to a secondary container. The transport device is for the controlled transport of the pipetting needle in three directions at right angles to one another, two of the transport directions extending horizontally and the third transport direction extending vertically. The control device is for controlling the metering device and the transport device.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: April 30, 1996
    Assignee: Hoffmann-La Roche Inc.
    Inventors: Guido Bonacina, Thomas Caratsch, Rolf Moser
  • Patent number: 5446392
    Abstract: A fault locating method and submarine equipment for detecting the location of a fault developed in a communication system including an optical submarine cable and submarine equipment such as repeaters and branching units inserted in the cable, which is supplied with operating current via a feed line of the cable. The submarine equipment has a main processing circuit for transmitting signals via the submarine cable; an power unit inserted in the feed line so as to supply operating power for the main processing circuit by receiving the operating current from the feed line; a nonlinear resistance device which is connected to the feed line and the resistance value of which increases as a current flowing through it decreases, and a charging/discharging resistor disposed in parallel to the nonlinear resistance device. The fault locating method detects the location of an open-circuit fault occurring in the cable by measuring the capacitance of the open-circuit cable.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: August 29, 1995
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Inoue, Makoto Sumitani
  • Patent number: 5438272
    Abstract: A network-under-test of a device is tested relative to other networks of the device by probing the network-under-test with a probe; generating a voltage which is applied across the network-under-test via the probe for developing a transient voltage between the network-under-test and the other networks of the device for stressing leakage resistance between the network-under-test and the other networks; and determining if the stressed leakage resistance is acceptable for determining integrity of the network-under-test relative to the other networks of the device.
    Type: Grant
    Filed: May 9, 1994
    Date of Patent: August 1, 1995
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey A. Craig, Ka-Chiu Woo
  • Patent number: 5432457
    Abstract: A probe for measurement of an electrically conductive surface covered by an insulating cover layer has a pair of electrically conductive pads for capacitive coupling to the conductive surface. The pads may be formed by photolithography as part of a disk of a metallic layer disposed on a substrate of low dielectric material such as fibrous glass in an epoxy binder, the pads being separated by a relatively narrow gap. Included within the probe is an electrically insulating holder for supporting the substrate and the pads, the holder being configured to facilitate manual manipulation of the probe. The probe connects with a signal analyzer which provides a test signal coupled to the pads via a coaxial transmission line. During a sliding of the pads along the cover layer, electrical characteristics of a signal coupled capacitively via the pads to the conductive surface are analyzed by the analyzer to provide information on electrical continuity and resistivity of the surface.
    Type: Grant
    Filed: January 28, 1994
    Date of Patent: July 11, 1995
    Assignee: Northrop Grumman Corporation
    Inventors: Kenneth M. Mitzner, Darin S. Hunzeker, William Hant, Silvan S. Locus, John C. Bryant
  • Patent number: 5430383
    Abstract: An automated method of verifying the capacitance loads on signal pins of an integrated circuit test load board employs a tester operating with transmission line techniques. The tester signal first is disconnected from the load board; and the rise time of the reflected waveform is measured between the ten percent and ninety percent values. The tester signal then is connected to the load board; and once again, the rise time of the reflected waveform is measured between the ten percent and ninety percent values. These two rise time values then are employed to calculate the total amount of edge loading capacitance on the path between the tester and the load board.
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: July 4, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Robert E. Boos
  • Patent number: 5425275
    Abstract: For detecting strains or breaks in the surface of a boat hull or other structure, the surface is covered with non-intersecting lengths of tape adhered to the surface. The tape has an inner strip of conductive elastomer and an outer strip of the same material, and between them a corrugated layer of copper foil. Both strips and the foil are insulated from each other and the outside. The strips and foil layer are connected to electrical resistance and capacitance measuring devices, which monitor any changes in the electrical properties of the tape lengths, caused by strain or breaking of the surface. Because of the corrugations, the foil will not change its resistance when the tape is elongated or compressed.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: June 20, 1995
    Inventor: James Lockshaw
  • Patent number: 5420500
    Abstract: Disclosed is a system for testing continuity that determines whether input and output leads of semiconductor components are present and properly soldered to a printed circuit board. The system includes a signal source stimulus which is connected to a wiring trace on the printed circuit board, which is soldered to the lead being tested. A capacitive test probe is placed on top of the component. The stimulus signal is capacitively coupled through the lead of the integrated circuit package being tested to the capacitive test probe, so if a predetermined signal level is detected by the capacitance test probe, the lead is connected to the circuit assembly. As the capacitances involved are small, the capacitive test probe includes an amplifier, a shield or guard and a buffer circuit to reduce stray fields pick up effects.
    Type: Grant
    Filed: November 25, 1992
    Date of Patent: May 30, 1995
    Assignee: Hewlett-Packard Company
    Inventor: Ronald K. Kerschner
  • Patent number: 5391993
    Abstract: In a method for testing whether a pin (12) of an electronic component (14) on a circuit board under test (18) has been properly connected to a circuit-board track (16), a source (20) drives the track (16), and a capacitive probe (34) located above the component (14) generates a resultant output. The pin (12) is determined to be connected correctly if that output exceeds a threshold determined for that pin (12) during a training process in which similar measurements have been made on a known good board for that pin and other pins on the same electronic device. The threshold is determined by dividing the capacitance measurement made during the training process for that pin into connection-dependent and connection-independent parts, the latter being the part that would result even in the absence of a proper pin connection.
    Type: Grant
    Filed: January 27, 1994
    Date of Patent: February 21, 1995
    Assignee: GenRad, Inc.
    Inventors: Moses Khazam, Steven M. Blumenau
  • Patent number: 5363048
    Abstract: The integrity of the interconnects in a predefined micro-chip-module are tested in two phases. Before any integrated circuit chips are loaded onto the micro-chip-module, the capacitance value of each interconnect is measured and the measured capacitance value is compared with a predetermined range of acceptable values to establish if an interconnect error exists. The measurement and comparison process is repeated after a predefined set of integrated circuit chips are loaded onto the micro-chip-module. The capacitance of each interconnect node is indicative of the total length of the interconnect traces of the node, and thus a short circuit will result in a capacitance measurement above the predetermined range for the node, and an open circuit will result in a capacitance measurement below the predetermined range for the node.
    Type: Grant
    Filed: November 17, 1992
    Date of Patent: November 8, 1994
    Assignee: Digital Equipment Corporation
    Inventors: Douglas Modlin, Joel Parke, Deng-Yuan Fu
  • Patent number: 5266901
    Abstract: A system and a method for testing the integrity of interconnection networks on a circuit board or substrate are disclosed. To test the continuity of a being tested network, two probes are used. To test the integrity of the being tested network, as it relates to other nets on the circuit board, a rectangular pulse is provided to the being tested network, and a signal in response to the stimulus pulse, provided across an external capacitor and resistor connected to the reference plane of the circuit board or substrate, is sampled by a transient analyzer. The leading edge of the thus sampled response signal provides an indication of whether the being tested net is acceptable, opened, shorted, or has a high leakage resistance to another net.
    Type: Grant
    Filed: May 29, 1992
    Date of Patent: November 30, 1993
    Assignee: International Business Machines Corp.
    Inventor: Ka-Chiu Woo
  • Patent number: 5256975
    Abstract: A hand-held test probe is employed which uses a capacitance measuring circuit to measure capacitance as the probe is scanned along a pattern of conductors (pads or pins) at a steady rate. The capacitance measurement is stored in a memory during the scan, then maximums are detected in the stored data, corresponding to the conductor pattern. If a particular conductor has a short or a break in continuity, its capacitance will be more or less than it should be. The detected maximums are compared with recorded values for a known-good printed wiring board for this scan pattern. If the comparison shows a difference greater than a selected threshold, an error is indicated for this pin location. The known-good is scanned in a "learn" mode, in which the capacitance values are stored for each scan, identified by scan number.
    Type: Grant
    Filed: June 1, 1992
    Date of Patent: October 26, 1993
    Assignee: Digital Equipment Corporation
    Inventors: Richard I. Mellitz, Ellsworth W. Stearns
  • Patent number: 5206597
    Abstract: The invention is an apparatus for measuring the volume of water intrusion underwater cables without dissecting the cables. The apparatus comprises a novel arrangement of a capacitive test fixture and an electrical impedance analyzer to provide measurement of the volume of water in a cable based on cable capacitance. The capacitive test fixture measures the electrical capacitance along the cable as the cable is fed through the test fixture.
    Type: Grant
    Filed: August 27, 1990
    Date of Patent: April 27, 1993
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: David F. Rivera, Charles E. Odams, Michael J. McDonald, Jr.
  • Patent number: 5187430
    Abstract: Method and apparatus for determining nets among nodes in a circuit board that includes applying a potential to a reference conducting surface oriented with respect to the board; measuring a parameter of an electrical response at a node of interest; and comparing the measurements to determine a plurality of nets among the nodes. The tentative net list developed from the measured parameters is then verified using continuity testing.
    Type: Grant
    Filed: August 30, 1991
    Date of Patent: February 16, 1993
    Assignee: Compaq Computer Corporation
    Inventors: James E. Marek, Douglas A. Goss
  • Patent number: 5175504
    Abstract: Circuit panels, such as LCD panels, are inspected in-process and after final assembly to identify defects. Prior to final assembly, panels identified as having sufficiently few defects are repaired. Similarly after final assembly, panels identified as having sufficiently few defects are repaired. The inspection and repair systems are linked through a repair file. The inspection system identifies each defect by type and location and includes such information in the repair file. The repair system accesses such file and follows a prescribed repair method for a given type of defect at the location of such defect. Simple matrix panel defects include open line defects and line to line shorts. The inspection system includes an automated non-contact capacitance imaging system. The repair system may include a pair of lasers and a film dispenser. A first laser is used to selectively remove material and cut lines. The dispenser is for applying a liquid organic metallic film in the defect area.
    Type: Grant
    Filed: June 17, 1991
    Date of Patent: December 29, 1992
    Assignee: Photon Dynamics, Inc.
    Inventor: Francois J. Henley
  • Patent number: 5150058
    Abstract: The voltage potential and E-Field occurring at the site of a circuit discontinuity is detected by capacitively coupling and actuating an annunciator responsive to an above threshold energy level.
    Type: Grant
    Filed: May 15, 1989
    Date of Patent: September 22, 1992
    Inventor: Michael J. Johnson
  • Patent number: 5097213
    Abstract: An apparatus for automatically testing multipin connectors is disclosed. A carrier frame contains connector cells of different configurations. Multiple groups of pins of the connector are connected together and to a source of high voltage. The resulting leakage current between energized pins and a remaining unenergized pin may be measured and compared with various stored test parameters. When the on-board computer detects a current which does not meet the stored test parameters, an error message is posted and displayed and also passed to a host computer connected to the on-board computer for storage and display.
    Type: Grant
    Filed: May 24, 1990
    Date of Patent: March 17, 1992
    Inventors: Curtis J. Hunting, Donald L. Patts, Brian J. Hunting
  • Patent number: 5088325
    Abstract: A system for indicating level of material in a vessel as a function of material capacitance includes a capacitance probe adapted to be positioned so as to be responsive to variations in capacitance as a function of material level in the vessel. Detection circuitry is responsive to capacitance at the probe and to a reference signal for indicating material level, and includes facility for selectively adjusting sensitivity of the detection circuitry to material capacitance so as to adapt the system for materials of differing capacitance characteristics. Calibration circuitry for establishing the reference signal includes facility for varying operating characteristics of the detection circuitry during a calibration mode of operation independent of material level so as to calibrate the detection circuitry to capacitance at the probe.
    Type: Grant
    Filed: February 11, 1991
    Date of Patent: February 18, 1992
    Assignee: Bindicator Company
    Inventors: Robert T. Eichberger, Scott M. Hewelt
  • Patent number: 4881072
    Abstract: A device for remote metering, comprising a meter (4) for measuring a consumption, a transmission circuit for transmitting information relating to quantities consumed, and consisting essentially of a modulating circuit (5,6) and of a bifilar line (3), and a counter circuit for counting sets of information. The modulating circuit comprises a capacitive network (6) and at least one switch (5) which is actuated by the meter and which is capable of modifying the capacity of the capacitive network. The device further comprises a circuit (7,14) suitable for evaluating the value of the capacity of the transmission circuit, and thus for distinguishing two states of the modulating circuit and one state of a fault in the line. Such a device is, in particular, usable for the remote metering of a consumption of gas or of electricity.
    Type: Grant
    Filed: March 9, 1987
    Date of Patent: November 14, 1989
    Assignees: Electricite de France, Service National and Enertec
    Inventor: Alain Carnel
  • Patent number: 4870365
    Abstract: At least a pair (4) or a band of wires of an electrically conducting material is longitudinally embedded in the fiber composite material forming the building element (2) and firmly secured to the fiber composite material over the whole length of the wires. A weak current source (7) is connected to the free ends of the wires. The current conduction is then monitored, the capacitance is measured or the current conduction and the capacitance are measured.
    Type: Grant
    Filed: September 2, 1987
    Date of Patent: September 26, 1989
    Inventor: Lutz Franke
  • Patent number: 4820991
    Abstract: An improved instrument for determining the distance to an open fault in a communications line, the instrument taking advantage of the predictable relationship between the current discharge rate in a reference capacitor and resistor and the current discharge rate in a faulty line whose capacitance is a function of the distance to the fault. Provisions are made to keep the meter readings within the usable scale of the meter of the invention by allowing the operator to select from among a range of driving signal frequencies to suit the distance to the fault. Calibration may be made by reference to an internal capacitor or by means of measuring a known length of open circuited line of the type to be tested. Provision is also made to provide for "tuning out" "dirty" short circuits.
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: April 11, 1989
    Assignee: Progressive Electronics, Inc.
    Inventor: Brian D. Clark
  • Patent number: 4812752
    Abstract: A circuit tester provides an indication of open circuit faults of individual conductors in cables. An oscillator circuit in the tesster includes a capacitance as an internal part of the circuit. Test probes connect conductor pairs to the oscillator circuit, thus changing the effective capacitance of the circuit. This changes the frequency output of the oscillator in accordance with the length of the conductors. Test indications may include a low pass filter and an audio circuit, or a circuit to convert frequency to a voltage or digitalized output. The tester may be used with automated test equipment.
    Type: Grant
    Filed: October 19, 1987
    Date of Patent: March 14, 1989
    Assignee: Allied-Signal Inc.
    Inventor: Ernest A. Preuss
  • Patent number: 4785234
    Abstract: Disclosed is an apparatus for determining the eccentricity of insulation on an elongated conductor comprising two flat parallel opposing electrodes positionable on opposite sides of an insulated conductor in physical contact with the insulation of the conductor, means for moving one of the two electrodes relative to the other in a direction parallel to the electrodes, whereby the insulated conductor is rotated therebetween, electrical contact means for making electrical contact to the conductor, means for translating the electrical contact means at the same rate that the insulating conductor is translated between the two flat opposing electrodes, and electrical means for determining the ratio of the capacitance of each of the two electrodes to the conductor as the insulating conductor is rotated between the two electrodes.
    Type: Grant
    Filed: June 15, 1987
    Date of Patent: November 15, 1988
    Assignee: Westinghouse Electric Corp.
    Inventors: Dean C. Westervelt, Allan I. Bennett
  • Patent number: 4734651
    Abstract: Electrical continuity between the terminals of a multi-contact electrical connector and the cores of insulated leads that have been connected thereto, is tested for by engaging a respective electrical test probe with each of the terminals and using a multiplexer to connect each test probe in turn to a continuity testing circuit, under the control of a computer. Following the continuity test, a bank of analog switches also controlled by the computer is used to apply short circuit test electrical potential to energize selected terminals, and the presence of the test potential on adjacent unenergized terminals is tested for by the computer, to detect short circuiting between the terminals.
    Type: Grant
    Filed: June 30, 1986
    Date of Patent: March 29, 1988
    Assignee: AMP Incorporated
    Inventors: Joseph R. Keller, Michael D. Strong