Tracing Test Signal To Fault Location Patents (Class 324/528)
  • Patent number: 11061135
    Abstract: A method for detecting a buried non-conductive pipe includes transmitting, by a radio frequency (RF) transmitter, guided RF energy through one end of the non-conductive pipe, receiving, by a RF receiver, electromagnetic signals due to RF energy leaks in one or more locations along the non-conductive pipe, and processing, by one or more processors, the received signals to determine a location of the non-conductive pipe. A system for detecting a buried non-conductive pipe includes a RF transmitter configured to transmit guided RF energy through one end of the non-conductive pipe, a RF receiver configured to receive electromagnetic signals due to RF energy leaks in one or more locations along the non-conductive pipe, and one or more processors configured to process the received signals to determine a location of the non-conductive pipe.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 13, 2021
    Assignee: Heath Consultants Incorporated
    Inventors: Ben Allen Abbott, Donald R. Poole
  • Patent number: 10055515
    Abstract: A probe is adapted to send a signal over a selected circuit and to provide circuit information. One or more modules have a connector for electrically connecting to an outlet, logic interconnected with the connector for detecting the signal and receiving the circuit information, and an indicator interconnected with the logic for presenting the circuit information in response to the signal. A computer is operably associated with the probe and configured to execute a program of instructions to provide a breaker box representation and an electronic record of one or more rooms showing outlet symbols that identify the location of outlets. The computer is configured to execute the program of instructions to collect the circuit information from the one or more modules and to associate the circuit information with a corresponding breaker on the breaker box representation and on outlet symbols on the electronic record of one or more rooms.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey A. Calcaterra, Humberto Gutierrez-Rivas, Steven M. Miller
  • Patent number: 9983608
    Abstract: An output module for programmable controller includes an output common output circuit that supplies load current to each of the load output circuits, and the control circuit controls ON/OFF of the output common output circuit in accordance with an instruction from the higher-level device.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 29, 2018
    Assignee: FANUC CORPORATION
    Inventor: Masashi Yamanaka
  • Patent number: 9488689
    Abstract: A fault location system for locating a fault in a power distribution system is provided. The fault location system includes a grounding resistor assembly configured to generate, in response to detection of the fault, a tracing signal that alternates between on periods and off periods, and a plurality of power distribution networks, wherein a first power distribution network of the plurality of power distribution networks is configured to receive a synchronizing message that includes a timing for the on periods and the off periods, measure, based on the synchronization message, a current through the first power distribution network to attempt to detect the fault, broadcast a fault detection message to all other power distribution networks of the plurality of power distribution networks when the fault is detected at the first power distribution network, and determine whether the first power distribution network is the location of the fault.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: November 8, 2016
    Assignee: General Electric Company
    Inventor: John James Dougherty
  • Patent number: 9389272
    Abstract: Method for detecting an electric are in a photovoltaic device by ultrasound, comprising measuring at least one parameter among the amplitude, the duration and the central frequency, of an electrical signal received by an ultrasound sensor; and comparing the measurement of this at least one parameter of the electrical signal with predefined values in order to determine whether the measurement corresponds to that of an electric arc.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: July 12, 2016
    Assignee: Commissariat a L'energie Atomique et aux Energies Alternatives
    Inventors: Nicolas Chaintreuil, Pierre Perichon, Sandrine Vallet
  • Patent number: 9030206
    Abstract: In a process plant, a first series of measurements from a coupling interface are received. The first series of measurements are stored. A second series of measurements from a coupling interface are received. The second series of measurements. The first series and second series of measurements are compared. An indication of loss of clamping force is generated if the first series of measurements deviates from the second series of measurements.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: May 12, 2015
    Assignee: Fisher Controls International LLC
    Inventor: Shawn W. Anderson
  • Patent number: 8912802
    Abstract: In a component-embedded circuit substrate having a plurality of capacitors embedded therein, the capacitors are connected in parallel, inspection electrodes are formed, and the inspection electrodes connect to respective terminal electrodes of the capacitor through via conductors. At the terminal electrodes of the capacitor, the connection position of the via conductors for connecting the inspection electrodes differs from the connection position of via conductors for connecting respective terminal electrodes of the capacitor.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: December 16, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Shigeo Sakurai, Tetsuo Saji
  • Patent number: 8803530
    Abstract: A method of determining the location of a fault in a cable at an underwater fluid extraction facility is provided. The method comprises: providing a time domain reflectometry unit at the facility, the unit being connected to at least one wire within the cable; causing the unit to transmit a current pulse to the wire; detecting a reflected pulse received at the unit; determining the time duration between the pulse transmission and the reflected pulse reception and using the duration to calculate a distance between the fault and the unit; and determining the location of a fault on the wire using the calculated distance.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: August 12, 2014
    Assignee: Vetco Gray Controls Limited
    Inventor: Martin Stokes
  • Patent number: 8762081
    Abstract: A method for locating partial discharges occurring at a discharge site (2) in an electric apparatus (3) with elongate geometry and generating corresponding electric pulses (4) propagating in opposite directions along the apparatus (3) from the discharge site (2) comprises the steps of detecting (11) the electric pulses (4) picked up by a first and a second sensor (5, 7), operatively connected to the apparatus (3) and spaced out along it, and generating corresponding electric signals representative of the waveform of the pulses (4), selecting (12) at least one pair of signals, detected in the consecutive sensors (5, 7), and representative of a pair of homologous pulses (4), relating to the same partial discharge and propagating in opposite directions along the apparatus, deriving, for the signals of the selected pair of homologous pulses (4), at least one attenuation parameter, correlated with a quantity that is variable depending on the distance travelled by the pulses (4), calculating (13) the distance betwe
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: June 24, 2014
    Assignee: Techimp Technologies S.R.L.
    Inventors: Stefano Serra, Andrea Cavallini, Gian Carlo Montanari, Gaetano Pasini
  • Patent number: 8752108
    Abstract: A system and method for detecting and geo-locating signal ingress interferences in a cable distribution network comprising a head station for transmitting content to subscribers at frequencies within a network bandwidth. The system comprises a vehicle mounted geo-locating device for generating geo-location data indicating the geographical position of a vehicle, and a vehicle mounted transmitter for transmitting a radio-frequency signal comprising said geo-location data at a frequency within the network bandwidth as the vehicle travels within the geographical area of the network. If an ingress exists in the network, the ingress signal sent from onboard the vehicle would leak into the network to be received and detected by a receiver at the head station of the cable distribution network. A server is used to process the data extracted by the receiver to produces reports and maps reflecting ingress points in a geographical area.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: June 10, 2014
    Inventor: Magella Bouchard
  • Patent number: 8749248
    Abstract: Signal egress from a shielding flaw in a cable telecommunication system is detected, even where signals carried by the cable telecommunication system are quadrature amplitude modulated signals that statistically resemble broadband noise by generating a marker signal comprising a double side band, suppressed carrier signal in the fringes of contiguous frequency bands and at a power level which cannot cause perceptible interference with signals in those contiguous frequency bands. The separation of the sidebands comprising the marker signal can unambiguously identify the marker signal and can distinguish between different cable telecommunication systems installed in the same geographic area. The marker signal can be additionally coded by varying the frequency and/or amplitude of the modulating signal used to create the marker signal.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: June 10, 2014
    Assignee: ConSonics, Inc.
    Inventors: John J. Murphy, Dennis A. Zimmerman
  • Patent number: 8729905
    Abstract: This invention relates to a method of detecting faults on an electrical power line (7) and a sensor (5) for use in such a method. Preferably, the sensor is a line-mounted sensor (5). The method comprises the initial step of determining an initial impedance profile for the power line (7), and thereafter the method comprises the subsequent steps of the line-mounted sensor (5) transmitting a conducted communication signal (41) along the power line, receiving a reflected signal (43) particular to the transmitted communication signal and correlating the transmitted signal and the reflected signal. By correlating the signals, it is possible to determine the actual impedance of the power line. The actual impedance of the power line may then be compared with the initial impedance profile and it is possible to ascertain whether a fault exists on the power line. Preferably, the method uses an adaptive filter to determine the location of the fault.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: May 20, 2014
    Assignee: General Electric Company
    Inventors: Michael Anthony McCormack, Charles Brendan O'Sullivan
  • Patent number: 8669767
    Abstract: Aspects of the present disclosure provide for a cable tester that tests a cable to determine the cable length. The cable tester can include a clock generator that generates a clock that has clock period that is a multiple of the data symbol period and a signal generator that injects the training signal, which can be synchronous with the clock, into the cable. The cable tester can also include a receiver that samples the returned signal from the cable and adaptively filters the returned signal based on the training signal and a controller that determines the cable length from the adaptive filter tap coefficients.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: March 11, 2014
    Assignee: Marvell International Ltd.
    Inventors: Ozdal Barkan, William Lo, Tak-Lap Tsui
  • Patent number: 8560991
    Abstract: Embodiments provide systems, devices, methods, and machine-readable medium for automated debugging of a design under test in a verification environment as part of electronic design automation. Embodiments may automatically identify inputs that are relevant to a bug for a device under test. A failing test run may be taken and rerun several times with small changes in the inputs. If the test is passing, the mutated inputs may be important to reproduce the bug and may be marked as “suspicious”. The result of this process may be a list of suspicious inputs and a shorter and simpler test that still fails. The shorter test may be rerun and fields of the inputs recorded. New tests may be created with mutated fields. Mutated fields that result in passing tests may be considered suspicious fields. Suspicious inputs and fields may be presented to a user as part of an electronic design process.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: October 15, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventor: Shai Fuss
  • Patent number: 8552709
    Abstract: Systems and methods presented herein locate and/or identify a circuit within an electrical system. In one embodiment, a transmitter is configured for inducing signals upon a plurality of circuit lines (e.g., power lines, communication lines, lighting circuits, etc.) with each circuit line having a unique signal to identify it from other circuit lines. Each signal may be induced upon an individual circuit line by a inductive coupling clip coupled about the circuit line. The transmitter may be used at a distribution point of the circuit lines, such as circuit breaker box. A receiver can then receive a signal from a distal point on the circuit line to acquire the unique signal induced thereon and identify determine which inductive coupling clip is coupled thereto. For example. the signal may be decoded to display a number of the circuit line being tested.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: October 8, 2013
    Assignee: Tasco Inc.
    Inventors: Steven Thomas McCasland, Thomas A. McCasland
  • Patent number: 8548760
    Abstract: An apparatus and a method for detecting a nonlinearity in a cable plant and for determining cable length to a source of the nonlinearity are disclosed. Upstream signal peaks are detected by averaging upstream signal waveforms. The upstream signal peaks are generated at the source of the nonlinearity from naturally occurring downstream signal peaks propagating in the cable plant. The downstream signal peaks occur due to constructive superposition of the downstream channel signals. Acquisition of the upstream signal waveforms is triggered by the downstream signal peaks. The cable length to the source of nonlinearity is determined from a time delay between the downstream signal peaks and the upstream signal peaks.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: October 1, 2013
    Assignee: JDS Uniphase Corporation
    Inventor: Daniel K. Chappell
  • Patent number: 8531804
    Abstract: The present invention is implemented by deploying an enhanced ground fault detection and location apparatus and by using the apparatus in conjunction with specific circuit analysis methods, using the information generated by the ground fault detection and location apparatus. The ground fault detection and location apparatus comprises the functionality of a voltmeter, an ammeter, a phase angle meter, a frequency generator, and a variable power supply, thereby providing for a variety of signals and analyses to be performed on a unintentionally grounded circuit in an ungrounded AC or DC power distribution system. The ground fault detection and location apparatus is capable of operating in six different modes, with each mode providing a different capability or opportunity for detecting, analyzing, and locating one or more unintentionally grounded circuits in an normally ungrounded AC or DC power distribution system.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: September 10, 2013
    Inventors: Warren A. Weems, II, Russsell L. Kincaid, Wayne L. Green
  • Patent number: 8525542
    Abstract: A short circuit detection device is provided to check a circuit layout. The circuit layout includes electronic components connected in parallel. Any of the electronic components includes two contacts on the circuit layout. The short circuit detection device includes a determination circuit configured to determine whether a short circuit has occurred in the circuit layout, and a detection circuit configured to determine the specific electronic component or components responsible for the short circuit. The determination circuit connects with one contact of any of the electronic components. The detection circuit connects with two contacts of any of the electronic components.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: September 3, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Jin-Liang Xiong
  • Patent number: 8513952
    Abstract: Aspects of the present disclosure provide for a cable tester that tests a cable to determine the cable length. The cable tester can include a clock generator that generates a clock that has clock period that is a multiple of the data symbol period and a signal generator that injects the training signal, which can be synchronous with the clock, into the cable. The cable tester can also include a receiver that samples the returned signal from the cable and adaptively filters the returned signal based on the training signal and a controller that determines the cable length from the adaptive filter tap coefficients.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: August 20, 2013
    Assignee: Marvell International Ltd.
    Inventors: Ozdal Barkan, William Lo, Tak-Lap Tsui
  • Patent number: 8482291
    Abstract: A substrate includes a first plate member; a plurality of first electrodes provided on the major surface of the first plate member, the first electrodes including at least one electrode for circuit connection and at least one monitor electrode separate from the electrode for circuit connection; a second plate member; a plurality of second electrodes provided on the major surface of the second plate member; a plurality of solder members provided between the first electrodes and the second electrodes for electrical connection therebetween, repeatedly; and a detector for detecting an electrical disconnection between at least one of the monitor electrode and the second electrode.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: July 9, 2013
    Assignee: Fujitsu Limited
    Inventors: Nobutaka Itoh, Makoto Sakairi, Mami Nakadate
  • Patent number: 8395403
    Abstract: A semiconductor device and a defect analysis method of a semiconductor device, in which a failure location can be easily identified. The semiconductor device is provided with at least 2N resistor patterns having a fixed form, and being divided into N groups; the resistor patterns of each group are disposed in parallel, in sequence, and at an equal pitch, so that (N?1) resistor patterns of another group interpose between a resistor pattern of each of the groups and another resistor pattern within the group in question; the resistor patterns of each of the groups is connected in series with other resistor patterns with the group; and the resistor patterns of each of the groups, which are connected in series, are additionally connected in series to resistor patterns of another group. Measuring pads are provided respectively between two ends of resistor patterns that are connected in series, and groups.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: March 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Tomomi Ukai
  • Patent number: 8339272
    Abstract: An arrangement that includes a transmitter unit and a receiver for locating a wire or a circuit interrupter associated with a selected branch circuit of a power distribution system. The transmitter is electrically interconnected with the selected branch circuit and produces a sequence of current pulses in a branch circuit that is to be traced to locate an associated circuit interrupter. Each current pulse is of a predetermined duration, a predetermined rise time, and a predefined fall time, which in one embodiment is equal to the current pulse rise time. The receiver is a handheld unit that is positioned in close proximity with the various circuit interrupters of the power distribution system and provides an indication that the desired wire or circuit interrupter has been located upon detecting current pulses that are with a predefined pulse duration, pulse separation and amplitude.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: December 25, 2012
    Assignee: Fluke Corporation
    Inventor: Michael F. Gallavan
  • Patent number: 8269505
    Abstract: One embodiment provides a method of locating a short circuit in a printed circuit board. Test signals may be injected at different test points on the circuit board. The distance between each test point and the short circuit may be determined according to how long it takes for a signal reflection at the short circuit to propagate back to each test point. The distances between the various test points and the short circuit can be used to narrow the possible locations of the short circuit or even to pinpoint the location of the short circuit.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Moises Cases, Bhyrav M. Mutnury, Terence Rodrigues
  • Patent number: 8253420
    Abstract: A detection circuit and one or more wires or circuit traces are included in a die. The combination is used to detect mechanical failure of the substrate, e.g. silicon after singulation of the dice from the wafer. Failures may be detected at different regions or planes within the die, and the tests may be performed during operation of the packaged die and integrated circuit, even after installation and during operation of a larger electronic device in which it is incorporated. This is especially useful for chip scale packages, but may be utilized in any type of IC package.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: August 28, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventors: Charles Nickel, Katherine Nickel, legal representative, David Lidsky, Seth Kahn
  • Patent number: 8154400
    Abstract: A system includes a plurality of electrical switches. Every switch is associated with at least one monitoring device for detecting the respective switching condition of the switch. All of the monitoring devices are interconnected through a data connection through which the switching conditions of all of the switches are made known to every monitoring device.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: April 10, 2012
    Assignee: Siemens AG
    Inventors: Markus Engel, Harald Karl
  • Patent number: 8154303
    Abstract: Methods are disclosed for identifying and locating points of impairment in a cable plant, such as that used for cable television (CATV). The methods utilize both known characteristics of signals as well as propagation times in free space and within the cable in conjunction with accurate determination of locations at which measurements are taken. The methods can be applied to both RF cable leaks as well as points of ingress of interference.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: April 10, 2012
    Inventors: Ben Maxson, Daniel K. Chappell
  • Patent number: 8143900
    Abstract: Detecting ingress of a transmitted signal into a cable communication system due to a radio frequency signal transmitted from a moving vehicle and interrogation of transmitter location over a separate wireless link provides monitoring of shielding integrity or flaws there in a cable communication system. The location of a shielding flaw may then be precisely located in a closed loop fashion without risking overload of the cable communication system or interference with upstream signaling therein by detecting ingress signal strength and controlling transmitted signal strength while providing a user-perceptible indication of ingress signal strength which is compensated for the control of transmitted signal strength and thus indicates proximity of a hand-held instrument or transmitter to said shielding flaw.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: March 27, 2012
    Assignee: Comsonics, Inc.
    Inventors: Richard L. Shimp, Dennis A. Zimmerman
  • Patent number: 8085517
    Abstract: The present invention is implemented by deploying an enhanced ground fault detection and location apparatus and by using the apparatus in conjunction with specific circuit analysis methods, using the information generated by the ground fault detection and location apparatus. The ground fault detection and location apparatus comprises the functionality of a voltmeter, an ammeter, a phase angle meter, a frequency generator, and a variable power supply, thereby providing for a variety of signals and analyses to be performed on a unintentionally grounded circuit in an ungrounded AC or DC power distribution system. The ground fault detection and location apparatus is capable of operating in six different modes, with each mode providing a different capability or opportunity for detecting, analyzing, and locating one or more unintentionally grounded circuits in an normally ungrounded AC or DC power distribution system.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: December 27, 2011
    Inventors: Warren A. Weems, II, Russsell L. Kincaid, Wayne L. Green
  • Publication number: 20110291661
    Abstract: A method of determining the location of a fault in a cable at an underwater fluid extraction facility is provided. The method comprises: providing a time domain reflectometry unit at the facility, the unit being connected to at least one wire within the cable; causing the unit to transmit a current pulse to the wire; detecting a reflected pulse received at the unit; determining the time duration between the pulse transmission and the reflected pulse reception and using the duration to calculate a distance between the fault and the unit; and determining the location of a fault on the wire using the calculated distance.
    Type: Application
    Filed: May 18, 2011
    Publication date: December 1, 2011
    Inventor: Martin Stokes
  • Patent number: 8050002
    Abstract: A fault determination apparatus includes a housing. The housing includes a circuit board disposed there within. The housing is shaped and dimensioned for non-intrusive placement within an existing electrical system. The circuit board is configured to provide one of a transmitter or a receiver within a fault determination system. A first set of connectors is disposed at a first side of the housing and a second set of connectors disposed at the second end of the housing. The first set of connectors and the second set of connectors are directly connected through the wires provided inside the apparatus while at least one wires under fault monitoring are tapped to the circuit board and configured so as to be electrically coupled to the existing electrical system.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: November 1, 2011
    Assignee: Howard University
    Inventor: Charles J. Kim
  • Patent number: 8044667
    Abstract: An apparatus for detecting failures in an illumination device includes at least two light emitting diodes connected in series. The apparatus includes a first, a second, and a third circuit node for interfacing the illumination device such that the voltage drop across at least two light emitting diodes is applied between the first and the second circuit node and a fraction of the voltage drop is applied between the second and the third circuit node. An evaluation unit is coupled to the first, the second, and the third circuit node and configured to assess whether the electric potential present at the third circuit node is within a pre-defined range of tolerance about a nominal value that is defined as a pre-defined fraction of the potential difference present between the first and the second circuit node.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: October 25, 2011
    Assignee: Infineon Technologies AG
    Inventors: Fabrizio Cortigiani, Andrea Logiudice, Andreas Eder
  • Patent number: 8006156
    Abstract: Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual operation timing of a logical circuit to be tested, ii) logical simulation block performs simulation by using delay times of signal paths corrected by adding minimum slack margin, and iii) when the simulation indicates that an end-side flip-flop cannot acquire data after an expected transition of logical value, masking block generates mask data that masks data held in the end-side flip-flop.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: August 23, 2011
    Assignee: Kawasaki Microelectronics, Inc.
    Inventor: Hiromi Kojima
  • Patent number: 8000519
    Abstract: A method of evaluating an inline inspection recipe compares the capture rate of metal pattern defects in bounding boxes arising from failed electrical test vectors to the capture rate after the bounding box is shifted. A difference between the first and second capture rates indicates whether the inline inspection recipe is valid for capturing killer defects, or if the inline inspection recipe needs to be adjusted. In a particular example, the electrical test vectors are directed at a selected patterned metal layer of an FPGA (M6), and the metal pattern defect data for the selected patterned metal layer is mapped to the bounding box determined by the electrical test vector.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: August 16, 2011
    Assignee: Xilinx, Inc.
    Inventors: Yongjun Zheng, David Mark, Joe W. Zhao, Felino Encarnacion Pagaduan
  • Publication number: 20110140709
    Abstract: One embodiment provides a method of locating a short circuit in a printed circuit board. Test signals may be injected at different test points on the circuit board. The distance between each test point and the short circuit may be determined according to how long it takes for a signal reflection at the short circuit to propagate back to each test point. The distances between the various test points and the short circuit can be used to narrow the possible locations of the short circuit or even to pinpoint the location of the short circuit.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Moises Cases, Bhyrav M. Mutnury, Terence Rodrigues
  • Patent number: 7880476
    Abstract: The present invention provides a new technique for solving the problem of detecting and locating soft faults, such as frays, in electrical conductor wires. This new technique utilizes the nonlinear ferroelectric capacitive properties of piezoelectric ceramic elements, such as PZT, in conjunction with an antenna coil, to realize a tuned antenna receiver circuit with significantly increased reception sensitivity. The present invention consists of a battery powered, hand-held transmitter, with an output terminal for physical connectors, and a battery powered, hand-held receiver. Soft faults are detected and accurately located, to within a half inch distance of the actual soft fault, as the receiver is passed along the path of the electrical conductor wire, by the operator, who determines a reduction or cessation of the visible and audible indicators.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: February 1, 2011
    Inventors: Fiona A. M. McKenzie, Charles S. Richardson
  • Patent number: 7881801
    Abstract: An apparatus (30) that can test external components of a cochlear implant system in a manner that does not require the person conducting the test to have advanced knowledge of the operation of the tested component. The apparatus provides a relatively quick and straightforward answer to the question of whether the component is operative or not. The testing apparatus (30) comprises at least one testing station (32,33,34) for receiving the component to be tested and makes an electrical and/or inductive connection thereto. A testing circuit is adapted to apply at least one test to the component and measure the response of the component to that test. The apparatus (30) compares the response of the component to stored data indicative of the response to the test of at least one equivalent component that is known to be operational and outputs a result of said comparison.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: February 1, 2011
    Assignee: Cochlear Limited
    Inventors: Paul M. Carter, David J. Bull
  • Patent number: 7853848
    Abstract: Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: December 14, 2010
    Assignee: International Business Machines Corporation
    Inventors: Rao H. Desineni, Maroun Kassab, Leah M. Pastel
  • Patent number: 7844873
    Abstract: A fault location estimation system includes single-fault-assumed diagnostic unit nodes; error-observation node basis candidate classification unit; inclusion fault candidate group selection unit; inter-pattern overlapping unit; and multiple-fault simulation checking unit.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yukihisa Funatsu
  • Patent number: 7836366
    Abstract: Among the various embodiments described is a method of detecting defects in a cell of an integrated circuit that analyzes exercising conditions applied to an input of the cell during a capture phase of testing with failed test patterns that produce an indication of a fault and that analyzes the exercising conditions that are applied during a capture phase of testing with observable passing patterns that do not provide an indication of a fault. From the analysis, true failing excitation conditions and passing excitation conditions can be determined and used to identify whether a defect is in the cell or on an interconnect wire of the integrated circuit.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: November 16, 2010
    Inventors: Manish Sharma, Wu-Tung Cheng
  • Publication number: 20100213949
    Abstract: Disclosed are advances in the arts with novel methods and apparatus for detecting faulty connections in an electrical system. Exemplary preferred embodiments include basic, ASIC, AC, DC, and RF monitoring techniques and systems for monitoring signals at one or more device loads and analyzing the monitored signals for determining fault conditions at the device loads and/or at the main transmission lines. The invention preferably provides the capability to test and monitor electrical interconnections without fully activating the host system.
    Type: Application
    Filed: February 22, 2010
    Publication date: August 26, 2010
    Applicant: TRIUNE IP LLC
    Inventors: Ross E. Teggatz, Wayne T. Chen, Brett Smith
  • Patent number: 7779375
    Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for testing logic devices configured across asynchronous clock domains, including a deactivation mechanism for deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto; wherein the deactivation mechanism is configured to permit data capture within the first plurality of latches, and wherein the deactivation mechanism is further configured to permit at-speed data launch from the first plurality of latches to downstream latches with respect thereto during at-speed testing.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gary D. Grise, Vikram Iyengar, Mark R. Taylor
  • Patent number: 7685542
    Abstract: A method for testing logic devices configured across asynchronous clock domains includes deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto. The deactivation of a local clock signal for each of the plurality of latches is implemented in a manner so as to permit data capture within the first plurality of latches, and wherein the deactivation of a local clock signal for each of the plurality of latches is further implemented in a manner so as to permit at-speed data launch therefrom to downstream latches with respect thereto during at-speed testing.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gary D. Grise, Vikram Iyengar, Mark R. Taylor
  • Patent number: 7679371
    Abstract: A cable testing system that tests cable includes a pulse generation module that transmits a first pulse on a first communications channel of the cable. A sampling module waits a predetermined time period after the pulse generation module transmits the first pulse and then detects a first amplitude of a reflected signal on a second communications channel of the cable. A time domain reflection (TDR) module receives the first amplitude and verifies proper operation of the cable based on the first amplitude. The predetermined time period corresponds with an estimated roundtrip propagation delay of the first pulse when the first pulse is reflected back to the cable testing system after traveling a first predetermined distance along the cable. The sampling module incrementally increases the predetermined time period during subsequent iterations of a cable test in order to verify proper operation of a predetermined segment of the cable.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: March 16, 2010
    Assignee: Marvell International Ltd.
    Inventor: William Lo
  • Patent number: 7636903
    Abstract: A method and device for testing an electric circuit, wherein exhaustive electric circuit modulation is not required yet circuit errors can be recognized in a reliable manner is provided. A marking signal is produced, indicating a predefined circuit state that might occur in specific components of an electric circuit, wherein a transformed network list is formed from an original network list describing the circuit, whereby all electric components of at least one predefined component group, with regard to a respective connection pair, are treated as short-circuited, all network nodes connected by one or several components that are to be treated as short-circuited are respectively combined to form an equivalence category, wherein respectively all states of the associated network nodes are assigned to each equivalence category, it is possible to determine whether and in which components the predefined circuit state can occur by taking into account the equivalence categories.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: December 22, 2009
    Assignee: Infineon Technologies AG
    Inventors: Peter Baader, Tilman Neunhoeffer
  • Patent number: 7603243
    Abstract: The invention relates to a method for error location in branched low voltage and medium voltage networks and to an evaluation network used therefor.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: October 13, 2009
    Assignee: Seba-Dynatronic Mess-und Ortungstechnik GmbH
    Inventors: Hubert Schlapp, Frieder Jehring
  • Patent number: 7557723
    Abstract: A system for evaluating at least one tripping stimulus for a ground-fault circuit interrupter includes: a sensing circuit configured to measure a leakage current from a voltage line to ground, wherein the sensing circuit is capable of generating a leakage signal including a voltage representative of the leakage current; and an evaluating circuit configured to evaluate the leakage signal to generate an indication signal, wherein the indication signal includes information corresponding to the at least one tripping stimulus. The sensing circuit may include a circuit substantially similar to at least a portion of a ground-fault circuit interrupter, and the evaluating circuit may include a peak hold circuit. The system may further include an indicator circuit for receiving the indication signal and displaying a status of the tripping conditions.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: July 7, 2009
    Assignee: Ericson Manufacturing Company
    Inventors: Jeffrey Richard Angle, Ronald Wayne Hughes
  • Patent number: 7543198
    Abstract: Reporting and/or analyzing test data from a plurality of tests of an array structure using a data array. One method includes obtaining the test data, and reporting the test data in a data array, which includes at least two portions representing different tests. Data stored in the data array is organized according to a translation table, which describes the locations of data for tests and criteria for data to be analyzed within the data array. Numerous other data arrangements such as a coordinate file listing a pre-defined maximum number of fail points, or a chip report including fail points by chip may also be generated. The data array reports all test data in a more easily generated and stored form, and may be converted to an image. A data analysis method for analyzing data using the data array is also presented.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: June 2, 2009
    Assignee: International Business Machines Corporation
    Inventors: William J. Ferrante, John J. Cassels, Stephen Wu
  • Patent number: 7468871
    Abstract: A residual current device (RCD) protects a circuit by tripping in response to an imbalance signal representative of residual current imbalance in the circuit. The RCD trips the circuit when the imbalance signal exceeds a predetermined threshold rating. The RCD includes a sense coil for generating the imbalance signal and a test coil for introducing a simulation residual current imbalance into the device so as to increase the imbalance signal. A processor monitors the imbalance signal and determines the simulation residual current imbalance required to increase the imbalance signal to a level that corresponds to the predetermined threshold rating so that the sense coil senses the sum of any residual current imbalance in the circuit being protected and the simulation residual current imbalance in order to test operation of the RCD against the predetermined threshold rating.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: December 23, 2008
    Assignee: Eaton Electric Limited
    Inventors: Jonathan Keith Jackson, Andrew Williams
  • Patent number: 7439747
    Abstract: The location of high resistance ground faults within buried co-axial power cables can be detected by transmitting a combined signal along the cable at a primary frequency of 0.718 Hz and a primary amplitude in the order of 4,500 volts peak to peak. This combined signal also has an interlocked secondary frequency of 11,780 Hz superimposed on the primary frequency. The ratio between the reactive impedance and resistive impedance is such as to create a condition where the 0.718 Hz primary frequency's single source caused resistive current is usually larger than the sum or total of all that cable's per foot of length's 0.718 Hz reactive currents. This condition then enables the detection of the resistive ground faults by a manually transported Receiver. When needed the effective resistance and/or capacitance of the cable can be increased by a remote end connection circuit.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: October 21, 2008
    Inventor: Terrence M. Beeman
  • Publication number: 20080255781
    Abstract: A method of performing transducer self-diagnostics and self-healing on an array of sensor transducers bonded to a structure for health monitoring includes measuring impedance to detect whether a transducer is missing, or a connection is damaged. Pitch-catch signals generated between one or more pairs of transducers are analyzed for detecting defects according to selected criteria of defect size and location to determine whether the sensors are damaged or partially/fully disbanded. Based on the resulting map of operational transducers, signal transmission paths are added/extended between additional pairs of transducers to maintain inspection coverage of the structure according to the selected criteria.
    Type: Application
    Filed: February 28, 2008
    Publication date: October 16, 2008
    Inventors: Shawn J. Beard, Chang Zhang, Xinlin Qing