By Applying A Test Signal Patents (Class 324/527)
  • Patent number: 10359465
    Abstract: A method for characterizing a fault affecting a cable in which a reference signal s of limited time support is injected and a measurement r of the reflection of the reference signal s in the cable is taken, comprises the following steps: identifying a section of the measurement r corresponding to a fault, this measurement section being called the signature of the fault; generating a modified reference signal s?, of parameterizable amplitude, equal to the sum of the reference signal s and of the reference signal s inverted and delayed by a parameterizable delay; determining conjointly the values of the parameterizable delay and of the parameterizable amplitude that minimize the error between the modified reference signal s? and the signature of the fault; and deducing therefrom an estimation of the length of the fault from the determined value of the delay.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 23, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Soumaya Sallem, Nicolas Ravot
  • Patent number: 10170199
    Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Harry Barowski, Sheldon Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter
  • Patent number: 10154819
    Abstract: Systems and methods are disclosed for classifying a condition of an entity that includes a conductive medium having multiple conductive paths, using a pattern recognition strategy to classify a signature constructed from impedance-interrogation measurements and optionally including inputs from other informative sources which may be external to the system.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: December 18, 2018
    Inventor: Jack S. Emery
  • Patent number: 10151787
    Abstract: An audible ground fault detection device may include: a pulse-width modulation (PWM) circuit to produce a pulse signal in response to an occurrence of a ground fault; and a buzzer circuit to emit an audible sound in response to receipt of the pulse signal. The device may include a power circuit configured to transfer power from the power line to the PWM circuit when a ground fault occurs in a load of the power line, and not to transfer the power from the power line to the PWM circuit when no ground fault occurs in any load of the power line. When the PWM circuit has no power, it will not produce the pulse signal. The power circuit may also provide DC power to the buzzer circuit in response to the occurrence of the ground fault. The buzzer circuit may include a passive buzzer.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: December 11, 2018
    Assignee: Eaton Corporation
    Inventors: Lin Yang, Tao Xiong, Haidong Zhang, Xianzhen Zhang, Shifang Zhang
  • Patent number: 10109797
    Abstract: A display device includes a display area, a test pad, a plurality of first test transistors, and at least one outline. The display area includes pixels coupled to data lines and scan lines. The test pad receives a test signal. The first test transistors are coupled between the data lines of the display area and the test pad. The at least one outline is coupled between one of the first test transistors and the test pad. The at least one outline is located in a non-display area outside the display area.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Won-Kyu Kwak, Hwan-Soo Jang, Jae-Yong Lee
  • Patent number: 10079070
    Abstract: The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature register (MISR) logically coupled to digital outputs of a CAM, to digital inputs of a RAM, and to digital outputs of an ABIST controller circuit, where the MISR includes a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), each of the outer XOR circuits logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Harry Barowski, Sheldon Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter
  • Patent number: 10026502
    Abstract: A method includes setting a first logical value in a control register provided in a variable delay control circuit that is included in a memory controller, detecting a first stuck-at fault of a second logical value that is a value except for the first logical value, the first stuck-at fault having occurred in one of a plurality of control lines, in accordance with a result of a comparison between a logical value output from the memory controller and an expected value of the logical value, setting the second logical value in the memory controller, and detecting a second stuck-at fault of the first logical value, the second stuck-at fault having occurred in one of the plurality of control lines, in accordance with a result of a comparison between a logical value output from the memory controller and an expected value of the logical value.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: July 17, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Michitaka Hashimoto
  • Patent number: 9971728
    Abstract: A connection system includes a flippable cable connector (7) for connecting wires in a cable (5) to a complementary host connector located at a host device (4), the cable connector having a set of cable terminals and a set of duplicate cable terminals corresponding to the set of cable terminals, and configured to be located symmetrically to the set of cable terminals, so that the connector has 180° rotational symmetry. A particular cable terminal (9) is connected to a particular wire (11) in the cable but the corresponding duplicate cable terminal (12) is not connected to it. The cable connector is connectable to the host connector such that either the set of cable terminals or the set of duplicate cable terminals is connected to host terminals of the host connector. The system includes means (18) for determining an orientation of the cable connector relative to the host connector.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: May 15, 2018
    Assignee: DISPLAYLINK (UK) LIMITED
    Inventor: Peter Alan Burgers
  • Patent number: 9941085
    Abstract: A movable arm is for a movable arm assembly of an electrical switching apparatus. The movable arm assembly includes a first separable contact. The electrical switching apparatus has a housing, an operating handle coupled to the housing, and a second separable contact located internal the housing and being structured to engage the first separable contact. The movable arm includes a first arm member structured to be coupled to the first separable contact; and a second arm member coupled to the first arm member, the second arm member being structured to be coupled to the operating handle. The first arm member is made from a first copper material and the second arm member is made from a second, different copper material.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: April 10, 2018
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Jeffrey Michael Cox, Jeffrey Wayne Lockhart
  • Patent number: 9739822
    Abstract: An input circuit has a plurality of input terminals connected to a plurality of input lines transmitting input signals outputted from a plurality of input signal sources. The input circuit includes a controller which outputs a control signal when performing self-diagnosis of a short-circuit fault between the input lines a pulse circuit which generates pulsed self-diagnosis voltage once, twice or more times based on a control signal of the controller a switch which, when performing the self-diagnosis, applies the pulsed self-diagnosis voltage to any one of the input lines based on the control signal of the controller and a comparing/determining section which, when the self-diagnosis voltage is applied to the any one of the input lines, determines whether the short-circuit fault between the input lines has occurred based on voltage variation in the input line different from the input line to which the self-diagnosis voltage is applied.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: August 22, 2017
    Assignees: DENSO CORPORATION, ADVICS CO LTD
    Inventor: Ken Onodera
  • Patent number: 9699891
    Abstract: A substrate includes a join-structure including a semiconductor package, first electrode pad, bump, second electrode pad, and circuit substrate joined in the order named. The substrate also includes a first wire and a second wire formed in a region below a corner of the semiconductor package. The first and second wires are configured to detect a change in electrical resistance value when the first wire or the second wire is disconnected. One of the first and second wires is connected to the first electrode pad or the second electrode pad. A break strength of each of the first wire and the second wire is lower than a break strength of the join-structure.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: July 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuu Yamayose, Kenji Hirohata
  • Patent number: 9535104
    Abstract: A method of detecting an arc fault in a power circuit includes injecting an AC-signal into the power circuit and measuring a response signal that is related to the injected AC-signal in the power circuit. The method further includes determining a frequency response of the power circuit from the response signal, analyzing the frequency response, and identifying a preferred frequency. A signal related to AC-current flowing in the power circuit within the preferred frequency range is measured and an occurrence of an arc fault in the power circuit is signaled depending on the measured signal. A system for detecting an arc fault is designed to perform a method as described before.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: January 3, 2017
    Assignee: SMA Solar Technology AG
    Inventors: Holger Behrends, Marcel Kratochvil, Markus Hopf, Sebastian Bieniek
  • Patent number: 9465067
    Abstract: A time reversal process for determining a fault location in an electrical power network comprising multi-conductor lines, comprises measuring at an observation point located anywhere along one of the multi-conductor lines, for each of the conductors of the multi-conductor line, respectively a fault-originated electromagnetic transient signal; defining a set of guessed fault locations each having a different determined location in the electrical power network, and each of the guessed fault locations is attributed a same arbitrary fault impedance; defining a network model for the electrical power network, based on its topology and multi-conductor lines electrical parameters capable of reproducing in the network model the electromagnetic traveling waves; and computing for each conductor a time inversion of the measured fault-originated electromagnetic transients signal.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: October 11, 2016
    Assignee: ECOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE
    Inventors: Mario Paolone, Farhad Rachidi-Haeri, Hossein Mahmoudimanesh, Reza Razzaghi, Gaspard Lugrin
  • Patent number: 9341666
    Abstract: A method for establishing at least one fault in connecting lines between electronic connection units and peripheral units, which are independent of one another, includes: outputting a start signal from the control unit to a first of the connection units, to start the establishment of the fault; applying a test signal to an interface of a first one of the connection units, the application of the test signal being monitored and/or controlled by a non-volatile first algorithm of the first connection unit; registering a cross-coupling of the test signal to an interface of a second connection unit and storing a fault value representing the cross-coupling in a first register, the registration and the storage of the fault value being monitored and/or controlled by a nonvolatile second algorithm of the second connection unit.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: May 17, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventors: Timo Weiss, Matthias Siemss, Jochen Widmaier, Guenter Weiss
  • Patent number: 9285427
    Abstract: A testing apparatus and a testing method of an electronic device are provided. The testing apparatus includes at least two device transfer plates and a testing circuit. The device transfer plates are electrically and respectively connected to corresponding electronic devices and at least two sockets corresponding to the electronic devices. The testing circuit is electrically connected to the device transfer plates respectively through at least two sets of serial signal wire pairs. According to types of the electronic devices, the testing circuit provides a serial signal to one of the device transfer plates through the corresponding serial signal wire pair and receives a response from another one of the device transfer plates through the corresponding serial signal wire pair, so as to test whether an open circuit is occurred to a bus between the electronic devices respectively corresponding to the device transfer plates.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: March 15, 2016
    Assignee: Wistron Corporation
    Inventors: Wen-Hwa Luo, Kuan-Han Chen, Chih-Sheng Liao
  • Patent number: 9250285
    Abstract: Detection and location of electrical faults in a network of metal structures which can receive electric cables and allow return of current by the cables. The reflectometry-based method involves injecting a probe signal into a cable coupled to the structures and analyzing the signal reflected by the anomalies. A conductive element is provided for carrying the probe signal at a constant distance from each structure. In one aspect, an insulated conductive element is arranged inside the metal structure and is built into a longitudinal groove in a surface for receiving a longitudinal plastic holder wedged into the structure. The reflected signal from the conductive element is compared to a threshold above which an anomaly is detected, and the anomaly is located by topological correlation. The invention is useful for airplane raceways having a composite skin.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: February 2, 2016
    Assignee: Airbus Operations (S.A.S.)
    Inventor: Gilles Millet
  • Patent number: 9057752
    Abstract: A power circuit configured to generate and distribute DC electrical power, the power circuit includes a photovoltaic (PV) system that includes an array of PV modules electrically coupled to a combiner box, and an inverter positioned to receive DC electrical power from the array of PV modules and output AC electrical power. The PV system also includes a signal generator coupled to a first portion of the PV system, and a signal detector coupled to a second portion of the PV system, the signal detector configured to detect secondary signals generated at a loose connection of an electrical joint in the PV system, wherein the secondary signals result from a signal generated by the signal generator.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: June 16, 2015
    Assignee: Eaton Corporation
    Inventors: Charles John Luebke, Xin Zhou, John J. Shea, Birger Pahl, B. Thomas Pier
  • Patent number: 9030225
    Abstract: An over voltage protection testing apparatus is applied for testing an over voltage protection function of a power supply apparatus. The over voltage protection testing apparatus mainly includes a voltage boost-storage unit and an energy release unit. The voltage boost-storage unit boosts an original output voltage outputted from the power supply apparatus into a testing voltage. Therefore, no extra testing voltage source is required for testing the over voltage protection function of the power supply apparatus. Moreover, the extra energy would be released to the energy release unit after the testing of the over voltage protection function of the power supply apparatus is finished. Therefore, the energy releasing of the present invention is faster than the energy releasing of a related art.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: May 12, 2015
    Assignee: Chicony Power Technology Co., Ltd.
    Inventors: Chih-Ching Huang, Jhen-Siang Huang, Wen-Nan Huang, Shiu-Hui Lee
  • Patent number: 9021086
    Abstract: System and methods for inferring network topology are described, including a method comprising determining a normalized transmit power of a first device, identifying a second device based upon a parameter of the second device and the normalized transmit power of the first device, and generating a topology including the first device and the second device based upon at least one of the normalized transmit power of the first device and the parameter of the second device.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: April 28, 2015
    Assignee: Comcast Cable Communications, LLC
    Inventors: Lawrence Wolcott, Justin Riggett, Bryan Johnston
  • Patent number: 8996323
    Abstract: A method of assessing an electrical power distribution system includes establishing a baseline signature for one or more points in the power distribution system and assessing the power distribution system using the baseline signatures. Establishing the baseline signatures includes injecting one or more input signals (for example, a tone) at one or more injection points in the power distribution system, sensing one or more output signals at one or more sensing points in the power distribution system, and establishing a baseline signature for one or more of the points based on one or more of the output signals.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: March 31, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Osvaldo P. Morales, Michael P. Czamara
  • Patent number: 8981791
    Abstract: A method, apparatus and software related product are presented for adaptive frequency-domain windowing to determine a time-domain crosstalk in a cable and produce effective TDX plots regardless of the frequency of a worst NEXT (near-end crosstalk). An adaptive window such as a low pass or pass band window may be selected based on the frequency of a measured worst NEXT margin for each pair combination.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: March 17, 2015
    Assignee: Fluke Corporation
    Inventor: Peter Q. Oakley
  • Patent number: 8963573
    Abstract: According to an example implementation, a universal tester includes a host interface slot connected to a first pluggable host card during an electrical test mode of operation to provide a stressed electrical signal to a host under test. The host interface slot is connected to a second pluggable host card during an optical test mode of operation, the second pluggable host card including an electrical-optical conversion block to convert a stressed electrical signal to a stressed optical signal that is provided to a host under test. A stressor generator may operation in pass-through mode or a loop-back mode.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 24, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: D. Brice Achkir, Marco Mazzini, Stefano Riboldi, Cristiana Muzio
  • Publication number: 20150015269
    Abstract: One embodiment of the present invention sets forth a method for detecting defective solder balls that includes configuring a transmitter pad to transmit a pulse signal, transmitting the pulse signal, configuring transmitter pad to receive a pulse reflection, receiving a pulse reflection, analyzing the pulse reflection; and determining whether the pulse reflection is indicative of a defective solder ball. One advantage of the disclosed method is that solder ball defects may be detected more accurately than in the trial and error approach.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: Hans Wolfgang SCHULZE, Cameron BUSCHARDT
  • Patent number: 8912802
    Abstract: In a component-embedded circuit substrate having a plurality of capacitors embedded therein, the capacitors are connected in parallel, inspection electrodes are formed, and the inspection electrodes connect to respective terminal electrodes of the capacitor through via conductors. At the terminal electrodes of the capacitor, the connection position of the via conductors for connecting the inspection electrodes differs from the connection position of via conductors for connecting respective terminal electrodes of the capacitor.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: December 16, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Shigeo Sakurai, Tetsuo Saji
  • Patent number: 8896318
    Abstract: Disclosed are advances in the arts with novel methods and apparatus for detecting faulty connections in an electrical system. Exemplary preferred embodiments include basic, ASIC, AC, DC, and RF monitoring techniques and systems for monitoring signals at one or more device loads and analyzing the monitored signals for determining fault conditions at the device loads and/or at the main transmission lines. The invention preferably provides the capability to test and monitor electrical interconnections without fully activating the host system.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: November 25, 2014
    Assignee: Triune IP LLC
    Inventors: Ross E. Teggatz, Wayne T. Chen, Brett Smith
  • Patent number: 8841974
    Abstract: A method and apparatus is disclosed herein for testing of multiple ring oscillators. In one embodiment, the apparatus comprises at least one ring oscillator structure having a ring oscillator having an inverter chain with an odd number of inverters connected back-to-back and operable to produce an oscillatory output, and a test structure coupled to provide either an observability chain input or a test input to the ring oscillator and to receive the oscillatory output as a feedback from the ring oscillator.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: September 23, 2014
    Assignee: Silicon Image, Inc.
    Inventors: Chinsong Sul, Hyukyong Kwon, Andy Ng
  • Publication number: 20140253140
    Abstract: An electrosurgical generator includes primary and test sources. The primary source supplies a primary signal and the test source supplies a test signal. The electrosurgical generator includes an output circuit and an abnormality detection circuit. The output circuit is electrically coupled to the primary and test sources. The output circuit receives the primary and test signals from the primary and test sources, respectively. The output circuit is electrically coupled to a load to supply the primary signal thereto. The abnormality detection circuit is electrically coupled to the output circuit to detect an abnormality therein as a function of the test signal. The abnormality detection circuit can also determine a location of the abnormality within the output circuit.
    Type: Application
    Filed: January 3, 2014
    Publication date: September 11, 2014
    Applicant: COVIDIEN LP
    Inventor: JAMES A. GILBERT
  • Patent number: 8829916
    Abstract: In one embodiment, the method for locating a defect in a wired transmission line, which extends between a first end and a second end, includes measuring a first modified noise signal at the first end by a first measuring unit, and making a first representation of the first modified noise signal. A second modified noise signal is measured at the second end by a second measuring unit, and a second representation of the second modified noise signal is made. The location of the defects are derived from the representations.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: September 9, 2014
    Assignee: Alcatel Lucent
    Inventors: Frank Cyriel Michel Defoort, Danny Van Bruyssel
  • Patent number: 8809073
    Abstract: A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Victor Chih Yuan Chang, Min-Chie Jeng
  • Patent number: 8773140
    Abstract: A system for inspection of electrical circuits including a calibration subsystem operative to apply a time varying voltage to an electrical circuit being inspected during calibration and to sense differences in an electrical state at various different locations in the electrical circuit being inspected, thereby providing an indication of location of defects therein.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: July 8, 2014
    Assignee: Photon Dynamics, Inc
    Inventors: Sam-Soo Jung, Raul Martin
  • Patent number: 8749248
    Abstract: Signal egress from a shielding flaw in a cable telecommunication system is detected, even where signals carried by the cable telecommunication system are quadrature amplitude modulated signals that statistically resemble broadband noise by generating a marker signal comprising a double side band, suppressed carrier signal in the fringes of contiguous frequency bands and at a power level which cannot cause perceptible interference with signals in those contiguous frequency bands. The separation of the sidebands comprising the marker signal can unambiguously identify the marker signal and can distinguish between different cable telecommunication systems installed in the same geographic area. The marker signal can be additionally coded by varying the frequency and/or amplitude of the modulating signal used to create the marker signal.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: June 10, 2014
    Assignee: ConSonics, Inc.
    Inventors: John J. Murphy, Dennis A. Zimmerman
  • Patent number: 8742766
    Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
  • Patent number: 8700551
    Abstract: The present invention is directed towards systems and methods for predicting one or more desired properties of external nodes or properties of their relations with internal nodes, based on a selected group of nodes about which it is known whether the nodes have the desired properties, or it is known whether they have a desired relation property with an internal node. The method comprises storing in one or more data structures a first data set regarding external nodes and a second data set regarding nodes with known properties in a selected group, each data set having one or more data items representing one or more events relating to or attributes of each node in the data set, the second data set including one or more types of data items not included in the first data set.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: April 15, 2014
    Assignee: Venture Lending & Leasing VI, Inc.
    Inventors: Yaacov Shama, Tal Segalov, Ehud Ben-Reuven, Evgeny Drukh, Uri Sternfeld
  • Patent number: 8633705
    Abstract: Embodiments of methods and apparatuses for characterizing an electrical power distribution system are disclosed. One method includes applying, by at least one test/response unit, at least one test signal to at least one test point of the system, measuring, by a plurality of test/response units, a plurality of response signals at a plurality of test points, wherein the plurality of response signals are generated in response to the at least one test signal, and characterizing the system based on the plurality of response signals.
    Type: Grant
    Filed: March 17, 2013
    Date of Patent: January 21, 2014
    Inventors: Bertrand M. Hochwald, Thomas L. Marzetta
  • Publication number: 20140009296
    Abstract: A test apparatus for testing for short circuits in electrical wiring comprises an emission apparatus and a detection apparatus. The emission apparatus provides a test signal into the electrical wiring, where the test signal is adjustable both for frequency and amplitude. An electromagnetic field is generated in and around the wiring under test. The detection apparatus amplifies strength of magnetic fields found, and detects electromagnetic fields caused by the test signal in a circuit loop. When a signal confirming detection drops suddenly in strength by more than a predetermined threshold, a point or portion of the wiring under the detector is established as a point of short circuit.
    Type: Application
    Filed: July 4, 2013
    Publication date: January 9, 2014
    Inventors: JIA LI, JUN LI
  • Patent number: 8620605
    Abstract: A method for detecting and determining a position of faults using reflectometry in a wired electrical network including: injecting a test signal e(t) into a cable in the electrical network, a timing of successive injections being controlled by a synchronization module that generates an emission clock signal and a reception clock signal; retrieving a reflected signal on the cable; sampling the reflected signal at a frequency Fe=1/Te, where Te is a sampling period; counting a number of samples obtained for the reflected signal and comparing the number of samples obtained with a number n predefined as a function of a length of the cable or the electrical network to be diagnosed, where n is an integer; repeating the injecting, the sampling, and the counting steps N times, shifting the emission clock signal by a duration ?; reconstituting the reflected signal from n*N samples obtained; and analyzing the reconstituted reflected signal to detect a fault.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: December 31, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Julien Guilhemsang, Fabrice Auzanneau, Yannick Bonhomme
  • Patent number: 8618811
    Abstract: An arc fault circuit interrupter test circuit is disclosed. The test circuit incorporates a controller along with at least one power transistor, a current sense circuit and a voltage sense circuit. When the power transistor is operated, the current flowing through the transistor is sensed, and if the current is not at least equal to a threshold value, the voltage at which the power transistor is operated is increased.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: December 31, 2013
    Assignee: Unique Technologies, LLC
    Inventors: Kerry Berland, Paul Berland, Mitch Budniak
  • Patent number: 8604798
    Abstract: A short circuit detection module for a touch panel includes first and second short circuit detection circuits. The first short circuit detection circuit is coupled to a first conductive line of the touch panel. The first short circuit detection circuit is configured to drive the first conductive line with a first signal having a first logic level. The second short circuit detection circuit is coupled to second, adjacent, conductive line of the touch panel. The second short circuit detection circuit is configured to drive the second conductive line with a second signal having a second logic level that is complementary to the first logic level.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: December 10, 2013
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Anthony Junior Casillan, Yannick Guedon, Dianbo Guo
  • Patent number: 8604799
    Abstract: A method for determining damaged faulty and/or weak points in a structural seal. The seal is provided with an electrically conductive layer arranged inside or outside the structural seal and extends over substantially the entire surface of the structural seal and to which layer an electrical test voltage is applied. To establish the damaged, faulty and/or weak points, a further electrically conductive layer is used, which is electrically separated from the aforementioned electrically conductive layer by the structural seal and extends over substantially the entire surface of the structural seal. The level of the test voltage between the electrically conductive layers charged with voltage is selected such that when at least one electrically non-conductive damaged, faulty and/or weak point is present in the structural seal, the electrical disruptive strength is exceeded and an electric spark or arc is formed at the location of the damaged, faulty and/or weak point.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: December 10, 2013
    Assignee: Progeo Monitoring GmbH
    Inventors: Andreas Rödel, Norbert Komma
  • Patent number: 8598886
    Abstract: Apparatus for detecting faults in the delivery of electrical power to electrical loads, includes a plurality of load electrical connections arranged to deliver electrical power from an electrical power source to each of a plurality of electrical loads, a plurality of electrical switches, each connected to an associated one of the load connections, and a diagnostic device operable to detect a short circuit fault in the apparatus, wherein the diagnostic device is operable to apply a diagnostic procedure to detect a short circuit connection between at least two of the load electrical connections and includes a control logic unit operable to apply to each of the electrical switches in turn a test control signal causing operation of the switch to apply a test electrical signal to each of the load electrical connections in turn; and detector means connected to the load electrical connections and operable, while the test electrical signal is applied in turn to each load electrical connection, to detect whether a cor
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: December 3, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kamel Abouda, Stephanie Creveau-Boury, Murielle Delage, Pierre Turpin
  • Patent number: 8599910
    Abstract: Provided is a jitter injection apparatus that injects jitter into a signal, comprising: a plurality of jitter injecting sections that are provided in series in a transmission path that propagates the signal; an output section that selects the signal that is passed from a jitter injecting section at a first stage through a designated jitter injecting section, and outputs the selected signal; and a plurality of branch-path jitter injecting sections that (i) are provided in a plurality of branch paths that propagate the signal output by each jitter injecting section from the transmission path to the output section and (ii) are relays having frequency characteristics of attenuating a high-frequency band more than a low-frequency band.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: December 3, 2013
    Assignee: Advantest Corporation
    Inventors: Kenichi Nagatani, Takayuki Nakamura
  • Patent number: 8570049
    Abstract: AC shield continuity for shielded twisted pair structured datacomm cable is determined by testing the cable, driven in a common mode, over a range of frequencies, to determine presence and location of shield breaks. DC ground path generated false results are thereby avoided.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: October 29, 2013
    Assignee: Fluke Corporation
    Inventors: Jeffrey Sandsmark Bottman, Jun Ho Yi
  • Patent number: 8552734
    Abstract: The integrated circuit (10) has an internal power supply domain with a power supply voltage adaptation circuit (14) to adapt the power supply voltage in the power supply domain. Typically, a plurality of such domains is provided wherein the power supply voltage can be adapted independently. During testing an internal power supply voltage is supplied to a temporally integrating analog to digital conversion circuit (16) in the integrating circuit (10). A temporally integrated value of the power supply voltage is measured during a measurement period. Preferably, integrating measurements of a plurality of internal supply voltages are performed in parallel during the same measurement time interval. Preferably a further test is performed by changing over between mutually different supply voltages during a further measurement period. In this way the measured integrated supply voltage can be used to check the speed of the change over between the different voltages.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: October 8, 2013
    Assignee: NXP B.V.
    Inventors: Rinze I. M. P. Meijer, Sandeep Kumar Goel, Jose De Jesus Pineda De Gyvez
  • Patent number: 8547105
    Abstract: A system for detecting a location of fault in a cable includes a cable transmitting a fault current a current transforming unit connected to the cable and receiving the fault current and detecting an original signal of fault current, a detecting unit detecting a first detail signal and a second detail signal from the original signal of fault current where both signals being detail components in a high frequency band, a comparing unit comparing the first detail signal with a preset reference value and determining a fault in the cable, and a signal filtering unit generating a first filtering signal and a second filtering signal by use of the first detail signal and the second detail signal and outputting a fault detection signal based on a result of comparing the both signals.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: October 1, 2013
    Assignee: Korea Electric Power Corporation
    Inventors: Chae-Kyun Jung, Ji-Won Kang
  • Patent number: 8531804
    Abstract: The present invention is implemented by deploying an enhanced ground fault detection and location apparatus and by using the apparatus in conjunction with specific circuit analysis methods, using the information generated by the ground fault detection and location apparatus. The ground fault detection and location apparatus comprises the functionality of a voltmeter, an ammeter, a phase angle meter, a frequency generator, and a variable power supply, thereby providing for a variety of signals and analyses to be performed on a unintentionally grounded circuit in an ungrounded AC or DC power distribution system. The ground fault detection and location apparatus is capable of operating in six different modes, with each mode providing a different capability or opportunity for detecting, analyzing, and locating one or more unintentionally grounded circuits in an normally ungrounded AC or DC power distribution system.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: September 10, 2013
    Inventors: Warren A. Weems, II, Russsell L. Kincaid, Wayne L. Green
  • Patent number: 8525542
    Abstract: A short circuit detection device is provided to check a circuit layout. The circuit layout includes electronic components connected in parallel. Any of the electronic components includes two contacts on the circuit layout. The short circuit detection device includes a determination circuit configured to determine whether a short circuit has occurred in the circuit layout, and a detection circuit configured to determine the specific electronic component or components responsible for the short circuit. The determination circuit connects with one contact of any of the electronic components. The detection circuit connects with two contacts of any of the electronic components.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: September 3, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Jin-Liang Xiong
  • Publication number: 20130214792
    Abstract: Embodiments of methods and apparatuses for characterizing an electrical power distribution system are disclosed. One method includes applying, by at least one test/response unit, at least one test signal to at least one test point of the system, measuring, by a plurality of test/response units, a plurality of response signals at a plurality of test points, wherein the plurality of response signals are generated in response to the at least one test signal, and characterizing the system based on the plurality of response signals.
    Type: Application
    Filed: March 17, 2013
    Publication date: August 22, 2013
    Inventors: Bertrand M. Hochwald, Thomas L. Marzetta
  • Patent number: 8515416
    Abstract: In a radio device such as a receiver or transceiver, a test operation can be performed to determine performance. A received signal can be processed to obtain demodulated samples, which can be provided to a logic to perform a logic operation on the samples to generate a logic output. A storage such as a counter or other mechanism is coupled to the logic to store a count of a number of the logic outputs having an error.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: August 20, 2013
    Assignee: Silicon Laboratories Inc
    Inventor: Hendricus De Ruijter
  • Patent number: RE45050
    Abstract: Systems and methods for determining the configuration of a connection between two devices by measuring an electrical characteristic are provided. Using the measured electrical characteristic, a device is able to select an appropriate communication interface, such as serial, Universal Serial Bus (USB), FireWire, parallel, PS/2, etc., and configure itself appropriately. Systems and methods which determine the physical orientation of a connector with respect to another connector may also be provided alone or in combination with such systems and methods for selecting communication interfaces. The physical orientation of a connector can be determined by measuring an electrical characteristic and a device can then configure itself appropriately. In accordance with the principles of the present invention, device designs can decrease in size and cost as well as simplify operation for the end-user.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: July 29, 2014
    Assignee: Apple Inc.
    Inventors: Jeffrey J. Terlizzi, Stanley Rabu, Nicholas R. Kalayjian
  • Patent number: RE45492
    Abstract: Systems and methods for determining the configuration of a connection between two devices by measuring an electrical characteristic are provided. Using the measured electrical characteristic, a device is able to select an appropriate communication interface, such as serial, Universal Serial Bus (USB), FireWire, parallel, PS/2, etc., and configure itself appropriately. Systems and methods which determine the physical orientation of a connector with respect to another connector may also be provided alone or in combination with such systems and methods for selecting communication interfaces. The physical orientation of a connector can be determined by measuring an electrical characteristic and a device can then configure itself appropriately. In accordance with the principles of the present invention, device designs can decrease in size and cost as well as simplify operation for the end-user.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: April 28, 2015
    Assignee: Apple Inc.
    Inventors: Jeffrey J. Terlizzi, Stanley Rabu, Nicholas R. Kalayjian