Abstract: A test circuit for evaluating the characteristics of an component formed on the surface of a semi-conductor substrate. The test circuit comprises at least two MOS field effect transistors having the same gate width and different gate lengths, and measuring electrodes mounted on opposite ends of each gate and enageable with probes when measuring the test circuit. The test circuit measures typical characteristic data of MOSFETs to be used in a semiconductor device with good match by an electrical means.

Abstract: A method for determining an electrical characteristic (such as a resistance) of an antifuse of a programmable device.

Abstract: A testing method and apparatus for conductive materials using electric current which makes it possible to rapidly evaluate the electromigration resistance of conductive materials. The apparatus includes a substrate support for supporting a substrate on which an interconnector pattern is formed, a cooling vessel for cooling the substrate, a first current supply for applying a first current to the interconnector, a resistance measurer for measuring the resistance of the interconnector pattern while the first electric current is being applied to the interconnector pattern, a second current supply for applying a second electric current larger than the first electric current to the interconnector pattern, and a controller which controls the repetition of the measurement of resistance of the interconnector pattern and the application of the second current to the interconnector pattern.

Abstract: The resistivity of the surface of a semiconductor wafer is measured at different temperatures to determine the resistivity as a function of temperature. The temperature of the semiconductor wafer is varied by a heater in thermal contact with the semiconductor wafer, and the temperature is measured by a temperature sensor in thermal contact with the semiconductor. The heater is controlled by a control unit which adjusts the amount of heat provided by the heater, thereby controlling the temperature at which a measurement from a four-point resistivity probe is taken.

Abstract: A wafer substrate test structure and method provides a novel means for quantitatively determining electrical isolation between active devices and passive elements in a monolithic integrated circuit. The structure and method of this invention are useful for both optimal design and manufacture of integrated circuit devices.

Abstract: Apparatus and method for determining and imaging superconductor surface resistance. The apparatus comprises modified Gaussian confocal resonator structure with the sample remote from the radiating mirror. Surface resistance is determined by analyzing and imaging reflected microwaves; imaging reveals anomalies due to surface impurities, non-stoichiometry, and the like, in the surface of the superconductor.

Abstract: A contact test structure and method provide accelerated testing of long term reliability of metal to silicon ohmic contacts and adjacent PN junctions on IC dies of a wafer. At least one wafer level reliability contact test structure (10) is formed on the wafer during CMOS or BICMOS wafer fabrication mask sequences without additional steps. A shallow layer (N+S/D) of semiconductor silicon material of second type carrier (N) conductivity is formed in a well (PWELL) of first type carrier (P) conductivity silicon material with a shallow PN junction (J) between the shallow layer and well. Metal to silicon first and second test contacts (TC1,TC2) of metal layer portions (M1) are formed at first and second locations on the shallow layer (N+S/D) spaced apart a selected distance. The second test contact (TC2) has a contact area between a metal layer (M1) and shallow layer (N+S/D) in the minimum size range for the fabrication process for maximizing current density through the second test contact (TC2).

Abstract: The invention relates to apparatus and method for determining the carrier concentration profile of the carrier concentration in semiconductor materials, multi-layer semiconductor structures and semiconductor devices. According to the invention, applied between an ohmic contact and a rectifying contact formed on the semiconductor are a d.c. voltage resulting in a reverse bias, and two periodic excitation signals having frequencies .OMEGA..sub.1 and .OMEGA..sub.2. Frequency .OMEGA..sub.1 is greater than .OMEGA..sub.2 such that .OMEGA..sub.1, .OMEGA..sub.2, their difference (.OMEGA..sub.2 -.OMEGA..sub.2) and their sum (.OMEGA..sub.1 +.OMEGA..sub.2) are in the same order of magnitude. Two components from the semiconductor's electronic response to the excitation are selected for analysis. The first component is the response to the frequency .OMEGA..sub.1 or .OMEGA..sub.2, and the second component is a first order intermodulation product of one of .OMEGA..sub.1 and .OMEGA..sub.2.

Abstract: A probe which is positioned in at least one axis by a piezoelectric transducer is provided. One or more piezoelectric transducers control position of the probe with respect to another probe, with respect to a sample surface, or with respect to a previous position of the probe itself. A method for measuring spreading resistance is provided where the distance between two probes is reproducibly controlled in the range of a few angstroms by measuring tunneling current between the two probes, and electrical contact between the two probes and a sample is reproducibly provided by monitoring current between the probes and the sample.

Abstract: A method and apparatus for characterizing the quality of an electrically thin semiconductor film and its interfaces with adjacent materials by employing a capacitor and a topside electrical contact on the same side of the electrically thin semiconductor film to thereby permit the taking of capacitance-voltage (C-V) measurements. A computer controlled C-V measuring system is operatively coupled to the contact and capacitor to modulate the potential on the capacitor. Variation of the voltage applied to the capacitor enables modulation of the potential applied to the film to thereby vary the conductivity of the film between the capacitor gate node and the topside contact.

Abstract: A non-destructive measurement system for producing whole wafer maps of sheet Hall concentration and Hall mobility in a GaAs wafer. The wafer need only have van der Pauw patterns available for the wafer measurements to be made. The measurement system includes an automatic test prober apparatus modified to incorporate a powerful permanent magnet providing a magnetic field to produce a Hall effect in the GaAs wafer. A parametric measurement system coupled through test probes to the van der Pauw patterns is programmed to measure sheet resistivity, Hall voltage and magnetic field strength, from which are derived values of sheet Hall concentration and mobility that are stored and mapped.

Abstract: A non-invasive sensor system (50) for real-time in situ measurements of sheet resistance and thickness of conductive layers of a semiconductor wafer. The sensor (50) includes a microwave source (78) for generating a plurality of microwave signals. An emitter waveguide (52) receives the plurality of microwave signals from the microwave source (78) and emits the microwave signals in the direction of the semiconductor wafer (20) in fabrication chamber (18). The collector waveguide (84) detects the reflected microwave signals from the semiconductor wafer (20). A dual directional coupler (64) communicates with emitter waveguide (52) to direct the microwave signals to and from the emitter waveguide (52) and to generate a plurality of electrical signals that relate to semiconductor wafer (20), conductive layer (108), and deposition vapor physical characteristics. These physical characteristics include conductive layer thickness, resistivity, and substrate temperature.

Abstract: Disclosed is a measurement method and apparatus by which measurement of the breakdown voltage of a semiconductor device under test (DUT) may be conducted with an inexpensive measuring system in which thermal stress applied to the DUT is small and thus measurement error caused by characteristic change of the DUT is less. A constant current smaller than the breakdown current of the DUT is applied to a DUT using a constant current source, and waveforms between terminals of said DUT are observed by a waveform observation device, thereby measuring the trigger voltage and the latchback voltage. When a constant current I is applied to the DUT from the constant current source, a stray capacitance C between terminals of said DUT is charged. Thus, the voltage between terminals of said DUT is increased with a constant inclination (I/C) as time goes by.

Abstract: Disclosed is a method for manufacturing an integrated circuit which includes the step of evaluating the reliability of metal films in the circuit using a noise measurement technique. In one embodiment, a film portion to be tested is incorporated in a Wheatstone bridge. A relatively large direct current is passed through the film to stimulate 1/f.sup.2 noise. A relatively small alternating current is concurrently passed through the film. The bridge imbalance signal at the ac frequency is amplified and demodulated by a phase-locked amplifier, and is then frequency analyzed. The film is evaluated by comparing the resulting noise power spectrum with predetermined standards.

Abstract: Thermal balance in an array of RF transistor cells in which all transistors are connected in parallel is obtained by interconnecting the transistors to array contacts by means of discrete wire leads. The array is electrically tested and a temperature distribution in the array is obtained. Thereafter, the wire leads are varied in length and height above the plane of the array to improve temperature distribution during test. The steps are repeated as necessary to obtain a desired temperature balance in the array.

Abstract: An apparatus and method for measurement of electrical properties of a dielectric layer on a semiconductor wafer body is disclosed. The apparatus supports the semiconductor wafer body in position and two electrical contacts are utilized, one of which is a probe tip having a uniformly flat contact portion. Means are provided for establishing a planar contact between the flat contact portion of the probe tip and the dielectric layer of the semiconductor wafer. Measurements of the electrical properties of the dielectric layer can then be made without the use of patterned mesas.

Abstract: An apparatus for measuring the resistance of a test specimen includes an insulated-gate-bipolar-transistor (IGBT transistor) which is provided for applying a test current to the test specimen. A voltage measuring unit is provided including a serial connection of a voltage measuring device and an MOS transistor. A current measuring device is provided for measuring the test flowing through the test specimen. The voltage measured by the voltage measuring unit is used to compensate for the voltage drop across the IGBT transistor when calculating the resistance of the test specimen.

Abstract: A method and apparatus for measuring resistivity employ the four-point probe method to measure the surface resistivity or volume resistivity of a sample. The method includes inputting sample shape information and calculating a resistance correction coefficient for the sample based on the shape information and information relating to a measurement position on the sample. The sample surface resistivity or volume resistivity is calculated by multiplying a resistance value, which is measured in accordance with the four-point probe method, by the correction coefficient.

Abstract: A method for measuring the width of structures in a semiconductor wafer comprises the step of constructing test structures on the wafer shaped to function as moats for confining electrically conductive liquid. The moats have an elongated shape. By measuring the electrical resistance exhibited by the liquid within the moat, the dimensions of the moat and, thus, the other structures on the wafer can be measured.