Abstract: It is an object of the present invention to provide a semiconductor-producing/examining device which can maintain a preferable connection state for a predetermined period of time and which can easily remove a ceramic substrate from a supporting case. The present invention is a semiconductor producing/examining device comprising: a ceramic substrate having a conductor layer formed on the surface thereof or inside thereof; and a supporting case; in which an external terminal is connected to the conductor layer, wherein a connection between the conductor layer and the external terminal is performed such that the external terminal is pressed on the conductor layer or the external terminal is pressed on another conductor layer connected to the conductor layer by using the elastic force and the like of an elastic body.

Abstract: Apparatus and method for measuring surface resistivity of a wafer (12). A source of high frequency radiation (6, 41) emits an incident wave burst that impinges the wafer at a desired spot location. A reflected wave burst is detected at an appropriate time window by a receiver (8, 42). The relationship between incident and reflected energies is a function of the surface resistivity of the wafer.

Abstract: A method for depositing a first metal layer such as tantalum or copper on a patterned semiconductor wafer using a metal sputtering tool that typically includes an electrically biased wafer chuck is disclosed. Initially, a first test wafer is placed on the wafer chuck and a first test layer of materials is deposited on the first test wafer. During the deposition of the first test layer on the first test wafer, the wafer receives the electrical bias at a first level. A second test wafer is then placed on the wafer chuck and a second test layer of material is deposited with the second wafer receiving a second level of electrical bias. The difference in thickness between the first layer and the second layer is then determined. If the difference in thickness is within a predetermined range, the metal sputtering chamber is qualified to deposit a production layer on a production semiconductor wafer.

Abstract: A particular portion of a damaged layer within a semiconductor substrate, which is likely to affect the performance of resulting semiconductor devices, is distinguished from the other negligible portions thereof and the depth of that non-negligible portion is detected. An Si substrate is placed on a stage, and a mercury electrode, which forms a Schottky barrier with the Si substrate, is brought into contact with the surface of the Si substrate. When a constant current is supplied from a constant current source between the mercury electrode and the Si substrate, charges are trapped at the trap centers in the damaged layer within the Si substrate. As a result, a potential on the conduction band rises near the surface of the Si substrate. And if the voltage between the electrode and the substrate is increased along with the potential rise, a constant current flows.

Abstract: A method for measuring electromigration includes the steps of measuring a corresponding voltage increase across an interconnect as a function of time for a plurality of nonzero heating rates and calculating an interconnect integrity from the voltage increase.

Abstract: A method of making a microelectronic package includes providing a first microelectronic element having electrically conductive parts and including first and second surfaces and providing a compliant element including a releasable adhesive over the first surface of the first microelectronic element. A second microelectronic element having electrically conductive parts is abutted against the releasable adhesive so that the second microelectronic element is releasably assembled to the first microelectronic element and the electrically conductive parts of the first and second microelectronic elements are connected to one another. The releasably assembled package is tested to determine whether the package has been properly assembled. A curable liquid is then introduced between the first and second microelectronic elements of a properly assembled package and the curable liquid is cured to permanently assemble the first and second microelectronic elements together.

Abstract: In order to measure a width of a wire a measuring pattern for the width of the wire is prepared. The measuring pattern includes: a first pattern with a first width; a second pattern connected to the first pattern and having a second width wider than the first width; and a third pattern connected to the second pattern and having a third width narrower than the first width. The first pattern, the second pattern and the third pattern are made of same material. The first pattern through a power source is connected to the third pattern. A first pair of probes are disposed on the first pattern and then are connected to a first voltmeter. A distance between the first pair of probes is a first distance wider than the first width. A second pair of probes are disposed on the second pattern and then are connected to a second voltmeter. A distance between the second pair of probes is a second distance wider than the first width.

Abstract: A method of measuring a width of an undoped or lightly doped polysilicon line is disclosed. The width measuring method includes generating carriers in the polysilicon line with an energy source; measuring a capacitance between the polysilicon line and a substrate separated from the polysilicon line by a dielectric layer; and determining a line width of said polysilicon line from the measured capacitance. The capacitance measurement includes connecting first and second probes to the polysilicon line; connecting a third probe to the substrate; connecting a first terminal of a capacitance meter to the first and second probes; connecting a second terminal of the capacitance meter to the third probe; and applying a direct current bias across the first and second probes. A capacitor may be connected between the first and second probes. Further steps include, connecting a fourth probe to a conductor that supports the substrate; and connecting the fourth probe to the third probe.

Abstract: In the method for testing a memory cell, a test voltage is applied to a memory cell and the test voltage is changed, preferably in incremental or decremental steps, during the testing. From the shape of the hysteresis of the memory cell it is determined whether or not the memory cell is a weak or substandard memory cell.

Abstract: The inventive apparatus is capable of accurate contactless sample conductance measurements. In accordance with the invention, a three coil apparatus for inductive conductance measurements comprises at least three coils, (or inductive devices,) a radio frequency (RF) generating device in conjunction with electronic circuitry for radio frequency amplitude measurement and comparison of radio frequency amplitude signals. The attainable accuracy is improved over that achieved using other conventional non-contact means by processing the differences of RF amplitude signals observed across pairs of sensing coils. Also, this invention does not require more complex RF signal processing, such as analysis of in-phase and quadrature voltage data. In a preferred embodiment, the natural resonance frequencies of the two sensing coils are tuned slightly off the RF driving frequency such that a monotonic response across a wide range of the sample's conductivity is achieved.

Abstract: A method and apparatus are disclosed for electrically monitoring processing variations of a material deposited using a collimated process. In one embodiment, the method and apparatus are directed to monitoring variations in step coverage of a conductive material deposited using a collimated sputtering process. A substrate having a plurality of trenches is used to mimic features desired to be monitored, such as contact holes. The resistance of metal deposited into the trenches is monitored to determine the effectiveness of the collimated sputtering process.

Abstract: A method and apparatus are disclosed for electrically monitoring processing variations of a material deposited using a collimated process. In one embodiment, the method and apparatus are directed to monitoring variations in step coverage of a conductive material deposited using a collimated sputtering process. A substrate having a plurality of trenches is used to mimic features desired to be monitored, such as contact holes. The resistance of metal deposited into the trenches is monitored to determine the effectiveness of the collimated sputtering process.

Abstract: A cathode-anode apparatus is constructed whereby the wafer under test, connected to a conducting wire, forms the cathode terminal and a copper plate, also connected to a conducting wire, forms the anode terminal. The wafer under test and the copper plate are immersed in a CuSO4—H2O solution. A positive dc voltage is applied to the copper plate; the dc current ionizes the CuSO4 solution and forms Cu2+ ions. These Cu2+ ions will diffuse to the wafer surface. Most of the Cu2+ ions will accumulate in and around defective contacts or vias in the semiconductor surface making these defective contacts or vias readily identifiable.

Abstract: A monitor for electrically testing energy beam dose or focus of a layer formed on a substrate by lithographic processing. The monitor comprises a substrate having in a lithographically formed layer an array of electrically conductive elements comprising a plurality of spaced, substantially parallel elements having a length and a width, with the individual elements being electrically connected, and the lengths of the elements being sensitive to dose and focus of an energy beam in lithographically forming the layer. The monitor further includes at least one pad electrically connected to the array to apply current through the array elements. Upon applying a voltage across the array elements, the suitability of dose or focus of the lithographically formed layer may be determined by the resistance of the array. Preferably, ends of the individual elements are aligned along essentially straight lines to form an array edge.

Abstract: The present invention provides a C-V method for measuring an effective channel length in a device, which can simultaneously measure a gate-to-drain overlap length and a gate etch bias length in the device. In the present method, the measured length of the gate by using the present method has a deviation below 5% to compare with the real gate length form SEM. Furthermore, the calculating method of the present invention is only using simple simultaneous equations, which can be measured by a man or a mechanism. As the layout rule shrunk, the present method provides a simple way to measure those parameters, which become more and more important in the device.

Abstract: A semiconductor testing process effectively determines the integrity of a large capacitive structure buried within an integrated circuit. According to one example embodiment, a process of testing the oxide integrity of a circuit involves selecting a large gate oxide structure or structures that can be isolated from leakage paths. The dielectric integrity of the structure is tested by stressing the structure via voltage settings, comparable to a supply voltage, across its two terminals. The structure is connected to a current-sensitive node in-the integrated circuit across the two terminals. Other circuits connected to the current-sensitive node are shut off so that the current-sensitive node should be an island relative to other current paths. The leakage current at the current-sensitive node is then measured and compared with a reference level. From the measurements and comparison, a quality factor indicative of the dielectric integrity in the structure is determined.

Abstract: A transistor having a longer channel length and serving as a reference, and a transistor having a shorter channel length and to be subjected to effective channel length extraction are prepared (step ST1.1). A hypothetical point at which a change in a total drain-to-source resistance is estimated to be approximately zero when a gate overdrive is slightly changed is extracted in a mask channel length versus total drain-to-source resistance plane. The values of a function (F) are calculated which are defined by the difference between the rate of change in the total drain-to-source resistance and the product of a channel resistance per unit length and the rate of change in a mask channel length at the hypothetical points (step ST1.6). A true threshold voltage of the transistor having the shorter channel length is determined by a shift amount (&dgr;) which minimizes the standard deviation of the function (F) determined in the step ST1.7 (step ST1.10).

Abstract: A method measures a resistance in a test structure to determine the sheet resistivity of a test structure. In one embodiment, a family of test structures is provided to determine the effective sheet resistivity of a conductor as a function of its width. The method is applicable to conductors in manufacturing processes in which “slots” or “islands” are created in the conductor to prevent dishing during chemical-mechanical polishing.

Abstract: A device stack for fabrication of an isolation structure and methods of fabricating the same are provided. In one aspect, a method of processing a substrate is provided that includes exposing the substrate to a plasma ambient containing nitrogen and oxygen to form a nitrogen containing interface. An oxide film is formed on the nitrogen containing interface and a silicon rich nitride film is formed on the oxide film. The silicon rich nitride film is exposed to a plasma ambient containing oxygen to convert an upper portion of the silicon rich nitride film to silicon oxynitride. The optical properties of the nitride film are enhanced so that UV lithographic patterning of etch masking is improved.

Abstract: The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (&dgr;) which minimizes the standard deviation of the function F to be obtained (step ST1.

Abstract: A test structure which includes a first conductive feature layer and a second conductive feature layer is described. The first conductive feature layer includes a first conductive line. The second conductive feature layer includes a second conductive line. A daisy chain conductive feature is also included in the test structure. The daisy chain conductive feature includes portions on the first and second conductive feature layers which are interconnected to each other by vias.

Abstract: A monitoring resistor element includes a plurality of resistors (1, 2) formed on an integrated circuit chip through the same fabrication steps as those used to form a practical circuit are connected to power source pads (3, 4, 5, 6), which are terminal pads formed on the integrated circuit chip. A method for measuring a relative preciseness of resistors (1, 2) formed on an integrated circuit chip includes the step of performing the relative preciseness of the resistors by using power source pads (3, 4, 5, 6), to which the resistors (1, 2) are connected and which are terminal pads formed on the integrated circuit chip, as measuring pads when the measurement of relative preciseness of the resistors (1, 2) is performed.

Abstract: A test coupon for measuring the effects of solder processes on circuit testability. The test coupon includes a circuit board having a multiplicity of circuit conductor patterns. Each conductor pattern is connected to a plurality of pads and vias on the circuit board. The circuit pads on an opposite surface of the circuit board support solder connections to a plurality of different circuit components. The circuit pads are connected to the vias, which in turn are connected to individual conductors of the circuit pattern. A surface connector is also supported on the circuit board, having pins extending through the circuit board. The circuit pattern conductors terminate on a respective connector pin. The test coupon may be subject to in-circuit testing where a value of the various components are measured. The multiple circuit patterns and mounted components permit different types of tester pins to be used to evaluate in-circuit testability in a test coupon used in a particular manufacturing process.

Abstract: To determine electrical resistance of an ohmic contact between a flexible printed circuit and a metallized layer upon a substrate of piezoelectric material, the printed circuit is provided with two exposed metal pads, in close proximity to each other, and two electrical leads from each pad to locations on the printed circuit that are accessible for probing with a four-lead resistance meter. For measurement of contact resistance in process development and process capability studies, many sets of such pads, of a variety of sizes, may be combined into a single printed circuit. For in-process monitoring of transducer manufacturing, a small number of contact resistance measurement pads may be designed into production printed circuits.

Abstract: Measurement of pulse CV characteristics and an SIMS measurement of a semiconductor substrate are made at the same position. An SIMS profile is calibrated by a method of least squares so that a dose amount determined from the SIMS profile coincide with a dose amount determined from the concentration profile of a carrier which is calculated from the pulse CV characteristics in a range where accuracy of the carrier concentration is secured. In the case where plural impurities are introduced, a measurement of pulse CV and SIMS measurement are made and the distribution of impurity concentration and the distribution of carrier concentration are estimated by simulation every time when an impurity is introduced. When an impurity is introduced in a high concentration, an impurity of the inverse conductive-type to that of the former impurity is introduced.

Abstract: Precise sensing and controlling of temperature during in-situ testing of a structure used in an integrated circuit by fabricating or placing a heat source element adjacent to the structure and by fabricating or placing a temperature sensing element adjacent to the structure.

Abstract: A process, voltage, and temperature calibration system that shares a single calibration resistor among multiple calibration circuits. The use of single calibration resistor among several calibration circuits is accomplished through time division multiplexing. N-channel and P-channel field effect transistor calibration also share the same resistor. Turning on transistors in calibration circuits of the type not being calibrated creates a low impedance path from one terminal of the calibration resistor to a power supply. This biases the calibration resistor for the calibration circuit.

Abstract: A test coupon for measuring the effects of solder processes on circuit testability. The test coupon includes a circuit board having a multiplicity of circuit conductor patterns. Each conductor pattern is connected to a plurality of pads and vias on the circuit board. The circuit pads on an opposite surface of the circuit board support solder connections to a plurality of different circuit components. The circuit pads are connected to the vias, which in turn are connected to individual conductors of the circuit pattern. A surface connector is also supported on the circuit board, having pins extending through the circuit board. The circuit pattern conductors terminate on a respective connector pin. The test coupon may be subject to in-circuit testing where a value of the various components are measured. The multiple circuit patterns and mounted components permit different types of tester pins to be used to evaluate in-circuit testability in a test coupon used in a particular manufacturing process.

Abstract: A method, apparatus and computer program product for identifying electrostatic discharge (ESD) damage to a thin film device. The method includes (1) determining a cold resistance of the thin film device, (2) determining a hot resistance of the thin film device, (3) calculating a heating delta resistance (HDR) from the hot and cold resistances and (4) comparing the HDR to a threshold value to ascertain if the thin film device has suffered ESD damage. The HDR of the thin film device is characterized by the following relationship: HDR=(hot resistance-cold resistance)/(cold resistance).

Abstract: A method of testing a leakage current caused by a self-aligned silicide process is described. The invention uses different test structure to monitor degree of and reason for a leakage current caused by a self-aligned silicide process. While monitoring a self-aligned silicide process performed on a metal-oxide semiconductor transistor without a LDD region, in addition to considering a leakage current occurring from the metal silicide layer to the junction and occurring at edge of the metal silicide layer, the invention further considers a leakage current at comer of the metal silicide layer. For a metal-oxide semiconductor transistor having a LDD region, the invention further considers a leakage current from the metal silicide layer to the LDD region. The invention monitors a leakage current at comer of the metal silicide layer.

Abstract: The present invention comprises a SCM measuring apparatus and a control section. A control section adjusts shape data of a probe tip initially inputted based on SCM measurement for a standard specimen and a simulated result by the measuring apparatus, and then performs the SCM measurement by a standard specimen, and then on the basis of the measuring result, a impurity distribution is assumed. Next, the impurity distribution is adjusted so that the CV property calculated by the SCM simulation coincides with the CV property measured by the SCM measuring apparatus, and then the CV property is calculated again. The impurity distribution in case both of the CV properties coincide with each other is determined as a definitive impurity distribution. The definitive impurity distribution is outputted to a display apparatus, a printer, and so on. Therefore, it is possible to analyze the impurity distribution with accuracy smaller than a width of the probe tip.

Abstract: Measuring an electrical potential in a semiconductor element by applying one or more voltages over the semiconductor element, placing at least one conductor in contact with the semi-conductor element using a scanning proximity microscope while injecting a substantially zero current in the semiconductor element with the conductor, measuring an electrical potential in the conductor while injecting a substantially zero current in the semiconductor element with the conductor, changing the position of the conductor, and repeating the measuring and changing steps.

Abstract: A system for detecting defects in an interlayer dielectric (ILD) interposed between first and second conductive lines lying adjacent each other along a first plane is provided. A processor controls general operations of the system. A voltage source adapted to apply a bias voltage between the first and second conductive lines is employed to induce a leakage current across the ILD. A light source for illuminating at least a portion of the ILD is used to enhance the leakage current. A magnetic field source applies a magnetic field in a direction orthogonal to the leakage current. The magnetic field deflects carriers in a direction substantially perpendicular to the first plane. A voltage monitor measures a voltage generated across third and fourth conductive lines, the third and fourth conductive lines lying adjacent each other along a second plane which is substantially perpendicular to the first plane. The voltage monitor is operatively coupled to the processor.

Abstract: The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (&dgr;) which minimizes the standard deviation of the function F to be obtained (step ST1.

Abstract: A method and apparatus for measuring sheet resistance and thickness of thin films and substrates. A four-point probe assembly engages the surface of a film on a substrate, and the thickness of the substrate is determined from the point of contact between the probes and film. A measuring apparatus then outputs a voltage waveform which applies a voltage to probes of the probe assembly. An inverter inverts the voltage and provides the inverted voltage on another probe of the probe assembly, thus inducing a current in these probes of the four point probe and through the surface of the film. Two other probes measure a voltage in the film created by the current. The voltages on the current probes provide a voltage close to zero at the other probes, thus allowing these other probes to measure voltages with greater precision. The current created by the voltage waveform and the voltage created across the inner probes are measured for each voltage level of the waveform.

Abstract: Measurement of pulse CV characteristics and an SIMS measurement of a semiconductor substrate are made at the same position. An SIMS profile is calibrated by a method of least squares so that a dose amount determined from the SIMS profile coincide with a dose amount determined from the concentration profile of a carrier which is calculated from the pulse CV characteristics in a range where accuracy of the carrier concentration is secured. In the case where plural impurities are introduced, a measurement of pulse CV and SIMS measurement are made and the distribution of impurity concentration and the distribution of carrier concentration are estimated by simulation every time when an impurity is introduced. When an impurity is introduced in a high concentration, an impurity of the inverse conductive-type to that of the former impurity is introduced.

Abstract: The present invention is a method for determining a carrier conductivity-rier mobility spectrum for a semiconductor sample, having the steps of: exposing the semiconductor sample to a range K of discrete magnetic fields k=1,2, . . . K; for each field obtaining a Hall coefficient R.sub.H and a resistivity .rho., and calculating from R.sub.H (B.sub.k) and .sigma.(B.sub.k) experimental conductivity tensor components .sigma..sub.xx.sup.k (exp) and .sigma..sub.xy.sup.k (exp), and slopes of these conductivity tensor components .sigma.'.sub.xx.sup.k (exp) and .sigma.'.sub.xy.sup.k (exp); selecting a trial carrier conductivity-carrier mobility spectrum s.sub.i corresponding to a plurality I of carrier mobilities .mu..sub.i, i=1,2, . . . I; for each B.sub.j, using this trial carrier conductivity-carrier mobility spectrum to calculate conductivity tensor components .sigma..sub.xx.sup.j and .sigma..sub.xy.sup.j, and slopes of the conductivity tensor components .sigma.'.sub.xx.sup.j and .sigma.'.sub.xy.sup.

Abstract: A method and apparatus are provided for determining the doping concentration profile of a specimen of semiconductor material. The specimen is positioned between a pair of electrodes, the specimen being disposed on one of the electrodes and being spaced form the other electrode by a nonconductive medium. In one implementation of the invention the nonconductive medium is air. A region of the surface of the specimen is illuminated with a beam of light of wavelengths shorter than that corresponding to the energy gap of the semiconductor material and which is intensity modulated at a predetermined frequency. A variable DC bias voltage is applied between the pair of electrodes, the variable DC bias voltage varying between that corresponding to accumulation and that corresponding to deep depletion for the specimen. The intensity of the light beam is low enough and the speed at which the DC bias voltage is varied is fast enough such that no inversion layer is formed at the surface of the specimen.

Abstract: A shield region of metallization is formed in a first metallization layer of an integrated circuit so as to increase the metal density of the first metallization layer to at least a minimum density required for proper fabrication. The shield region is coupled via an amplifier or other suitable coupling mechanism to at least a portion of another metallization layer overlying or underlying the first metallization layer in the integrated circuit, such that the shield region acts to reduce parasitic capacitance associated with a circuit node in the other metallization layer. In an illustrative fingerprint sensor cell implementation, the shield region is in the form of a shield plate underlying a sensor plate in the sensor cell and serves to increase the metal density of a lower-level metallization layer in the cell.

Abstract: Measuring an electrical potential in a semiconductor element by applying one or more voltages over the semiconductor element, placing at least one conductor in contact with the semi-conductor element using a scanning proximity microscope while injecting a substantially zero current in the semiconductor element with the conductor, measuring an electrical potential in the conductor while injecting a substantially zero current in the semiconductor element with the conductor, changing the position of the conductor, and repeating the measuring and changing steps.

Abstract: A thin-film depositing apparatus of the present invention deposits a sputtered film on a substrate in a sputtering chamber, and removes the substrate having the sputtered film deposited thereon from the sputtering chamber via a load-lock chamber by a robot arm. As a system for controlling the sheet resistance of the sputtered film deposited on the substrate, a measuring device using an eddy current method is mounted in the proximity of a substrate outlet of the load-lock chamber and measures the sheet resistance of the sputtered film of the substrate removed from the substrate outlet. With this structure, it is possible to provide a thin-film depositing apparatus which stably measures the sheet resistance of a thin film deposited on a substrate and performs feedback of the measurement result to control the film deposition conditions so that a thin film to be deposited on a subsequent substrate has a desired thickness.

Abstract: An apparatus measures a property of a layer (such as the sheet resistance of a conductive layer or thermal conductivity of a dielectric layer that is located underneath the conductive layer) by performing the following method: (1) focusing the heating beam on the heated a region (also called "heated region") of the conductive layer (2) modulating the power of the heating beam at a predetermined frequency that is selected to be sufficiently low to ensure that at least a majority (preferably all) of the generated heat transfers out of the heated region by diffusion, and (3) measuring the power of another beam that is (a) reflected by the heated region, and (b) modulated in phase with modulation of the heating beam. The measurement in act (3) can be used directly as a measure of the resistance (per unit length) of a conductive line formed by patterning the conductive layer.

Abstract: A method for estimating the longevity of a gate dielectric film of a semiconductor device. A plurality of test bias voltages are applied to a plurality of test semiconductor devices. The test gate currents drawn in the respective dielectric films of the test semiconductor devices in response to the test bias voltages are measured. A relationship is determined between the test gate currents and the longevity of the test semiconductor devices. A production semiconductor device is biased with a predetermined bias voltage. The gate current drawn through the gate dielectric film of the semiconductor device in response to the predetermined bias voltage is measured. The longevity of the gate dielectric film of the production semiconductor device is estimated based on the measured gate current, using the determined relationship.

Abstract: An ultra-thin dielectric film is subject to a dynamic electrical bias. During a first phase, the ultra-thin dielectric film is under a high field bias generated by the application of a high voltage. The duration of the high electrical stress is dependent on the intrinsic properties of the ultra-thin dielectric material. In a second phase, the ultra-thin dielectric film is subjected to an operating field bias generated by the application of an operating voltage. The change in the field bias exposes the dielectric to a similar dynamic stress that microelectronic devices ordinarily experience. At the operating field stage, a gate current is measured and compared to a predetermined range. Once the gate current exceeds that range the test concludes. Otherwise, the test cycles between the above-mentioned phases for a predetermined number of iterations based on prior experimental correlation.

Abstract: A method for monitoring the temperature of a product wafer during thermal processing of the product wafer in an emissivity independent thermal processing system includes processing a test wafer in the emissivity independent thermal processing system that thermally processes the product wafer. The test wafer is pretreated before being thus placed in the thermal processing system. The test wafer is thermally processed following a substantially same thermal processing recipe as that used for thermal processing of the product wafers. After the thermal processing of the test wafer, a sheet resistance of the test wafer is measured. This sheet resistance is correlated to a wafer temperature at the test wafer that was achieved during the thermal processing of the test wafer.

Abstract: A method for testing thin gate oxide integrity of a semiconductor device includes the steps of performing a current or voltage ramp test on the thin gate oxide semiconductor device. The resultant current and voltage data points indicating an increasing magnitude of current flowing through the thin gate oxide and corresponding increasing magnitude of voltage across the thin gate oxide are measured and recorded (14, 16). A slope is then computed between each successive pair of data points and stored (20). Each successive pair of computed slopes are then compared against a predetermined setpoint (22), where a possible kink point is detected if a pair of successive computed slopes has a difference greater than the predetermined setpoint (24).

Abstract: A method for calibrating the temperature of an epitaxy reactor includes the steps of preparing a reference wafer having undergone on at least one of its surfaces an implant of a doping followed by an activation annealing to form a diffused layer; measuring the sheet resistance of the diffused layer at one point on the surface of the wafer; placing the reference wafer in the epitaxy reactor, the reactor being set at a desired temperature and having a neutral gas flowing therein; and measuring the sheet resistance at the same point and calculating the difference between the two values of sheet resistance, this difference representing the thermal cycle undergone by the reference wafer during its stay in the epitaxy reactor.

Abstract: A database method and method of using the database for determining the carrier concentration profile of a semiconductor, wherein the database includes a first set of first data, the first data being a correction factor; and a second set of second data, each of the second data including first and a second set of parameters, the first set of parameters characterizing the carrier concentration profile and the second set of parameters characterizing the measurement technique. Each data of the first set of first data is obtained from one data of the second set of data through simulation or calculation.

Abstract: A method for detecting open circuits in a semiconductor device, more specifically in a static CMOS device. A device to be tested is powered-up and the clock on the device is stopped so that the device enters a quiescent state. Once the device has reached a quiescent state a first current is measured and after a specified period of time a second current is also measured. The first current and the second current are then compared to determine if there is a defect, i.e. an open circuit, in the device. The determination as to whether or not a device is defective is based upon the difference between the first and second current measurements.

Abstract: A method for monitoring the temperature of a product wafer during thermal processing of the product wafer in an emissivity independent thermal processing system includes processing a test wafer in the emissivity independent thermal processing system that thermally processes the product wafer. The test wafer is pretreated before being thus placed in the thermal processing system. The test wafer is thermally processed following a substantially same thermal processing recipe as that used for thermal processing of the product wafers. After the thermal processing of the test wafer, a sheet resistance of the test wafer is measured. This sheet resistance is correlated to a wafer temperature at the test wafer that was achieved during the thermal processing of the test wafer.