Abstract: A test and measurement apparatus and method wherein a software implemented phase lock loop recovers a clock signal associated with the received data signal, the recovered clock signal being used to do TIE measurement, to generate eye diagram and to do mask testing.

Abstract: A space-saving test structure includes a core metal line, at least one extrusion detection line and an extrusion monitoring segment. The core metal line has a “non-linear configuration” and is capable of conducting current for an electromigration test, an isothermal test, and extrusion monitoring. The at least one extrusion detection line is situated adjacent to the core metal line. The extrusion monitoring segment is electrically connected to the at least one extrusion detection line. The extrusion monitoring segment is adapted to determine whether an extrusion occurs in the core metal line by measuring a resistance between the core metal line and the at least one extrusion detection line.

Abstract: A method for testing tunnel oxide on a memory-related structure. In one method embodiment, the present invention accesses a memory-related structure during a manufacturing process. Next, the present embodiment applies a constant voltage to a gate of the memory-related structure. The present embodiment then measures a first gate current for the memory-related structure when the constant voltage is initially applied, to obtain a first value. Next, the present embodiment measures a second gate current for the memory-related structure a period of time after the constant voltage is initially applied to obtain a second value. A calculation of ratio of the second value to the first value is then performed. The present embodiment then generates a graph of the first value and the ratio of the second value to the first value as a function of time, wherein a decrease in the graph signifies stress induced electron trapping behavior of the tunnel oxide.

Abstract: A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).

Abstract: A circuit for measuring mechanical stress impressed on a printed circuit board includes a number of electrically conductive pads formed on at least one outer surface of the printed circuit board, and a resistive material applied in a pattern to the printed circuit board and defining a resistor between first and second ones of the number of electrically conductive pads. The resistive material exhibits an electrical resistance that varies as the resistive material is deformed so that the resistor exhibits an electrical resistance value that varies as a function of mechanical stress impressed on the printed circuit board sufficient to deform the resistive material defining the resistor. Any number of such resistors may be formed on or within the printed circuit board, and any such resistor may form part of an external resistor bridge network configured to monitor changes in its resistance value.

Abstract: A migration measuring method based on an alternating current impedance method, including steps: direct current with fine alternating current superposed is applied across electrodes (1), (2) to measure the impedance there between; and a surface static capacity (c) is calculated from the measured value of impedance in order to measure migration in accordance with the variation of the calculated surface static capacity.

Abstract: A system and method for measuring a resistance or a resistance per square, Rsq, of a material having a surface using a multi-point probe comprising four or more collinear contact points placed in the interior of the sample, the method comprising: making a first measurement using a first set of probe electrodes for inducing a current and a second set of probe electrodes for measuring the voltage difference when the current is induced; making a second measurement using a set of probe electrodes different from the first set for inducing a current and a set of probe electrodes different from the second set for measuring the voltage difference when the current is induced; and using a known relationship among the currents induced, the voltages measured, the nominal probe positions and the resistance per square to determine the resistance per square such that measurement errors resulting from positioning of the probes are reduced.

Abstract: A highly sensitive, non-contact tank probe to measure surface conductance of thin film structures, and a method for using the same, are described. The tank probe includes inductor (L), capacitor (C) and resistor (R) circuitry that is driven by a signal generator at the probe's resonant frequency. The conductance of a film structure specimen is determined from measuring the signal that is reflected from the tank probe and it respective frequency. Various types of information can be obtained from the tank probe. For instance, information as to film thickness, doping concentration, and the presence of defects can be obtained. In one embodiment of the invention, the tank probe is formed of integrated circuits within a semiconductor substrate. Another aspect of the present invention pertains to a method of using the tank probe system to measure the conductivity of a material specimen.

Abstract: An apparatus for contactless measurement of carrier concentration and mobility includes a microwave source, a circular waveguide for transmitting microwave radiation to a sample, such as a semiconductor wafer or panel for flat panel displays, at a measurement location, a first detector for detecting the forward microwave power, a second detector for detecting the microwave power reflected from the sample, and a third detector for detecting the Hall effect power. A circular waveguide, carrying only the TE11 mode, is terminated by the sample behind which a short is located. Perpendicular to the plane of the sample (and along the axis of the circular waveguide), a magnetic field is applied. In this configuration, a given incident TE11 wave will cause two reflected waves. One is the ordinary reflected wave in the same polarization as the incident one. A detector is provided to measure this reflected radiation. The other reflected wave is caused by the Hall effect.

Abstract: According to one exemplary embodiment, a method for establishing a relationship between Joule heating in a conductor and a current density in the conductor is implemented by performing wafer level measurements. According to this exemplary embodiment, wafer level measurements are performed to arrive at a temperature coefficient of resistance in the conductor. The method also includes determining a thermal resistance of the conductor. The thermal resistance is then utilized to establish a relationship between Joule heating in the conductor and the current density in the conductor. The relationship so obtained is then utilized to determine design rules, mean time to fail, and other information to aid in the design of reliable semiconductor devices. According to another exemplary embodiment, a wafer level measurement system is utilized to establish a relationship between Joule heating in a conductor and a current density in the conductor.

Abstract: For locating an extrusion from an interconnect, an extrusion monitor structure is formed to surround the interconnect and is separated from the interconnect by a dielectric material. A first via is coupled to the interconnect, and a second via is coupled to the extrusion monitor structure and separated from the first via by a via distance (Lv). The extrusion is located at an extrusion site distance (Lextrusion) from the first via and between the first and second vias to short-circuit the interconnect to the extrusion monitor structure. A resistance (Rtotal) between the first and second vias is measured, and the Lextrusion is determined from a relationship with Rtotal, Lv, and resistivities and dimensions of the interconnect and the extrusion monitor structure.

Abstract: A switching regulator that has first, second, third and fourth terminals, a first power transistor disposed between the first terminal and a first node, a second power transistor disposed between the first node and a second node, a filter including a capacitor and an inductor, and a controller. The first power transistor is partitioned into a plurality of individually-addressable first transistor segments. The second node couples the second and fourth terminals. The second power transistor is partitioned into a plurality of individually-addressable second transistor segments. The inductor is disposed between the first node and the third terminal, and the capacitor is disposed between the third and fourth terminals.

Abstract: The novel apparatus permits precise measurements of parasitic capacitances. The apparatus has a test structure and a reference structure, each with two conductor tracks. In the reference structure, the two conductor tracks are always at the same potential. In the test structure, one conductor track is coupled to ground potential and the other conductor track to a different potential. The test structure and the reference structure are connected to a voltage potential and the charge which builds up on the test structure and the reference structure is registered. The parasitic capacitance can be calculated precisely from the charge difference. The conductors of the test structure and of the reference structure are arranged in such a way that each conductor perceives a relationship to capacitive parasitic effects in the same environment.

Abstract: A fringing capacitance measurement probe and a method for determining a surface dielectric constant. The fringing capacitance measurement probe includes a planarized surface probe element for making interfacial planar contact with a measurement surface, the planarized surface having a metal conductive line portion and an insulating area portion to form a measuring area. The perimeter portion of the metal conductive line portion has a length greater than the perimeter length of the measuring area such that a fringing capacitance of the measurement surface may be determined.

Abstract: A method and system for determining an operating voltage for a semiconductor device. A first plurality of lifetimes may be determined for a first plurality of semiconductor device where the polysilicon lines in each of the first plurality of semiconductor devices have the same total area but different peripheral lengths. A second plurality of lifetimes may be determined for a second plurality of semiconductor devices where the polysilicon lines in each of the second semiconductor device have the same peripheral length but different total areas. Further, the STI structures (used to separate one or more active areas) in each of the second plurality of semiconductor devices may have the same length as the STI structures (used to separate one or more active areas) in each of the first plurality of semiconductor devices. The operating voltage may be determined based on the first and second plurality of lifetimes.

Abstract: The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (&dgr;) which minimizes the standard deviation of the function F to be obtained (step ST1.

Abstract: A test circuit is included in an IC wafer for testing the reliability of ICs under high current stress. The test circuit includes two sensing transistors, a select transistor, and a resistor. The two ends of the resistor are coupled to two sense terminals through the two sensing transistors. One end of the resistor is also coupled to a first stress input terminal; the other end of the resistor is coupled to a second stress input terminal through the select transistor. When the test circuit is selected, the sensing and select transistors are turned on. A current path is formed between the two stress input terminals, and a voltage differential can be measured across the resistor using the two sense terminals. Row and column select circuits enable the rapid testing of many resistor sizes and configurations in an array of such test circuits.

Abstract: A probe assembly for use with a calibration/validation robot to calibrate/validate a plurality of semiconductor tester channels is disclosed. The probe assembly includes a bracket adapted for mounting to the robot and a probe element for engaging test points disposed on the semiconductor tester channels. A magnetic attach/release mechanism cooperates with the bracket and probe element to allow for the separation of the probe element from the bracket whenever the probe element meets a force that exceeds a predetermined value.

Abstract: A device and automated method of calculating bulk states information and interface states information of a thin film transistor from a current-voltage measurement and a capacitance-voltage measurement comprising the steps of: calculating the flat band voltage from the input capacitance-voltage measurement; applying a general expression of Gauss's Law and the calculated flat band voltage to a capacitance voltage relationship which define capacitance so as to calculate a relationship between gate surface potential and gate/source voltage; applying Gauss's Law to the calculated relationship between gate surface potential and gate/source voltage to thereby calculate and ouput the interface states; calculating conductance/gate voltage data from the current-voltage measurement using the calculated flat band voltage; conducting an initialisation process using the calculated conductance/gate voltage data and the calculated relationship between gate surface potential and gate/source voltage, said initialisat

Abstract: An interrogation of a switched state of a switch is carried out with a high interrogation current until a closed switch is detected. The following interrogations of the switched state are then carried out with a low interrogation current until a definable time period which runs starting from a detection of the closed switch or until a definable number of interrogations which is counted starting from the detection of the closed switch is exceeded. After the expiry of the time period or the number of interrogations, the interrogation is continued with the high interrogation current until a closed switch state of the switch is detected again.

Abstract: In the present method of electrically testing the width of a line, a short pulse of laser energy is applied to the line to generate conductive electrons therein. An electrical potential is applied to the line to cause electrons to flow in the line, and current is measured to determine the width of the line.

Abstract: In order to provide an IC tester which can measure noise measuring performance in a position where a DUT to be analyzed on an evaluation board is mounted quantitatively, a noise evaluation circuit comprises a reference resistor which generates thermal noise, a reference noise generator a summing circuit, an amplifying circuit which amplifies result of the calculation in the summing circuit, a switch, and an evaluation board having the reference resistor, the reference noise generator, the summing circuit, the amplifying circuit, and the switch thereon for evaluating the DUT to be evaluated. Two kinds of electricity value which is output by the amplifying circuit by an on/off operation of the switch are calculated with noise figure F according to three kinds of electricity value including electricity value such as the reference noise electricity.

Abstract: In the present invention, an apparatus of testing leakage current protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern composed of a length portion, multiple tooth portions which are connected orthogonally to the length portion, and vias which are formed vertically from the ends of the tooth portions, respectively, through an interlayer dielectric layer. Additionally the apparatus has a serpentine-like pattern including a length parallel part or a connection part which is running parallel to the length portion, a tooth parallel part which is parallel to the tooth portion and formed at a level different from the level of the connection part or the length parallel part, and vias connecting them. The via of the comb-like pattern is located at the central position between the neighboring two vias of the serpentine-like pattern.

Abstract: In order in a method for measuring the resistance across discharge times of a capacitor to eliminate the interfering influence of the resistance values of electronic switches, the invention provides for a capacitor to be repeatedly charged and discharged and the charging or discharging time is measured by means of at least one resistor (R1, R2, R3) and at least one first switch (S11, S21 or S31) connected in series therewith, at least one second switch (S12, S22 or S32) connected in series with the resistor (R1, R2 or R3) and juxtaposed, parallel-connected switches (S11, S12 or S21, S22 or S31, S32) connected in series with the resistor (R1, R2 or R3).

Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule.

Abstract: A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.

Abstract: A method for measuring the step height of a STI structure is described. The method involves measuring the change in resistance of a polysilicon structure as the step height changes. The resistance of the polysilicon structure is measured by applying a voltage and measuring the resulting current.

Abstract: A method for determining contact resistance between an automated test equipment (ATE) system and a device under test (DUT). The DUT is configured to drive a known voltage to a pin. The ATE system is then controlled to force a first test current into the DUT at that pin. A board precision measurement unit (BPMU) of the ATE system then measures the voltage VM+ required to force the first test current. The ATE system is then controlled to force a second test current to flow out of the DUT at the same pin. The ATE system controls the second test current to have the same magnitude (but opposite direction) as the first test current. The BPMU then measures the voltage VM− required to force the second test current. The contact resistance is then determined in response to the measured voltages VM+ and VM−, and the magnitude of the test current.

Abstract: The invention relates to a method and arrangement for passivating the surface of semiconductor samples in which, simultaneously to passivation, the life-time of free carriers is also determined by illuminating the semiconductor sample by a light pulse of higher energy than the forbidden band of the material, and the time function of the resistance change occurring in the semiconductor as a result of illumination is measured advantageously by a microwave reflectometer, and the life-time of carriers is determined as the characteristic time constant of the process. The essence of the method lies in that, the surface part of the semiconductor sample to be measured is continuously electrically charged. The arrangement comprises a microwave reflectometer (2), a signal processing unit (3), and a laser light source (4) illuminating the semiconductor sample (1). The surface of the semiconductor sample (1) charged by ions generated by corona generators (5, 6) simultaneously with the measurement.

Abstract: In accordance with the present invention, a method is described which facilitates heat transfer from a silicon die after the silicon die is bonded to a substrate. An alignment tool is used to align the spacer with the silicon die. A thermal conductor can be placed on the silicon layer after the silicon layer has been bonded to the substrate layer. A die interface material is not necessarily applied between the silicon die and the thermal conductor. A spacer is used between the substrate and the thermal conductor. The spacer can facilitate heat transfer from the die. The spacer can facilitate force transfer from the thermal lid to the die. The spacer allows a thermal conductor to be affixed to the silicon die without use of a die interface. An alignment tool is used to align the spacer with the silicon die.

Abstract: An apparatus for the automated measurement and recording of the electrical resistivity of a semiconductor boule or ingot using the method of four probes has a four point boule support grid is provided adjacent to the home position of a four tip probe which is equipped with three axis linear mobility, rotational capability, and computer control, to provide automated mapping and testing of an “as grown” or ground semiconductor boule with cropped ends, for obtaining and recording resistivity data.

Abstract: A switching regulator that has first, second, third and fourth terminals, a first power transistor disposed between the first terminal and a first node, a second power transistor disposed between the first node and a second node, a filter including a capacitor and an inductor, and a controller. The first power transistor is partitioned into a plurality of individually-addressable first transistor segments. The second node couples the second and fourth terminals. The second power transistor is partitioned into a plurality of individually-addressable second transistor segments. The inductor is disposed between the first node and the third terminal, and the capacitor is disposed between the third and fourth terminals.

Abstract: In measuring the resistance value of an output buffer, a supply voltage is supplied to a first P-channel transistor in its source through an ammeter provided within an IC tester, a ground potential is supplied from the IC tester to a first N-channel transistor in its source, and a voltmeter provided within the IC tester is connected to a first external output terminal. A test control signal is then brought to a high level. Further, a test signal of a plurality of bits, which brings only a first test control signal to a high level while brining the remaining 2nd to nth test control signals to a low level, is input into a decoder. As a result, the first P-channel transistor and the first N-channel transistor are brought to an ON state, while 2nd to nth external output terminals are brought to a high-impedance state.

Abstract: A process to assess the occurrence or the likelihood of a failure in an integrated circuit. The process includes forming a conductive region such as a runner about the periphery of a substrate or die. The conductive regions may be located at one or more different metallization layers within the integrated circuit. The conductive region is coupled to one or more of the bond pads. The die is assessed by measuring the resistance, conductivity, cross talk or other electrical characteristics on the conductive region via the bond pads. The assessment can then be used to predict whether, for example, the runners formed in the integrated circuit have failed or are likely to fail.

Abstract: A test structure and method for testing a semiconductor material is provided with a semiconductor wafer having an electrical ground and a source of electrical potential. A conductor layer is placed over the semiconductor wafer and a semiconductor material is placed over the conductor layer. A dielectric layer is placed over the semiconductor material. Conductive top and bottom layers are placed over the dielectric layer and the bottom of the semiconductor wafer. The conductive top layer is connected to the electrical ground. The conductive bottom layer is connected to the source of electrical potential. The current flow is measured from the conductive bottom layer to the conductive top layer.

Abstract: A migration measuring method based on an alternating current impedance method, including steps: direct current with fine alternating current superposed is applied across electrodes (1),(2) to measure the impedance there between; and a surface static capacity (c) is calculated from the measured value of impedance in order to measure migration in accordance with the variation of the calculated surface static capacity.

Abstract: In a quasi-hemispherical Fabry-Perot resonator for the non-destructive determination of the surface resistance Rs of electrically conductive thin material films, spherical and planar mirrors are disposed opposite each other in a double shielded cooled resonator space structure supported on individual base plates and the planar mirror, on which a wafer with the thin material film is supported, is mounted on a support arm which extends through the double shield structure. Shield sections through which the support arm extends are supported on pivot arms which are pivotally mounted in the center of the base plates and the shield sections are engaged by the support arm so that they move along with the support arm when the support arm is moved sidewardly for a positioning change of the planar mirror thereby preventing radiation leakage from the resonator space.

Abstract: A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type.

Abstract: In an electroplating machine having a number of cathode electrodes which are simultaneously brought into contact with a silicon wafer to be electroplated in a semiconductor device fabricating process, a detector for detecting a contact resistance anomaly in a number of cathode electrodes includes a testing wafer which is formed of a circular silicon wafer and which has a number of metal film strips formed on one surface of the circular silicon wafer, separately from each other, so that the number of cathode electrodes can be individually brought into contact with the number of metal film strips, respectively. When the cathode electrodes are individually brought into contact with the metal film strips, respectively, a measuring tool is used to measure a contact resistance between each of the number of cathode electrodes and a corresponding one of the number of metal film strips.

Abstract: Non-contact methods for determining a property of an insulating film are provided. One method includes measuring an amount of hysteresis in the insulating film without contacting the insulating film. The method also includes determining the amount of hysteresis in the insulating film. Computer-implemented methods for data analysis are also provided. One computer-implemented method includes determining a single numeric value representing an amount of hysteresis in an insulating film from electrical characteristics of the insulating film. The electrical characteristics are measured without contacting the insulating film. In addition, systems that include a measurement system and a computer-usable carrier medium are provided. The measurement system is configured to measure an amount of hysteresis in an insulating film without contacting the insulating film.

Abstract: A semiconductor device includes a circuit board, a semiconductor element that is mounted on an upper surface of the circuit board and has an electrode terminal, and a sealing resin for sealing a periphery of the semiconductor element that is mounted on the upper surface of the circuit board. The circuit board includes a plurality of conductive members and an insulating substance for binding and fixing the plurality of conductive members. Each of the plurality of conductive members includes a conductive material formed integrally from the upper surface through the lower surface of the circuit board, and an insulating material covering an outer circumference of the conductive material. The conductive material of at least one conductive member of the plurality of conductive members is exposed to the upper surface of the circuit board.

Abstract: The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (&dgr;) which minimizes the standard deviation of the function F to be obtained (step ST1.

Abstract: A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type.

Abstract: A wafer suitable to be tested for current-perpendicular to the plane resistance includes a substrate, a conductive base layer on the substrate, a magnetic multilayer on the conductive base layer, and a top conductive layer. A testing ring is formed on the magnetic multilayer in a manner whereby it is separated from rest of the magnetic multilayer by a trench in the magnetic multilayer. Within the testing ring, the magnetic multilayer includes a hole. The current perpendicular to the plane resistance of the wafer may be determined by passing a predetermined current perpendicular through the testing ring by contacting a probe to the testing ring and measuring the voltage at the conductive base layer. The probe used in the present invention may be an AFM or a STM probe.

Abstract: The present invention provides a check pattern for evaluating the result of via openings during fabrication of a semiconductor device. The check pattern uses a Wheatstone bridge circuit so as to eliminate any influence of variation of wiring resistance and/or contact resistance. In the bridge circuit, four terminals are provided, namely first, second, third and fourth terminals. Each of four sides of the bridge circuit is defined by connecting an upper conductor layer including one terminal, a sub-group of via openings belonging to one group, a lower conductor layer, the other sub-group of via openings belonging to the same group, and an upper conductor layer including another terminal.

Abstract: In order to monitor the amount of heavy metal contamination in a wafer, the monitoring method comprising the steps of: setting a wafer for monitoring an amount of heavy metal contamination in a prescribed monitoring place, performing thermal treatment to the wafer at a temperature in the range from 1150° C. to 1350° C. in an atmosphere of O2+He or an atmosphere of H2+He, performing thermal treatment to the wafer at a temperature in the range from 900° C. to 1000° C. in an atmosphere of N2+O2 or an atmosphere of O2, and measuring an amount of heavy metal contamination in the wafer.

Abstract: In the present invention, an apparatus of testing leakage current protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern composed of a length portion, multiple tooth portions which are connected orthogonally to the length portion, and vias which are formed vertically from the ends of the tooth portions, respectively, through an interlayer dielectric layer. Additionally the apparatus has a serpentine-like pattern including a length parallel part or a connection part which is running parallel to the length portion, a tooth parallel part which is parallel to the tooth portion and formed at a level different from the level of the connection part or the length parallel part, and vias connecting them. The via of the comb-like pattern is located at the central position between the neighboring two vias of the serpentine-like pattern.

Abstract: In order to provide an IC tester which can measure noise measuring performance in a position where a DUT to be analyzed on an evaluation board is mounted quantitatively, a noise evaluation circuit comprises a reference resistor which generates thermal noise, a reference noise generator a summing circuit, an amplifying circuit which amplifies result of the calculation in the summing circuit, a switch, and an evaluation board having the reference resistor, the reference noise generator, the summing circuit, the amplifying circuit, and the switch thereon for evaluating the DUT to be evaluated. Two kinds of electricity value which is output by the amplifying circuit by an on/off operation of the switch are calculated with noise figure F according to three kinds of electricity value including electricity value such as the reference noise electricity.

Abstract: It is an object of the present invention to provide a semiconductor-producing/examining device which can maintain a preferable connection state for a predetermined period of time and which can easily remove a ceramic substrate from a supporting case. The present invention is a semiconductor producing/examining device comprising: a ceramic substrate having a conductor layer formed on the surface thereof or inside thereof; and a supporting case; in which an external terminal is connected to the conductor layer, wherein a connection between the conductor layer and the external terminal is performed such that the external terminal is pressed on the conductor layer or the external terminal is pressed on another conductor layer connected to the conductor layer by using the elastic force and the like of an elastic body.

Abstract: Apparatus and method for measuring surface resistivity of a wafer (12). A source of high frequency radiation (6, 41) emits an incident wave burst that impinges the wafer at a desired spot location. A reflected wave burst is detected at an appropriate time window by a receiver (8, 42). The relationship between incident and reflected energies is a function of the surface resistivity of the wafer.