By Information On Device Under Test Patents (Class 324/750.18)
  • Patent number: 11761983
    Abstract: The present disclosure provides a wafer probe card including: a non-magnetic printed circuit board (PCB) having a first side and a second side opposite the first side, the first side configured to face a magnet; a plurality of connection structures provided on the first side of the non-magnetic PCB; and a Hall sensor unit fixedly provided on the first side of the non-magnetic PCB, the Hall sensor electrically connected to at least one of the plurality of connection structures.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: September 19, 2023
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Guoquan Teo, Meng Yew Seah, Yongshun Sun, Eng Huat Toh
  • Patent number: 11724354
    Abstract: Various examples of the present technology disclose a self-contained and programmable Processing Probe Apparatus (PPA) that can measure processing properties of a processing tool. The PPA comprises one or more sensors, an analog-to-digital converter and information (ADCI) processor, an electrical power source (EPS), and a digital signal communication device, all of which are attached to a flexible film. The flexible film can be mounted on a substrate that mimics a semiconductor workpiece.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: August 15, 2023
    Assignee: Ioneer, LLC
    Inventor: Anthony Chen
  • Patent number: 11703541
    Abstract: A semiconductor inspecting method for ensuring a scrubbing length on a pad includes following steps. First off, a first position of a probe needle from above is defined. In addition, a wafer comprising at least a pad is placed on a wafer chuck of a semiconductor inspecting system. Thereafter, a relative vertical movement between the probe needle and the pad is made by adopting a driving system of the semiconductor inspecting system to generate a scrubbing length on the pad. Next, whether the scrubbing length is equal to or larger than a preset value or not is recognized by adopting the vision system and the relative vertical movement is stopped by adopting the driving system.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: July 18, 2023
    Inventors: Volker Hansel, Sebastian Giessmann, Frank Fehrmann, Chien-Hung Chen
  • Patent number: 11674978
    Abstract: A measurement system is described. The measurement system comprises a measurement device and a probe unit, wherein the measurement device comprises an image analysis circuit or module. The probe unit comprises at least one image sensor, wherein the at least one image sensor is connected to the image analysis module in a signal transmitting manner. The image sensor is configured to capture an image of a measurement area being associated with a device under test. The image analysis module is configured to analyze the image captured and to determine at least one characteristic quantity of the image captured via an image analysis technique. The image analysis module is further configured to gather an information concerning a test position of the probe unit from the at least one characteristic quantity. Further, a method for operating a measurement system is described.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: June 13, 2023
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Bernhard Sterzbach
  • Patent number: 11486899
    Abstract: A wafer test system includes a probe apparatus, a data server, an automation subsystem, and a probe mark assessment subsystem. The probe apparatus includes a probe card, a tester, and a camera. The probe card includes probe pins for contacting test pads in the wafer, and the camera captures an image of the test pads. The automation subsystem obtains an image specification from the probe apparatus and triggers an automated assessment of a probe mark in the image of the test pads. The probe mark assessment subsystem performs the automated assessment of the probe mark in the image of the test pads. The probe mark assessment subsystem performs an image-processing operation to obtain a probe mark assessment result, and the automation subsystem stops the probe apparatus if the probe mark assessment result indicates a probe test failure.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: November 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chia-Lin Tsai, Wun-Ye Ku, Tien-Yu Chen, Chia-Yi Lin
  • Patent number: 11340259
    Abstract: A probe card management system includes inspection apparatuses that inspect an inspection object and a management apparatus that manages a state of a probe card. Each inspection apparatus includes a camera that captures an image of a tip of each needle provided on the probe card, an inspection part that measures a state of the tip from the image, and inspects the inspection object by bringing the tip into contact with each test pad based on the measurement result, and supplying an electrical signal to the inspection object through the tip; and a transmission part that transmits the measurement result and a number of executions of the inspection to the management apparatus. The management apparatus includes a threshold specification part that specifies a first threshold value, and a notification part that notifies an outside of the number of executions and the first threshold value.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: May 24, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Shinjiro Watanabe
  • Patent number: 10643909
    Abstract: A method for inspecting the influence of an installation environment upon a processing apparatus includes setting a mark for specifying a relative positional relation between a chuck table and a processing unit, imaging the mark plural times by using an imaging unit when a moving unit is at rest, and detecting the position of the mark from an image and then determining whether or not the influence of the installation environment upon the processing apparatus is present based on whether the change in position of the mark is less than or more than a threshold.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: May 5, 2020
    Assignee: DISCO CORPORATION
    Inventor: Hiroyuki Yoshihara
  • Patent number: 10557889
    Abstract: Methods and systems for a universal device multi-function test apparatus are provided. Specifically, the universal device multi-function test apparatus is configured to receive multiple device types, manufacturers, and/or models attached to a nest via an interface module. The device can then be subjected to a battery of tests in a unified and controlled test environment. Information related to the initiated tests, even including results, may be associated with the device and stored in memory, written to the device, and/or forwarded for further processing/repair operations.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: February 11, 2020
    Assignee: Flextronics AP, LLC
    Inventors: Adam Montoya, Niklas Ake Torberntsson
  • Patent number: 10486203
    Abstract: A substrate cleaning method includes: steps (a) to (d). In step (a), a liquid is supplied onto a nanoimprint template substrate that has a patterned surface with foreign particles to form a liquid film on the patterned surface. In step (b), the liquid film is solidified to form a solidified film including the foreign particles. In step (c), the substrate is reversed. In step (d), the solidified film is melted to remove the foreign particles.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: November 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hideaki Sakurai, Kyo Otsubo, Kenji Masui, Tetsuo Takemoto, Minako Inukai, Masato Naka
  • Patent number: 10365323
    Abstract: Probe systems and methods for automatically maintaining alignment between a probe and a device under test (DUT) during a temperature change. The methods include collecting an initial image of a planar offset fiducial and determining an initial height reference of a height offset fiducial. The methods further include changing a temperature of the DUT, automatically maintaining a planar alignment between a probe and the DUT during the changing, and automatically maintaining a height alignment between the probe and the BUT during the changing. The probe systems include a chuck, which defines a support surface configured to support a substrate that includes the DUT, and a probe head assembly, which includes a probe configured to contact a corresponding contact pad of the DUT. The probe systems further include a substrate thermal module, which is configured to regulate a temperature of the DUT, and a controller programmed to execute the methods.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 30, 2019
    Assignee: FormFactor Beaverton, Inc.
    Inventors: Peter Douglas Andrews, David Michael Newton, David Randle Hess
  • Patent number: 10338134
    Abstract: In an interface board for testing a multichip package, the multichip package includes a first type semiconductor chip and a second type semiconductor chip, the interface board includes a first surface facing the multichip package and a second surface facing a test apparatus, the first surface includes upper terminals that are electrically connected to terminals of the multichip package, the second surface includes lower terminals that are electrically connected to the test apparatus, and the upper terminals include a first upper terminal group for testing the first type semiconductor chip and a second upper terminal group for testing whether a crack defect exists in the second type semiconductor chip.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Chul Jun, Yun-Bo Yang, Dong-Ho Lee, Tae-Hwan Oh, Dong-Han Yoon
  • Patent number: 10324126
    Abstract: A method for aligning probe pins with respect to positions of electronic devices comprises conducting contact stamping on a first electronic device with the probe pins to form first probe marks on lead pads of the first electronic device, capturing an image of the first electronic device, determining positions of the first probe marks on the first electronic device using the captured image, calculating an offset using the positions of the first probe marks, adjusting relative positions between a subsequent plurality of electronic devices and the probe pins using the offset, and contacting lead pads of the subsequent plurality of electronic devices with the probe pins for testing said electronic devices. The first probe marks are configured to have greater visibility as compared with second probe marks formed when contacting the lead pads of the subsequent plurality of electronic devices with the probe pins, so as to improve the accuracy of the offset calculated.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: June 18, 2019
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD.
    Inventors: Yu Sze Cheung, Hon Kam Ng, Chun Shing Yip
  • Patent number: 10067180
    Abstract: Provided is a semiconductor device including a substrate, insulating layers on the substrate, interconnection lines in or between the insulating layers, and pads on the insulating layers. The pads may include signal pads connected to the interconnection lines, and measurement pads disposed spaced apart from the signal pads and electrically connected to corresponding ones of the signal pads by the interconnection lines. Misalignment of probes contacting the semiconductor device may be detected by detecting a signal communicated between one or more of the measurement pads and the signal pads.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: September 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Junhee Lee
  • Patent number: 9632110
    Abstract: A semiconductor inspection device (1) equipped with a contacting unit (7) having a contacting side surface (7a) electrically contacting a semiconductor element (3), and which inspects the semiconductor element (3) by making the contacting unit (7) electrically contact the semiconductor element (3). The contacting side surface (7a) is provided with a plurality of projecting units (13), and the semiconductor element inspection device (1) is equipped with a hitting mark detecting unit (11) configured to detect hitting marks of the projecting unit (13) transferred to the semiconductor element (3) when the contacting side surface (7a) contacts the semiconductor element (3), and a control unit (17) configured to determine whether or not an inspection of the semiconductor element (3) is performed appropriately, on the basis of the hitting marks detected by the hitting mark detecting unit (11).
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: April 25, 2017
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Shigeto Akahori, Shinyu Hirayama, Hiroyuki Yamagishi, Yoko Yamaji
  • Patent number: 9632133
    Abstract: A circuit board testing system includes a testing fixture and a computer system. The testing fixture includes a contact element, a switching circuit, and a data acquisition unit. The contact element is connected with a circuit board. The switching circuit is connected with the contact element. By enabling the switching circuit, the data acquisition unit acquires a real voltage value corresponding to the electronic component. The computer system is connected with the testing fixture for converting the real voltage value into a real resistance value corresponding to the electronic component. According to the real resistance value, the computer system judges whether the electronic component passes the test.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: April 25, 2017
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventor: Pei-Ming Chang
  • Patent number: 9581640
    Abstract: A method for performing an operation on an article, the article including a plurality of fiducial marks and a set of features. A digital imaging system is used to capture a digital image of the article, which is analyzed to determine spatial relationships between positions of the features and positions of the fiducial marks. The article is positioned in proximity to an instrument and a fiducial sensing system including a plurality of fiducial sensors is used to determine positions of the fiducial marks. Predicted positions of the features are determined responsive to the determined spatial relationships and the determined fiducial mark positions. The position of the instrument or the article is adjusted responsive to the predicted positions of the features, and the instrument is used to perform an operation on the article.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: February 28, 2017
    Assignee: EASTMAN KODAK COMPANY
    Inventor: Eric Karl Zeise
  • Patent number: 9557374
    Abstract: A system is used to perform an operation on an article, the article including a plurality of fiducial marks and a set of features. A digital imaging system captures a digital image of the article, which is analyzed to determine spatial relationships between positions of the features and positions of the fiducial marks. The article is positioned in proximity to an instrument and a fiducial sensing system including a plurality of fiducial sensors is used to determine positions of the fiducial marks. Predicted positions of the features are determined responsive to the determined spatial relationships and the determined fiducial mark positions. The position of the instrument or the article is adjusted responsive to the predicted positions of the features, and the instrument is used to perform an operation on the article.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: January 31, 2017
    Assignee: EASTMAN KODAK COMPANY
    Inventor: Eric Karl Zeise
  • Patent number: 9347979
    Abstract: A prober system comprises a chuck, sensor and processing circuit. The chuck is configured to horizontally move a semiconductor wafer having a plurality of dies to position a selected group of the dies for parallel testing and vertically move the wafer to press the selected group of dies in contact with probes of a tester probe card. The sensor is configured to measure the vertical movement of the chuck when the wafer is on the chuck. The processing circuit is configured to control the horizontal and vertical movement of the chuck to test different groups of the dies, determine a total number of touchdowns between the wafer and the probes based on the vertical movement of the chuck measured by the sensor and associate each of the touchdowns with a location of the wafer contacted by the probes during that touchdown. A corresponding test data analysis system is also provided.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 24, 2016
    Assignee: Infineon Technologies AG
    Inventors: Stefan Pesl, Robert Schütz
  • Patent number: 9041421
    Abstract: An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: May 26, 2015
    Assignee: MEDIATEK INC.
    Inventors: Chun-Hsien Peng, Pei-Wei Chen, Ping-Hsuan Tsu, ChiaYu Yang, Chun-Yu Lin
  • Publication number: 20150054536
    Abstract: A device of one embodiment includes a sensor, an indicator electrically connected to the sensor, a first base portion including a plurality of first channels, a second base portion including a plurality of second channels and located between the first base portion and the sensor, and a plurality of pins. Each pin includes first and second ends, and each pin passes through a respective first channel and a respective second channel such that the first end extends beyond the first base portion away from the sensor and the second end extends beyond the second base portion toward the sensor. Each pin is adjustably disposed within the respective first and second channels such that each pin is operable to move along a longitudinal axis of the pin. Furthermore, the sensor is operable to determine whether all pins of the plurality of pins are positioned proximate to the sensor.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Inventor: Donald Jay Rackley
  • Patent number: 8963573
    Abstract: According to an example implementation, a universal tester includes a host interface slot connected to a first pluggable host card during an electrical test mode of operation to provide a stressed electrical signal to a host under test. The host interface slot is connected to a second pluggable host card during an optical test mode of operation, the second pluggable host card including an electrical-optical conversion block to convert a stressed electrical signal to a stressed optical signal that is provided to a host under test. A stressor generator may operation in pass-through mode or a loop-back mode.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 24, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: D. Brice Achkir, Marco Mazzini, Stefano Riboldi, Cristiana Muzio
  • Publication number: 20140347080
    Abstract: An exemplary printed circuit board testing method includes determining whether there is an open shielding box every a time interval. The method then transmits a first control signal including a first predetermined path to a robot when there is an open shielding box. Next, the method obtains an image captured by a camera and recognizes a unique identifier of a to-be-tested PCB in the obtained image. The method then determines a second predetermined path corresponding to the determined open shielding box, and transmits a second control signal comprising the determined second predetermined path to the robot. Next, the method closes the determined shielding box when a duration after transmitting the second control signal reaches a predetermined time, and controls a testing software to test the to-be-tested PCB, to generate a testing result corresponding to the unique identifier of the to-be-tested PCB.
    Type: Application
    Filed: March 27, 2014
    Publication date: November 27, 2014
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., FU TAI HUA INDUSTRY (SHENZHEN) CO., LTD.
    Inventors: YONG LI, YUN-QING LIU, XI-SONG SHUAI
  • Publication number: 20130321014
    Abstract: A testing apparatus for testing a number of different characteristics of a circuit board includes at least two probes, at least one measuring meter, and a storage device. After a circuit schematic diagram of the circuit board and a circuit wiring diagram of the circuit board have been compared, the location of each electric contact is determined. The probes necessary for testing particular characteristics are connected in turn to the measuring meter. The circuit board is moved to align the electric contacts with the probes, and bring the probes into electrical contact with the electric contacts for testing.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 5, 2013
    Inventor: QI-LONG YU
  • Patent number: 8461857
    Abstract: The present invention relates to a distance adjustment system and a solar wafer inspection machine provided with the system. The inspection machine has a conveyer for carrying a solar wafer, an optical inspection system for inspecting the surface and color appearance of the wafer and an illumination inspection system. A holder is provided in the inspection position where the wafer is clamped along its width direction to prevent the wafer from offset. During the opto-electrical inspection, probes are brought into contact with conductive buses of the wafer and light is applied to the wafer to allow the probing of electric energy thus generated. An adjusting device is employed to adjust the clamping gap of the holder and the distance of the probes in accordance with the size of the solar wafer. The data are collected and transmitted to a sorting system for sorting the wafer.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 11, 2013
    Assignee: Chroma Ate Inc.
    Inventor: Chia-Hung Lai
  • Patent number: 8345951
    Abstract: A binarizing method for binarizing an original image of an electrode pad on a substrate. The method includes the steps of processing an electrode image to generate a binary image of the electrode by binarzing the original image with a first threshold value, calculating a contact trace area to calculate the contact trace area including a portion that is predicted to be a trace of an object that contacted the electrode from the binary image of the electrode, processing a contact trace image to generate the contact trace area binary image by binarizing the original image of the area extracted by the contact trace area extracting unit with a second threshold value different from the first threshold value, and synthesizing the images to synthesize the binary image of the electrode and the contact trace area binary image by taking a logical sum on a corresponding pixel to pixel basis.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: January 1, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Junya Sato
  • Patent number: 8154308
    Abstract: A method of detecting small changes to a complex integrated circuit measuring RF/microwave scattering parameters between every pin over a wide frequency range. The data from a characterization of a known good integrated circuit is stored and compared to each subsequent integrated circuit of unknown background.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: April 10, 2012
    Assignee: The Boeing Company
    Inventor: Brian K. Kormanyos
  • Patent number: 8093918
    Abstract: An electronic device that includes an actual operation circuit that operates during an actual operation of the electronic device, a second test circuit and a third test circuit that operate during a test of the electronic device, and a power supply section. The power supply section, during the actual operation of the electronic device, does not apply a power supply voltage to the second test circuit and applies power supply voltages to the actual operation circuit and the third test circuit. The power supply section, to obtain identification of the electronic device, applies a power supply voltage to the second test circuit.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: January 10, 2012
    Assignees: National University Corporation Tohoku University, Advantest Corporation
    Inventors: Toshiyuki Okayasu, Shigetoshi Sugawa, Akinobu Teramoto
  • Patent number: 7982487
    Abstract: A test apparatus for determining layer-to-layer misregistration of a multiple layer printed circuit board having an electrical test pattern formed on an inner layer and an electrical test reference formed on an outer layer with the reference electrically connected to the pattern. The apparatus includes a holder for the board, an electrical input device that moves into and out of connection with the reference when the board is in the holder, with the input device adapted to provide a signal to the reference, and an electrical output probe configured to move into and out of electrical connection with the pattern when the board is in the holder. The output probe is adapted to receive at least one signal from the pattern when a signal is provided to the reference, such that the signal received by the output probe conveys layer-to-layer misregistration between the inner layer and the outer layer.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: July 19, 2011
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Orrin Paul Lorenz, Anthony A. Primavera, Howard Lee Bentley
  • Publication number: 20110109336
    Abstract: In a positioning method and apparatus capable of preventing a solar battery panel from suffer damage during inspection, the method includes steps of providing a transport platen, a set of positioning device, a first probe row and a second probe row; transporting the solar battery panel to an inspecting region by the transport platen; moving the positioning devices to position the solar battery panel step by step; the first probe row pressing an electrode line on one surface of the solar battery panel; the second probe row pressing an electrode line on the other surface of the solar battery panel, thereby electrically connecting the first probe row and the second probe row. In this way, the solar battery panel can be inspected accurately without suffering damage.
    Type: Application
    Filed: November 6, 2009
    Publication date: May 12, 2011
    Inventors: Yu-Hsing LIN, Jin-Po Tsa, Che-Min Lin, Po-Wen Peng
  • Patent number: 7893699
    Abstract: An identification device for electronic circuits comprises at least two electronic components having different electronic characteristics, a detection unit configured to detect at least one electrical parameter determining the electronic characteristics of the electronic components and an evaluation unit configured to evaluate a mismatch exhibited by the at least two electronic components with respect to each other. In order to distinguish different electronic circuits, the at least one electrical parameter of the electronic components is detected by the detection unit and is analyzed by the evaluation unit.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: February 22, 2011
    Assignee: Infineon Technologies AG
    Inventor: Heiko Koerner