Relative Positioning Or Alignment Of Device Under Test And Test Structure Patents (Class 324/750.16)
  • Patent number: 10948384
    Abstract: A position detection switch is provided with a case having a cylindrical part that has a plurality of ribs on an inner circumferential wall thereof along the axial direction thereof. Accordingly, the strength of the case is increased and running of a molten resin for fixing a substrate disposed on the inside are improved when the molten resin is injected from a long groove of the case. The contact surface area between the ribs and a sheath is increased whereby durability against an external force and temperature variation is increased.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 16, 2021
    Assignee: SMC CORPORATION
    Inventor: Jiro Mandokoro
  • Patent number: 10948518
    Abstract: A test apparatus for testing electronic device comprises a lower base, an upper base and a pressing force generating module disposed between the upper and lower bases. The lower base having a chip socket for receiving a plurality of probes, and a test socket plate having a first guiding device, each of the probes has a spring force stored therein. The upper base having a second guiding device coupled to the first guiding device. When an electronic device is placed in the chip socket, and the upper base is slidably moved with respect to the lower base by the cooperative actions between the first and second guiding devices, so that the pressing force generating module is in alignment with the electronic device for applying a pressing force on the electronic device, and the pressing force being greater than the sum of the spring forces generated by the plurality of probes.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: March 16, 2021
    Assignee: CHROMA ATE INC.
    Inventors: Chien-Ming Chen, Meng-Kung Lu, Yung-Chih Chen
  • Patent number: 10935570
    Abstract: There is provided an intermediate connection member which is provided between a first member having a plurality of first terminals and a second member having a plurality of second terminals and electrically connects the plurality of first terminals and the plurality of second terminals, respectively, the intermediate connection member including: a pogo block including a main body and a plurality of pogo pins provided in the main body, the pogo block configured to connect the plurality of first terminals and the plurality of second terminals, respectively; and a pogo frame having an insertion hole into which the pogo block is inserted, wherein the pogo block has a positioning pin, and the pogo frame has a positioning hole into which the positioning pin is inserted, and wherein the pogo block is positioned with respect to the pogo frame when the positioning pin is inserted into the positioning hole.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 2, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jun Fujihara, Hiroaki Sakamoto
  • Patent number: 10876988
    Abstract: Component for use in mineral processing are described including a substantially electrically conductive layer of elastomeric material; and two or more measurement points in the form of electrical connections are provided at different points of the electrically conductive layer.
    Type: Grant
    Filed: May 13, 2017
    Date of Patent: December 29, 2020
    Inventors: Edward Humphries, Michael Hambe
  • Patent number: 10859861
    Abstract: According to one implementation, a dual-mode augmented reality and virtual reality viewer (AR/VR viewer) includes a device configured to provide AR and VR effects, the device including a display screen, a VR shield, and a transparency control unit coupled to the VR shield. The AR/VR viewer also includes a computing platform for generating the AR and VR effects communicatively coupled to the device. The display screen has a user facing first surface for receiving the AR and VR effects, and a second surface opposite the user facing first surface. The display screen or a transmissive layer adjoining the display screen is configured to have a variable transparency. The VR shield is configured to be one of substantially transparent in an AR mode and substantially opaque in a VR mode under the control of the transparency control unit.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: December 8, 2020
    Assignee: Disney Enterprises, Inc.
    Inventors: Randall Davis, Nathan Nocon
  • Patent number: 10852322
    Abstract: A high-frequency testing probe having a probe substrate and at least two probe tips. The probe substrate is a printed circuit board and the probe tips are coupled to and extend outward from the printed circuit board. The first and second probe tips are each communicatively coupled to respective first and second probe connectors through respective first and second conducting traces disposed upon the printed circuit board. The probe connectors are configured to couple the testing probe to at least one of a high-frequency vector network analyzer and a high-frequency time domain reflectometer. The probe tips translate along their respective central longitudinal axes through respective adjustable couplings to modify respective distances the probe tips extend outward from the printed circuit board.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: December 1, 2020
    Assignee: SIGNAL MICROWAVE, LLC
    Inventors: William Rosas, Eric Gebhard, Brian Shumaker
  • Patent number: 10802048
    Abstract: A universal test socket including a first sub-layer including a plurality of first through conductors, the plurality of first through conductors arranged at a first pitch in a first substrate, and a second sub-layer including a plurality of second through conductors, the second sub-layer stacked on the first sub-layer so that the plurality of first through conductors are in contact with the plurality of second through conductors, the plurality of second through conductors arranged at a second pitch in a second substrate, the second pitch being less than or equal to the first pitch may be provided.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daisuke Yamada, Dong-uhn Shin
  • Patent number: 10718789
    Abstract: According to one embodiment, there is provided a common test board including a socket board, an IP evaluation board, and a common board. To the socket board, a semiconductor device is to be connected. On the IP evaluation board, the socket board is able to be attached. On the common board, the IP evaluation board is able to be attached.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 21, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Onda, Seiji Sakurai
  • Patent number: 10622231
    Abstract: A method of manufacturing a semiconductor package includes obtaining a plurality of individual chips classified according to a test bin item as a result of performing an electrical die sorting (EDS) process including testing electrical characteristics of a plurality of chips at a wafer level, packaging the individual chips on corresponding chip mounting regions of a circuit substrate and forming a plurality of individual packages based on position information of the chip mounting regions, each of the individual packages having test bin item information corresponding to the test bin item, classifying the plurality of individual packages according to the test bin item based on the test bin item information, and testing the individual packages classified according to the test bin item.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-chan Ahn, Won-young Kim, Kyung-seon Hwang
  • Patent number: 10613137
    Abstract: Methods and apparatus are described relating to a probe assembly having a probe head securing mechanism that includes a lock ring housing and a lock ring disposed in the lock ring housing. In an example, a probe assembly includes a rigid substrate, a circuit board coupled to the rigid substrate, and a probe head securing mechanism. The probe head securing mechanism includes a lock ring housing and a lock ring disposed within the lock ring housing. The circuit board has a surface. The lock ring housing is coupled to the rigid substrate. The circuit board is disposed between the lock ring housing and the rigid substrate. The lock ring is rotatable relative to the lock ring housing. Rotation of the lock ring is configured to move the lock ring in a direction perpendicular to the surface of the circuit board.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: April 7, 2020
    Assignee: XILINX, INC.
    Inventors: Mohsen H. Mardi, Lik Huay Lim, King Yon Lew, Andy Widjaja
  • Patent number: 10573605
    Abstract: A method of assessing vulnerability of Integrated Circuit (IC) can include: preparing a list of logic nets of the IC; obtaining rectangular segments from the logic nets; finding a milling exclusion area based on a covering wire; and superimposing the found milling exclusion area onto the rectangular segments of the logic nets. The milling exclusion area is an area that microprobing attack does not succeed without cutting off at least one of the rectangular segments.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: February 25, 2020
    Assignees: University of Florida Research Foundation, Incorporated, The University of Connecticut
    Inventors: Mark M. Tehranipoor, Domenic J. Forte, Navid Asadizanjani, Qihang Shi
  • Patent number: 10535575
    Abstract: An interposer includes a substrate having a mounting area and a test area, first conductive plugs separate from each other, the first conductive plugs being disposed along a first direction and into the test area of the substrate, a first line pattern group including first non-conductive patterns disposed on first centers of the first conductive plugs, and first conductive patterns disposed to bridge first peripheries of a first adjacent pair of the first conductive plugs, and first pads connected to the first conductive patterns at both first ends of the first line pattern group.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: January 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shaofeng Ding, Kyoung-woo Lee, In-hwan Kim, Jong-woon Lee
  • Patent number: 10495683
    Abstract: A test instrument performs a power supply stress test by invoking current surges in a device under test. The current surges are invoked by stimulating functional blocks in the device under test with test signals received via a network interface of the device under test.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: December 3, 2019
    Assignee: VIAVI SOLUTIONS DEUTSCHLAND GMBH
    Inventor: Reiner Schnizler
  • Patent number: 10424030
    Abstract: A system and computer implemented method for estimating difficulty of a document includes retrieving a subject document from a storage, setting difficulty of each keyword included in the subject document to locality of the keyword in the subject document as an initial value, estimating, by a processor, difficulty of each subject document by a statistical processing of the difficulties of keywords included in the subject document, and updating the difficulty of each keyword based on the difficulty of each subject document depending on a significance value of the keyword in the subject document.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yohei Ikawa, Shoko Suzuki
  • Patent number: 10386388
    Abstract: It is described a contact probe for a testing head for a testing apparatus of electronic devices, the probe comprising a probe body extended in a longitudinal direction between respective end portions adapted to contact respective contact pads, the second end being a contact tip adapted to abut onto a contact pad of the device under test, the body of each contact probe having a length of less than 5000 ?m, and including at least one pass-through opening extending along its longitudinal dimension. Conveniently, the at least one pass-through opening is filled by a filling material, in order to define at least one first and one second lateral portions in the body, being parallel and joined to each other by a connecting central portion realized by the filling material at the pass-through opening, the connecting central portion made of the filling material acting as a strengthening element.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 20, 2019
    Assignee: TECHNOPROBE S.P.A.
    Inventors: Daniele Acconcia, Raffaele Vallauri
  • Patent number: 10215774
    Abstract: The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: February 26, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10048290
    Abstract: A probe card device includes a testing circuitry board, a flexible probe needle, a first solder portion, a second solder portion and an interconnected holder electrically connected to the testing circuitry board and the flexible probe needle in which one end of the interconnected holder is coupled to the flexible probe needle with the first solder portion, and the other end of the interconnected holder is coupled to a conductive pad of the testing circuitry board with the second solder portion. A first desoldering melting point of the first solder portion is higher than a second desoldering melting point of the second solder portion.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: August 14, 2018
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chieh Liao, Yu-Min Sun, Chih-Feng Cheng
  • Patent number: 9983232
    Abstract: A prober for testing devices in a repeat structure on a substrate is provided with a probe holder plate, probe holders mounted on the plate, and a test probe associated with each holder. Each test probe is displaceable via a manipulator connected to a probe holder, and a substrate carrier fixedly supports the substrate. Testing of devices, which are situated in a repeat structure on a substrate, in sequence without a substrate movement and avoiding individual manipulation of the test probes in relation to the contact islands on the devices, is achieved in that the probe holders are fastened on a shared probe holder plate and the probe holder plate is moved in relation to the test substrate.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: May 29, 2018
    Assignee: Cascade Microtech, Inc.
    Inventors: Frank-Michael Werner, Matthias Zieger, Sebastian Giessmann
  • Patent number: 9915698
    Abstract: A device of contacting a substrate with a probe card includes a mounting table 15 that transfers a wafer W together with a wafer plate 24 to a position facing the probe card 19; a lifting device 15a that contacts multiple electrodes of semiconductor devices formed on the wafer W with multiple probes of the probe card 19 by moving the wafer plate 24 and the wafer W toward the probe card 19 and then further moves the wafer W toward the probe card 19; a depressurization path 26 that decompresses a space S between the probe card 19 and the wafer plate 24 and maintains a contact state between the electrodes of the semiconductor devices and probes 19b of the probe card 19; and the lifting device 15a that separates a chuck member 14 on the mounting table 15 from the wafer plate 24.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: March 13, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroshi Yamada
  • Patent number: 9903885
    Abstract: Techniques are described to provide a universal direct docking tester to prober interface between the test head and a prober of semiconductor wafer prober for testing die within semiconductor wafers. In an implementation, a universal direct docking tester to prober interface includes a tray assembly configured to be mounted within an opening of the prober housing and a stiffener assembly configured to be mounted to a test head to support a load board PCB that includes a probe head. The stiffener assembly includes a skirt that is received in the tray assembly when the test head is interfaced with the prober to position the load board PCB within the prober to facilitate engagement of the probe head with the wafer.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: February 27, 2018
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Morris R. Fox, Paras P. Shah, Eric G. Anusevicius, Ricardo C. Pakingan, Reinhardt B. Gatchalian
  • Patent number: 9863977
    Abstract: A method of contacting a substrate with a probe card in a substrate inspection apparatus can inspect electrical characteristics of semiconductor devices on the substrate. A wafer W is transferred to a position facing a probe card 36 while being mounted on a chuck member 22 with a wafer plate 37 therebetween, and electrodes of semiconductor devices on the wafer W are contacted with probes of the probe card 36 by moving the wafer W and the wafer plate 37 toward the probe card 36 through an elevating device 43. Then, the wafer W is overdriven toward the probe card 36 and a contact state between the electrodes of the semiconductor devices and the probes of the probe card 36 is maintained by decompressing a space S between the probe card 36 and the wafer plate 37. Then, the chuck member 22 is separated from the wafer plate 37.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: January 9, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kunihiro Furuya, Hiroshi Yamada, Takanori Hyakudomi, Jun Mochizuki
  • Patent number: 9810973
    Abstract: A mechanical camera bracket for mounting different accessories to the camera is disclosed that ensures a positive lock through the central hub from which extend a first arm and a second arm, allowing for accessories to be attached and detached without having to remove the entire bracket. The central hub has a clamping knob and defining a common axis about which the first arm and second arm rotate. A first bushing and second bushing are rotatable about the common axis in tandem with the first arm and second arm. The first bushing and second bushing each have a first ramp coupled to a first pressure cup in a first ball head camera mount and a second pressure cup in a second ball head camera mount. The clamping knob is configured to move the ramps along the common axis, thus urging the pressure cups against the ball heads.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: November 7, 2017
    Inventor: Sage Elmohtaseb
  • Patent number: 9807872
    Abstract: Provided is a circuit board including an inspection terminal, the circuit board including: a connection terminal, which is arranged on a front surface or in an inner layer of the circuit board and is electrically connected to an object to be inspected; an inspection terminal configured to measure a resistance value of the object to be inspected; and a connection wiring configured to electrically connect the object to be inspected and the inspection terminal to each other, the inspection terminal being arranged on a side surface of the circuit board, at least a part of the connection wiring being formed on a back surface or in the inner layer of the circuit board.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: October 31, 2017
    Assignee: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
    Inventor: Toshiki Onishi
  • Patent number: 9734984
    Abstract: A current quantity measuring method of multi-beams irradiates with a charged particle beam, amplifies an electric signal corresponding to multi-beams passed through a plurality of aperture holes of an aperture member having the plurality of aperture holes to form multi-beams by irradiation with the charged particle beam, receives the electric signal amplified in the minute current measurement unit and counting the number of electrons in the multi-beams, calculates a current quantity of the multi-beams passed through the plurality of aperture holes by using a product of the calculated number of electrons in the multi-beams and elementary charge, and corrects irradiation time of the charged particle beam of each of the plurality of aperture holes on the basis of the calculated current quantity.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: August 15, 2017
    Assignee: NuFlare Technology, Inc.
    Inventor: Hideyuki Iwata
  • Patent number: 9733299
    Abstract: An inspection jig may include a frame, an electrode body provided with electrodes, conductive contactors having a wire shape, a support block having a facing surface opposite to which an inspection circuit board is disposed, guiding one ends of the contactors to the inspection points of the circuit board mounted on the facing surface, guiding other ends to the electrodes, and configured to move relatively to the frame in a moving direction which crosses the facing surface, biasing parts configured to bias the support block in a direction moving away from the electrode body and close to the circuit board, and a regulating plate disposed between the support block and the frame so as to extend in a direction from the support block to the frame, having elasticity, and having regulation of deformation in a first direction which is parallel to the facing surface and which crosses the extending direction.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: August 15, 2017
    Assignee: NIDEC-READ CORPORATION
    Inventors: Norihiro Ota, Mitsunobu Tokimasa, Kosuke Hirobe, Kohei Tsumura
  • Patent number: 9726694
    Abstract: A probe apparatus has probe wires with a contact pattern on one side. The contact pattern is for contacting a respective contact pattern on another test equipment or component, such as a circuit board. The probe wires have tips that probe a device desired for testing. Signals are transmitted through the probe wires from the probe card, for example, through a circuit board to other diagnostic equipment. The contact of the probe card with the circuit board allows signals to be transferred through the probe wires to the other diagnostic equipment. On another side of the probe card is a connector structure. The connector structure includes a retainer that can allow the probe card to be replaced from a test system, such as allowing it to be connected and disconnected from a holder.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: August 8, 2017
    Assignee: Celadon Systems, Inc.
    Inventors: William A. Funk, John L. Dunklee, Bryan J. Root
  • Patent number: 9689916
    Abstract: In a method for determining a set value of a pressure for inspection in a wafer inspection apparatus, a surrounding space sealable between a chuck top and a probe card by a vacuum mechanism is evacuated and a highest negative pressure in the surrounding space is measured as a reference pressure when the chuck top has floated by the evacuation. Then as a reference height position, a height position of the chuck top corresponding to the reference pressure is obtained. Further, a pressure in the surrounding space is decreased to a level lower than the reference pressure, the pressure in the surrounding space, when the chuck top reaches a target height position obtained by adding a preset overdrive amount for a press-contact state between the probe card and the wafer to the reference height position, is measured and the measured pressure is set as the set value of the pressure.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: June 27, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroshi Yamada
  • Patent number: 9658250
    Abstract: A vertical probe device includes upper and lower dies having upper and lower installing holes, probe needles, a lower positioning film disposed between the dies and having lower positioning holes, and a dividing film disposed between the lower positioning film and the upper die and having through holes and dividing ribs. The needle tail is individually inserted through a lower installing hole. The needle head is individually inserted through an upper installing hole. Each lower positioning hole is located under at least one dividing rib and capable of accommodating a plurality of needle heads. Each needle head is inserted through a lower positioning hole and a through hole. Therefore, the films are easily installed, free of irregular hole but passable by narrow needle bodies, and facilitate easy and fast installation and less damage to the probe needles that are well positioned, and facilitate easy installation of the upper die.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 23, 2017
    Assignee: MPI CORPORATION
    Inventors: Hsiang-Sheng Hsieh, Sang-Yi Lin, Chih-Hao Hsu
  • Patent number: 9618536
    Abstract: A probe needle includes a head, a tail and a body connected between the head and the tail and provided with a first flat section curvedly extending from the head towards the tail for providing sufficient deformation when the tail is pressed on a device under test, and a second flat section neighbored to the first flat section for supporting the probe needle in between upper and lower dies. When the probe needles are used in a probe module, the probe needles can be arranged with a pitch same as that of the conventional probe needles even though the probe needles are formed from posts having a relatively greater diameter than that of the posts for making the conventional probe needles, such that the probe needles may have enhanced current withstanding capacity and prolonged lifespan.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: April 11, 2017
    Assignee: MPI Corporation
    Inventors: Chia-Yuan Kuo, Tien-Chia Li, Ming-Chi Chen, Chien-Chou Wu, Tsung-Yi Chen
  • Patent number: 9554474
    Abstract: A removable, permanent or reconfigurable debug probing device for use in debug probing of a printed circuit assembly, the printed circuit assembly having at least one through via, the debug probing device comprising at least one leader thread configured to be threaded through the at least one through via. Using the probing device comprises inserting a selected one of the at least one leader threads through a selected one of the at least one through via to thereby probe a surface of the printed circuit assembly; and responsive to detecting a defect in the selected through via, using a flexible circuit connected to the selected leader thread to repair the detected defect.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald K. Bartley, David J Braun, John R Dangler, Matthew S Doyle, Thomas D Kidd
  • Patent number: 9459279
    Abstract: An electrical testing machine includes a base having two parallel first rails, a platform provided on the base, a probe holder provided on the base and having a plurality of placement locations, a support provided between the first rails and having a second rail thereon, a test arm provided on the second rail and above the platform, a receiving seat provided on the test arm, and a plurality of probe sets, wherein one of the probe sets is engaged on the receiving seat, while the others are respectively provided on the placement locations. The support is movable relative to the base and the platform. The test arm is movable along with the support, and is also movable relative to the support. The receiving seat is movable or rotatable relative to the test arm. The probe set engaged on the receiving seat is movable along with the receiving seat.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: October 4, 2016
    Assignee: MPI CORPORATION
    Inventors: Wei-Cheng Ku, Shao-Wei Lu, Hung-Chih Sung, Chun-Nan Chen
  • Patent number: 9453879
    Abstract: An apparatus and method for determining performance of system is disclosed. While operating in a test mode, a plurality of test results may be received and stored in a memory. Each test result may be indicative of a performance of the system when the system is operating under a respective test condition. Also, during the test mode, a respective value of an operating parameter of a predetermined system element at each test condition. An association between each test result and a corresponding detected respective value of the operating parameter may be provided. During a normal operating mode, an operating value of the operating parameter may be determined. A performance level of the system based on a test value retrieved from memory dependent upon the operating value and the association may then be determined.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: September 27, 2016
    Assignee: Apple Inc.
    Inventors: Brian S. Leibowitz, Mohamed H. Abu-Rahma, Michael R. Seningen
  • Patent number: 9423424
    Abstract: A current-diverting guide plate for use in a probe module is disclosed to include a plate body having a first surface, a second surface opposite to the first surface, and a plurality of through holes penetrating through the first and second surfaces. A conducting layer is provided at a periphery wall of each through hole of the plate body and electrically coupled to a probe slidably inserted through the through holes. A current-diverting circuit trace is disposed on the first surface of the plate body and electrically connected with the conducting layers for diverting the electric current flowing through probes. Thus, the current-diverting guide plate can be used to prevent the probes from possible damage due to an excessive instantaneous current.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: August 23, 2016
    Assignee: MPI CORPORATION
    Inventors: Hsien-Ta Hsu, Horng-Kuang Fan
  • Patent number: 9335384
    Abstract: A method and apparatus for testing near field magnetic fields of electronic devices. The method comprises measuring a magnetic field using a loop antenna that is oriented in a first direction. The loop antenna is swept through a desired range of azimuth angles while measuring the magnetic field. Once the first direction testing is completed, the loop antenna is changed to a second orientation direction. The magnetic field is then measured in the second orientation direction and is swept through a desired range of orientation angles in the second direction. The apparatus provides a loop antenna connected to a coaxial probe, with the coaxial cable serving as the center conductor, and two outer conductors. An axle is mounted to the loop antenna and connected to a step motor. A servo motor is also provided for moving the arm assembly.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: May 10, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Kyu-Pyung Hwang, Young K. Song, Dong Wook Kim, Changhan Hobie Yun
  • Patent number: 9316670
    Abstract: The present invention is a probe array for testing an electrical device under test comprising one or more ground/power probes and one or more signal probes and optionally a gas flow apparatus.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: April 19, 2016
    Assignee: FormFactor, Inc.
    Inventor: January Kister
  • Patent number: 9201115
    Abstract: A wafer inspection apparatus includes a first and second wafer transfer mechanisms, an alignment chamber, a second wafer transfer mechanism and a plurality of inspection chambers. The first wafer transfer mechanism is installed at a first transfer area to transfer wafers individually from a housing. The alignment chamber has an alignment mechanism configured to align the wafer at an inspection position for an electrical characteristics inspection. The second wafer transfer mechanism is configured to transfer the wafer through a wafer retaining support in a second transfer area formed along the first transfer area and an alignment area. The plurality of inspection chambers is arranged at an inspection area formed along the second transfer area and is configured to inspect electrical characteristics of the wafer transferred by the second wafer transfer mechanism through the wafer retaining support.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: December 1, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroshi Yamada, Takaaki Hoshino, Shinji Kojima, Takeshi Saigusa, Hiroshi Shimoyama
  • Patent number: 9159698
    Abstract: A method for producing a semiconductor module arrangement includes providing a semiconductor module and a printed circuit board. The semiconductor module has a circuit mount populated with a semiconductor chip, an adjustment device in a first relative position with respect to the circuit mount, and a plurality of electrical connections each of which has a free end. Each of the connections is routed through a different passage opening in the adjustment device. The printed circuit board is pushed onto the electrical connections by each of the free ends being inserted into a different contact opening in the printed circuit board. The adjustment device is moved to a second relative position, which is different from the first relative position, with respect to the circuit mount.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: October 13, 2015
    Assignee: Infineon Technologies AG
    Inventor: Patrick Jones
  • Patent number: 9110097
    Abstract: A test system having a manipulation device and a test unit. The manipulation device has a receiving unit with a socket that accommodates a packaged integrated circuit, which has a top side and a bottom side. A plurality of electrical terminal contacts are formed on the bottom side. In a first state, the manipulation device provides the integrated circuit to the test unit, and during the first state the test unit is disposed above the top side of the integrated circuit and forms a connection with the manipulation device, and the test unit carries out a function test on the integrated circuit. A sensor device is formed on the top side, and the top side of the integrated circuit is oriented in a direction of the test unit and the electrical terminal contacts are electrically connected to the receiving unit of the manipulation device.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: August 18, 2015
    Assignee: Micronas GmbH
    Inventors: Sebastian Becker, Werner Kutscher
  • Patent number: 9024649
    Abstract: An insert for a semiconductor package testing apparatus comprises a body having a pocket constructed and arranged to receive the semiconductor package, and a sliding tool slidingly positioned on the body. The sliding tool is constructed and arranged to open and close the pocket as a result of a sliding motion of the sliding tool relative to the body.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Guiheum Choi, Minsu Kang, Teaseog Um, Seunghee Lee
  • Patent number: 9007085
    Abstract: A semiconductor package testing apparatus and testing a semiconductor package, the apparatus including a test circuit substrate that electrically tests a semiconductor package having connection terminals; a socket electrically connecting the test circuit substrate with the semiconductor package; a socket guide having an open region delimiting the socket; an insert that fixes the semiconductor package and positions the semiconductor package in the open region of the socket guide; a pusher that presses the semiconductor package to make contact between the socket and the semiconductor package; and an alignment part that aligns the semiconductor package with the open region, wherein the alignment part is configured to selectively apply a magnetic force to align keys of the semiconductor package, the align keys being formed of a magnetic material.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hunkyo Seo
  • Patent number: 9000785
    Abstract: A test structure may characterize the properties of a transistor including a DC test structure for testing DC properties of the transistor, and an AC test structure for testing AC properties of the transistor. The DC and AC test structures may have common test pads.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics SA
    Inventors: Clement Charbuillet, Patrick Scheer
  • Publication number: 20150091594
    Abstract: A test system including an embodiment having a sensor array adapted to test one or more devices under test in learning modes as well as evaluation modes. An exemplary test system can collect a variety of test data as a part of a machine learning system associated with known-good samples. Data collected by the machine learning system can be used to calculate probabilities that devices under test in an evaluation mode meet a condition of interest based on multiple testing and sensor modalities. Learning phases or modes can be switched on before, during, or after evaluation mode sequencing to improve or adjust machine learning system capabilities to determine probabilities associated with different types of conditions of interest. Multiple permutations of probabilities can collectively be used to determine an overall probability of a condition of interest which has a variety of attributes.
    Type: Application
    Filed: June 24, 2014
    Publication date: April 2, 2015
    Inventor: Brett J Hamilton
  • Patent number: 8994390
    Abstract: A probe apparatus has probe wires with a contact pattern on one side. The contact pattern is for contacting a respective contact pattern on another test equipment or component, such as a circuit board. The probe wires have tips that probe a device desired for testing. Signals are transmitted through the probe wires from the probe card, for example, through a circuit board to other diagnostic equipment. The contact of the probe card with the circuit board allows signals to be transferred through the probe wires to the other diagnostic equipment. On another side of the probe card is a connector structure. The connector structure includes a retainer that can allow the probe card to be replaced from a test system, such as allowing it to be connected and disconnected from a holder.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 31, 2015
    Assignee: Celadon Systems, Inc.
    Inventors: Bryan J. Root, William A. Funk, John L. Dunklee
  • Publication number: 20150077148
    Abstract: A data storage device may be tested during or after manufacture by a testing device that may have at least a work piece with at least one contact pad concurrently contacting bottom and sidewall surfaces of a probe tip with a centering feature of the at least one contact pad.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Applicant: Seagate Technology LLC
    Inventors: Leping Li, Jeffrey Robert O'Konski, Saravuth Keo, Pramit P. Parikh
  • Patent number: 8975904
    Abstract: A wafer inspection interface IF comprises a probe card, an adsorption unit configured to adsorb a wafer to the probe card, a wafer adsorption sealing member to which the probe card is adsorbed, and a fixing ring configured to fix the wafer adsorption sealing member to a card holder. The adsorption unit includes an air exhaustion unit, a first air duct whose right end portion is opened in the hermetically closed space and the left end portion is opened at a side of the fixing ring, a second air duct whose right end portion is opened to face an opening of the left end portion of the first air duct and the left end portion is opened to be connected with the air exhaustion unit, and a hole by which the first air duct is in communication with the second air duct.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: March 10, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Hiroshi Yamada
  • Publication number: 20150061713
    Abstract: Wire probes are described that resist rotation during assembly into a probe head of a die tester. One example includes probe wires with a protrusion at a pre-determined position along the length of the wire. A probe substrate with pads on one side each to attach to and electrically connect with a probe wire and a pads on the opposite side to connect to test equipment and a probe holder above the substrate with holes. Each hole holds a respective one of the probe wires against the probe substrate. Each hole also has a key to mate with a protrusion of a respective probe wire so that the protrusions engage the keys to prevent rotation of the respective wire.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Inventors: David Shia, Todd P. Albertson, Keith J. Mortin
  • Patent number: 8970235
    Abstract: A semiconductor test device and method for sequentially carrying out tests including an AC test, DC test, and thermal resistance test on a power semiconductor device are provided. The semiconductor test device includes a holding unit that positions the power semiconductor device. Test units each generate a test signal for the power semiconductor device and determine a test result generated in response to the test signal. A connection unit switches between the test units and selectively connects the test units electrically to electrodes of the power semiconductor device. The connection unit is controlled such that the test units are sequentially connected to the power semiconductor device to perform a plurality of the tests. The connection unit may include parallel plate electrodes in proximity to each other across an insulating sheet. The parallel plate electrodes may connect the power semiconductor device to positive and negative power sources of the test unit.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: March 3, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Atsushi Yoshida
  • Patent number: 8933719
    Abstract: A combined probe head being disposed in a space transformer of a vertical probe card is provided, in which the combined probe head is used for differentiating or segmenting a layout area of the probes in the vertical probe card. The combined probe head may include a locating plate and sub-probe heads. The locating plate may include fixed portions. Each sub-probe head may include corresponding sub-dies and probes inserted between the sub-dies, and each sub-probe head is assembled and fixed in the corresponding fixed portion. Therefore, the layout area of the probes in the vertical probe card can be respectively differentiated or segmented from the sub-probe heads in order to avoid mutual interference under repair process. In addition, a related method for assembling and aligning the above mentioned combined probe head is provided.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: January 13, 2015
    Assignee: MPI Corporation
    Inventors: Chao-Ching Huang, Wen-Chi Chen, Chiu-Chu Chang
  • Publication number: 20140354315
    Abstract: A probe guide plate used for a semiconductor inspection apparatus that inputs and outputs an electrical signal for inspecting an object via a probe needle, the probe guide plate includes a silicon substrate provided with a through hole that penetrates the silicon substrate from one surface to another surface through which the probe needle is inserted, the through hole including a first tapered portion provided at an end portion at the one surface side such that the hole size of which increases as it approaches the one surface, and a second tapered portion provided at an end portion at the other surface side such that the hole size of which increases as it approaches the other surface; and a silicon oxide film formed on an inner wall surface of the through hole including the first tapered portion and the second tapered portion.
    Type: Application
    Filed: May 2, 2014
    Publication date: December 4, 2014
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yuichiro SHIMIZU, Kosuke Fujihara
  • Patent number: 8901525
    Abstract: The present invention provides a panel alignment apparatus and a panel alignment method. The panel alignment apparatus comprises an image detection device and a first clamp. The method comprises the following steps: utilizing the image detection device to detect a position of a display panel, and to calculate a position adjustment value; and utilizing the first clamp to hold the standing display panel, and to rotate the display panel according to the position adjustment value for adjusting a position of the display panel. The present invention can utilize the clamps to precisely align the standing display panel.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: December 2, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Jiasheng Lu, Teng-chou Wei