Abstract: A semiconductor fabricating apparatus may include a probe card, a test head, a support and a chamber wall. The probe card may include a plurality of probing needles. The probe card may be installed at the test head. The support may be configured to receive a wafer including a plurality of test pads making contact with the probing needles. The chamber wall may be configured to receive the support. The chamber wall may define a chamber in which a probe test may be performed. At least one of the probe card and the support, the probe card and the test head, and the test head and the chamber wall may be combined with each other by a magnetic module.

Abstract: Described are various configurations for performing efficient optical and electrical testing of an opto-electrical device using a compact opto-electrical probe. The compact opto-electrical probe can include electrical contacts arranged for a given electrical contact layout of the opto-electrical device, and optical interface with a window in a probe core that transmits light from the opto-electrical device. An adjustable optical coupler of the probe can be mechanically positioned to receive light from the device's emitter to perform simultaneous optical and electrical analysis of the device.

Abstract: The test system provides an array of test probes. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and flex circuits continue the electrical connection from the probes to a load board. The test probes are bonded to the flex circuits by ring shaped flowable conductive material. The flex circuits are biased against a load board by an elastomeric pad of spaced part conical projections.

Abstract: A semiconductor device includes a substrate, a semiconductor package including a semiconductor chip, and a connector between the substrate and the semiconductor package, the connector having opposing first and second planar surfaces, the first planar surface in contact with the substrate and the second planar surface in contact with the semiconductor package. The connector also includes a plurality of wires extending between the first and second planar surfaces to electrically connect electrodes of the substrate to electrodes of the semiconductor package.

Abstract: Among other things, one or more techniques and/or systems are provided for shielding a signal pin. A signal pin, such as a signal pin within a probe card used to test electronic devices, such as integrated circuits, is shielded from interference signals, which are emitted from other signal pins within the probe card. Shielding the signal pin mitigates cross-talk issues and/or impendence control issues associated with signals that are carried by the signal pin. In one example, one or more shield pins are arranged with respect to the signal pin according to a shield configuration. For example, the shield configuration comprises a plane of signal pins, a substantially regular layout of signal pins, or a polygonal layout of signal pins, etc. In this way, one or more shield pins inhibit unintended interactions or effects that otherwise occur among two or more signal pins.

Abstract: A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair. In this way, no gasket is required to be disposed between the wafer and the wafer translator. Air, or gas, is evacuated from between the wafer and wafer translator through one or more evacuation pathways in the gasketless sealing means.

Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface.

Abstract: Resilient electrical interposers that may be utilized to form a plurality of electrical connections between a first device and a second device, as well as systems that may utilize the resilient electrical interposers and methods of use and/or fabrication thereof. The resilient electrical interposers may include a resilient dielectric body with a plurality of electrical conduits contained therein. The plurality of electrical conduits may be configured to provide a plurality of electrical connections between a first surface of the electrical interposer and/or the resilient dielectric body and a second, opposed, surface of the electrical interposer and/or the resilient dielectric body. The systems and methods disclosed herein may provide for improved vertical compliance, improved contact force control, and/or improved dimensional stability of the resilient electrical interposers.

Abstract: [Problems to be solved] To provide a test-use individual substrate capable of improving testing accuracy and connecting reliability. [Means for solving the Problems] A test-use individual substrate 30 which is used for testing a semiconductor wafer, comprises a main body portion 31, thin portions 321, 322 extending from the main body portion 31 and being relatively thinner than the main body portion, and bumps 33 provided on the thin portions 321, 322.

Abstract: Composite materials having conductive properties are described for use in testing circuits and in manufacturing electrical switches. The composite materials described, when in an unstressed state, generally behave as insulators. However, when sufficient mechanical pressure is applied to portions of the composite materials, the portions to which the mechanical pressure is applied become increasingly conductive. Methods for testing a PCB using composite material switches are also disclosed. A sheet that includes a composite material may be used to test electrical functionality of various regions on a PCB by way of local pressure application. The sheet may be easily applied to and removed from the PCB. Additionally, in forming an electrical switch, a voltage applied to one or more actuating elements may be used to provide mechanical pressure to a composite material that is disposed between two conductive members.

Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted.

Abstract: An electrical probe assembly includes a flexible circuit. A plurality of electrically conductive regions is on a first side of the flexible circuit. The flexible circuit is arranged about an axis formed by rolling the flexible circuit such that the electrically conductive regions form a plurality of isolated electrically conductive bands.

Abstract: An analyte sensor apparatus and a corresponding fluid medium, the analyte sensor apparatus comprising a sensing element, the external surface of which comprises a membrane to inhibit exposure of the sensing element; the corresponding fluid medium comprising a receptor species and an activatable species, the receptor species for interacting with an analyte to activate the activatable species, activation of the activated species causing increased porosity of the membrane of an in-contact analyte sensor apparatus to correspondingly increase exposure of the sensing element to allow for production of a detectable electrical signal which can be used to sense the presence of the analyte.

Abstract: A probing tip for a signal acquisition probe has a non-conductive substrate compatible with thin or thick film processing having opposing horizontal surfaces and side surfaces with two of the side surfaces converging to a point. A contoured probing tip contact is formed at the converging point on the non-conductive substrate with the probing tip contact having first and second intersecting arcuate surface. Electrically conductive material is deposited on the countered probing tip contact using thin or thick film processing for providing electrical contact to test points on a device under test. A resistive element is formed on the non-conductive substrate using thin film processing that is electrically coupled to the probing tip contact and to an input of an amplifier formed on an integrated circuit die mounted on the non-conductive substrate. The output of the amplifier is coupled to a transmission structure formed on a second non-conductive substrate.

Abstract: A wafer test probe for testing integrated circuitry on a die is disclosed. The wafer test probe includes a membrane core. The wafer test probe also includes circuitry within the membrane core. The circuitry within the membrane core includes at least one portion of an inductor. The wafer test probe further includes a probe tip.

Abstract: A substrate, preferably constructed of a ductile material and a tool having the desired shape of the resulting device for contacting contact pads on a test device is brought into contact with the substrate. The tool is preferably constructed of a material that is harder than the substrate so that a depression can be readily made therein. A dielectric (insulative) layer, that is preferably patterned, is supported by the substrate. A conductive material is located within the depressions and then preferably lapped to remove excess from the top surface of the dielectric layer and to provide a flat overall surface. A trace is patterned on the dielectric layer and the conductive material. A polyimide layer is then preferably patterned over the entire surface. The substrate is then removed by any suitable process.

Abstract: A microelectronic probe element can include a base, a tip, and a spring assembly coupled between the tip and the base. The spring assembly can include a first spring and a second spring, wherein the first spring has a negative stiffness over a predefined displacement range and the second spring has a positive stiffness over the predefined displacement range. The first spring and second spring can be coupled so that the negative stiffness and positive stiffness substantially cancel to produce a net stiffness of the tip relative to the base over the predefined displacement range.

Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted.

Abstract: An integrated high-speed probe system is provided. The integrated high-speed probe system includes a circuit substrate for transmitting low-frequency testing signals from a tester through a first probe of the probe assembly to a DUT, and a high-speed substrate for transmitting high-frequency testing signals from the tester to the DUT. The high-speed substrate extends from the upper surface of the circuit substrate in the testing area to the lower surface of the circuit substrate in the probe area for being adjacent to the probe assembly and electrically connecting the second probe. In this way, the tester can transmit testing signals of different frequencies through the integrated high-speed probe system.

Abstract: The present invention provides on IC test substrate for testing various signals, a combined flexible and rigid PCB included in the structure is applicable to perform a mission including for example: stabilizing power input/output, signal transfer by a connector; general, power, and high frequency signal transmission in preserved integrity state.

Abstract: Disclosed are a probe substrate and a probe card using the same. The probe substrate includes a ceramic stack structure stacked with a plurality of layers; vias disposed in the ceramic stack structure to perform inner-layer connection, and pads electrically connected to the vias; a contact opening disposed at the ceramic stack structure, and partially exposing the pads; and contact pads disposed at side walls of the contact opening, electrically connected to the pads, and electrically connected to pogo pins.

Abstract: A socket connector for electrically connecting a lead of a semiconductor device under test (DUT) with a tester includes a container having a chamber, a conductive end or plug that seals the chamber at one end, and a conductive membrane that seals the chamber at another end. A liquid conductive material fills the chamber. The conductive plug is arranged to be in electrical contact with the tester. The lead of the semiconductor DUT is in electrical contact with the conductive membrane and thus with the tester via the conductive membrane, the liquid conductive material and the conductive plug.

Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface.

Abstract: An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.

Abstract: A probe includes a plurality of boards each of which has a plurality of magnets, a plurality of the boards include a first board and a second board laid on the first board, a plurality of the magnets include a plurality of first magnets provided with the first board and a plurality of second magnets provided with the second board and arranged so as to respectively face a plurality of the first magnets, and the first magnet and the second magnet facing each other are provided so that mutually different magnetic poles face each other.

Abstract: A wafer test probe for testing integrated circuitry on a die is disclosed. The wafer test probe includes a membrane core. The wafer test probe also includes circuitry within the membrane core. The circuitry within the membrane core includes at least one portion of an inductor. The wafer test probe further includes a probe tip.

Abstract: A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair. In this way, no gasket is required to be disposed between the wafer and the wafer translator. Air, or gas, is evacuated from between the wafer and wafer translator through one or more evacuation pathways in the gasketless sealing means.

Abstract: A socket connector for electrically connecting a lead of a semiconductor device under test (DUT) with a tester includes a container having a chamber, a conductive end or plug that seals the chamber at one end, and a conductive membrane that seals the chamber at another end. A liquid conductive material fills the chamber. The conductive plug is arranged to be in electrical contact with the tester. The lead of the semiconductor DUT is in electrical contact with the conductive membrane and thus with the tester via the conductive membrane, the liquid conductive material and the conductive plug.