Abstract: A coaxial line is provided which includes: a first columnar conductor disposed inside a multilayer substrate such that one end thereof is coupled to a first stripline and that the other end thereof is coupled to a second stripline; and one or more second columnar conductors penetrating the multilayer substrate such that one end thereof is coupled to a ground layer and that the other end thereof is coupled to a ground layer, the first columnar conductor acting as an inner conductor, and the second columnar conductors acting as outer conductors. Each of the first and second striplines is coupled to an open stub acting as resonators and a matching conductor acting as capacitance matching elements.

Abstract: Provided is a current sensor having variable tuning precision capability depending on an amount of a current to be measured, a system state and the like. In the present disclosure, the current measurement apparatus having variable tuning precision capability does not separately require a current sensor measuring a small current with high precision and a current sensor stably measuring a large current without saturation. In the present disclosure, a single current measurement apparatus may vary current measurement precision depending on a current magnitude and the like, and may thus measure the small current with the high precision and stably measure the large current without saturation.

Abstract: The invention relates to a computer system, comprising a chassis, a system board, which is arranged in the chassis, and a first power supply unit, which is directly connected to the system board via at least one first plug connector. Furthermore, the computer system comprises an expansion board, which is arranged in the chassis and connected to the system board via at least one second plug connector. Furthermore, the computer system comprises a second power supply unit, which is directly connected to the expansion board via at least one third plug connector, and a circuit, which is arranged on the system board, wherein the circuit is connected to the at least one first plug connector and the at least one second plug connector and is configured to enable a power supply of the computer system selectively by the first power supply unit and/or the second power supply unit.

Abstract: An apparatus comprising: a passive array (202) of resistive elements (250); a row selector switch (204) and a column selector switch (206) configured to respectively connect a particular row and a particular column of resistive elements to ground; and a feedback column selector switch (208) configured to connect all columns of resistive elements to a voltage source, except for the particular column connected to ground by the column selector switch; the voltage source configured to apply a voltage to the columns of resistive elements, the voltage matching a voltage dropped over the resistive element connected in circuit by the row and column selector switches; and further comprising: a row selector switch compensation circuit (220), a column selector switch compensation circuit (240) and/or a feedback column selector switch compensation circuit (260) each configured to apply a voltage across a corresponding dummy element equal and opposite to a voltage dropped over the corresponding selector switch.

Abstract: A test device includes: a testing unit connected with a measurement line, and configured to apply bias to the measurement line and measure the measurement line; a plurality of switching units configured to electrically connect the measurement line and the plurality of samples; and a control unit configured to sequentially turn on the plurality of switching units to sequentially apply the bias to the plurality of samples. The control unit determines whether a corresponding device sample has a defect based on a first measurement value according to measurement by the testing unit when the bias is applied to each of the plurality of samples.

Abstract: The present invention discloses a semiconductor chip probe for measuring conducted electromagnetic emission (EME) of a bare die and a conducted EME measurement apparatus with the semiconductor chip probe. The semiconductor chip probe comprises a substrate, a dielectric layer, an impedance unit, a measuring unit and a connection unit. The measurement apparatus comprises a semiconductor chip probe, a high frequency probe, a signal cable and a test receiver. The integrated passive component network designed and embedded inside the semiconductor chip probe forms the 1? or 150? impedance network. And the semiconductor chip probe is able to directly couple the EME conducted current or voltage from the test pin of the flipped chip under test to the test receiver for measurement.

Abstract: A signal distribution structure for distributing a signal to a plurality of devices includes a first signal guiding structure including a first characteristic impedance. The signal distribution structure also includes a node, wherein the first signal guiding structure is coupled to the node. The signal distribution structure includes a second signal guiding structure including one or more transmission lines. The one or more transmission lines of the second signal guiding structure are coupled between the node and a plurality of device connections. The second signal guiding structure includes, side-viewed from the node, a second characteristic impedance which is lower than the first characteristic impedance. The signal guiding structure also includes a matching element connected to the node.

Abstract: A test coupler for supplying a device under test with test signals contains a first coaxial connector, a waveguide port, and a first strip conductor. Test signals of a lower frequency range are supplied to the first coaxial connector. Test signals of an upper frequency range are supplied to the waveguide port. The test coupler guides the test signals on the first strip conductor to the device under test.

Abstract: Systems and methods for simultaneous optical testing of a plurality of devices under test. These systems and methods may include the use of an optical probe assembly that includes a power supply structure that is configured to provide an electric current to a plurality of devices under test (DUTs) and an optical collection structure that is configured to simultaneously collect electromagnetic radiation that may be produced by the plurality of DUTs and to provide the collected electromagnetic radiation to one or more optical detection devices. The systems and methods also may include the use of the optical probe assembly in an optical probe system to evaluate one or more performance parameters of each of the plurality of DUTs.

Abstract: An object of the invention is to provide an inspection device which has a function of preventing electric discharge so that an absorbed current is detected more efficiently. In the invention, absorbed current detectors are mounted in a vacuum specimen chamber and capacitance of a signal wire from each probe to corresponding one of the absorbed current detectors is reduced to the order of pF so that even an absorbed current signal with a high frequency of tens of kHz or higher can be detected. Moreover, signal selectors are operated by a signal selection controller so that signal lines of a semiconductor parameters analyzer are electrically connected to the probes brought into contact with a sample. Accordingly, electrical characteristics of the sample can be measured without limitation of signal paths connected to the probes to transmission of an absorbed current. In addition, a resistance for slow leakage of electric charge is provided in each probe stage or a sample stage.

Abstract: A method and a circuit functionally test a semiconductor component. The functional test is performed with galvanic isolation by using a transformer. The test itself is based on determining the frequency-dependent impedance of a series circuit of capacitors and inductors using the semiconductor component itself. The impedance is strongly influenced by the conduction state of the semiconductor component, in other words, by the instantaneous conductivity or blocking capability of the semiconductor component.

Abstract: A probe card interface for interfacing a probe head with a first circuit. The probe card interface includes an impedance control element to interface a first set of pins of the probe head with the first circuit. The impedance control element is further configured to control the impedance of the first set of pins. The probe card interface includes a conductive plane to interface a second set of pins of the probe head with the first circuit. The conductive plane is further coupled to provide at least one of power or ground to the second set of pins.

Abstract: A probe card having a configurable structure for exchanging/swapping electronic components for impedance matching and an impedance method therefore are provided. In the probe card, an applied force is exerted on the electronic component so as to make the electronic component electrically connected with at least one conductive contact pad of a supporting unit. The supporting unit is a circuit board or a space transformer. In order to facilitate the exchange or swap of the electronic component, the applied force can be removed. The probe card includes a pressing plate which can be moved between a pressing position and a non-pressing position. The pressing plate has a pressing surface which is contacted with the top end of the electronic component while the pressing plate is in the pressing position. Therefore, the applied force can be generated or removed by changing the positioning of the pressing plate.

Abstract: Wireless electronic devices may include a transceiver, an antenna resonating element coupled to the transceiver via a transmission line path, transceiver and antenna impedance matching circuits, and other circuitry. The transceiver and the impedance matching circuits may be formed on a first substrate. The antenna resonating element may be formed using a second substrate. The antenna resonating element may be decoupled from the first substrate during testing. First and second sets of test points may be formed at first and second locations long the transmission line path. During testing, a test probe may mate with the first set of test points, whereas an impedance adjustment circuit that serves to electrically isolate the antenna impedance matching circuit from the transceiver may mate with the second set of test points. The impedance adjustment circuit need not be used if the antenna impedance matching circuit is decoupled from the transceiver during testing.

Abstract: A detecting circuit measures at least one response characteristic of an output channel in an electro-acoustic transducer system. A memory stores a plurality of equalizations, each equalization corresponding to a known electro-acoustic transducer system associated with at least one response characteristic stored in the memory. A processor in communication with the detecting circuit and the memory selects one of the stored response characteristics matching the response characteristic measured by the detecting circuit. In some cases, an appropriate equalization is loaded based on the selected response characteristic.

Abstract: A flicker noise test system includes a guarded signal path and an unguarded signal path selectively connectable to respective terminals of a device under test. The selected signal path is connectable a terminal without disconnecting cables or changing probes.

Abstract: A full duplex, high speed test interface comprises a tester side circuit and a device under test side circuit, each comprising balancing circuits. The balancing circuit of the test side circuit is configured to cancel its own transmitted data at the test side circuit such that the transmitted data does not influence any other signal generated at the test side circuit. Similarly, the balancing circuit of the device under test side circuit is configured to cancel its own transmitted data at the device under test side circuit such that the transmitted data does not influence any other signal generated at the device under test side circuit.

Abstract: An evaluation device 20 comprises a circuit element comprising respective pairs of inputs and outputs including several capacitances 25a-25c and resistances 26a-26d, one end of each being connected to both ends of the capacitances 25a-25c, wherein a resistance value of a signal input side is generally equal to that of a signal output side. The evaluation device 20 is further provided with a connecting terminal with an output device 10 for outputting signals to a device to be evaluated 30 on the signal input side, and is provided with a connecting terminal with the device to be evaluated 30 on the signal output side.

Abstract: This invention is an electrostatic discharge testing circuit that can deliver current pulses to a component under test (CUT) with a custom amplitude versus time profile shape. Pulse generation with customized shapes is accomplished by discharging an energy storage network comprised of capacitor(s), transmission line(s) and other passive components. Current pulses compliant to the European International Electrotechnical Commission IEC 61000-4-2 standard can be so produced. These current pulses are delivered to the CUT with low distortion through a constant impedance electrical path, such as a combination of cables and controlled impedance conductors of printed wiring boards compatible with packaged IC devices, assemblies, and wafer probes. The current pulses can be delivered with various impedances, and measurements made that allow the CUT currents and voltages to be calculated.

Abstract: A digital communications test system and method for testing a plurality of devices under test (DUTs) in which multiple sets of a single vector signal analyzer (VSA) and single vector signal generator (VSG) can be used together to perform error vector magnitude (EVM) measurements for one or more DUTs in parallel, including one or more of composite, switched and multiple input multiple output (MIMO) EVM measurements. This allows N pairs of a VSA and VSG to test N DUTs with NxN MIMO in substantially the sane time as a single VSA and VSG pair can test a single DUT, thereby allowing a substantial increase in testing throughput as compared to that possible with only a single VSA and VSG set.

Abstract: A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed.

Abstract: It is disclosed to measure the impedance of a read-out line. The read-out line includes at least two cascaded electrical circuit segments, each electrical circuit segment including two longitudinal arms, wherein one of the longitudinal arms includes an electrical component, and a lateral arm including a switch configured to close in the presence of an object in the vicinity of the switch. The measured impedance of the read-out line can be compared to a preset value corresponding to an allowable value of the impedance of the read-out line.

Abstract: The present disclosure provides a method for testing an integrated circuit having a load impedance. The method includes generating a first test signal having a first frequency and a second test signal having a second frequency, wherein the second frequency is greater than the first frequency, transmitting the first test signal to a substrate having a board circuit operable to process the first signal, transmitting the second test signal to a substrate, wherein the substrate includes an impedance matching circuit operable to transform the load impedance of the integrated circuit into a desired impedance for the second frequency, and sending the first and second test signals to the integrated circuit via the substrate.

Abstract: A test and measurement instrument including a port including a plurality of connections; an impedance sense circuit configured to sense an impedance coupled to a connection of the plurality of connections; and a controller configured to setup the test and measurement instrument in response to a sensed impedance from the impedance sense circuit.

Abstract: A system for providing a reference voltage includes a tester adapted to provide a predetermined current, a first ground pad connected to a ground voltage of the tester, a second ground pad connected between the tester and the first ground pad, the second ground pad being connected to the tester through first and second resistors, a reference voltage pad connected to a node between the first and second resistors, the reference voltage pad adapted to provide a test reference voltage, and a multiplexer connected to the reference voltage pad, the multiplexer configured to output the test reference voltage as a reference voltage during substantial voltage variation.

Abstract: A test apparatus for testing a device under test includes a test signal generating section that generates a test signal to be supplied to the device under test, a main driving section that outputs an output voltage determined in accordance with the test signal, to an input/output pin connected to a signal input/output terminal of the device under test, a replica driving section that outputs a comparison voltage determined in accordance with the test signal, a resistance voltage dividing section that generates a divided voltage by resistance-dividing the comparison voltage, a comparing section that compares a voltage of the input/output pin with the divided voltage, a judging section that judges acceptability of the device under test based on a result of the comparison by the comparing section, and an adjusting section that adjusts a voltage dividing ratio of the resistance voltage dividing section so that the divided voltage becomes equal to a voltage obtained by adding together a predetermined threshold volt

Abstract: A storage device transporter is provided for transporting a storage device and for mounting a storage device within a test slot. The storage device transporter includes a frame that is configured to receive and support a storage device. The storage device transporter also includes a conductive heating assembly that is associated with the frame. The conductive heating assembly is arranged to heat a storage device supported by the frame by way of thermal conduction.