Multiple Chip Module Patents (Class 324/757.05)
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Patent number: 8970244Abstract: One embodiment is a transport apparatus for moving carriers of microelectronic devices along a track, the transport apparatus including: (a) a track with two rails adapted to support the carriers; (b) a trolley adapted to be transported in a direction along the track by a linear actuator; and (c) a first and a second engagement feature attached to the trolley wherein the first engagement feature is adapted to engage temporarily with a first of the carriers, and the second engagement feature is adapted to engage temporarily with a second of the carriers; wherein a predetermined movement of the trolley slidably moves the first carrier onto a test position and slidably moves the second carrier off the test position simultaneously.Type: GrantFiled: September 24, 2010Date of Patent: March 3, 2015Assignee: Centipede Systems, Inc.Inventors: Thomas H. Di Stefano, Peter T. Di Stefano
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Patent number: 8779795Abstract: In a case where a semiconductor chip is mounted over a first package, 80 pads are coupled to 80 terminals of the package, and in a case where the semiconductor chip is mounted over a second package, 100 pads are coupled to 100 terminals of the second package. An internal circuit of the semiconductor chip operates as a microcomputer with 80 terminals in a case where electrodes are insulated from each other and operates as a microcomputer with 100 terminals in a case where the electrodes are shorted therebetween by an end part of a bonding wire. Therefore, a dedicated pad for setting the number of terminals of the packages is no longer required.Type: GrantFiled: July 24, 2012Date of Patent: July 15, 2014Assignee: Renesas Elecronics CorporationInventor: Yuta Takahashi
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Patent number: 8779788Abstract: A testing apparatus includes a thermal control chamber including a test room, which temperature is controlled within a testing temperature range; a carrier frame including a direction guiding unit installed securely within the test room and formed with one guiding groove and a carrier rod extending through the guiding groove in the direction guiding unit; and a clamping unit mounted on the carrier rod for clamping a display-panel module securely, wherein, movement of the carrier rod transversely within the guiding groove relative to the direction guiding unit results in disposing the display-panel module to extend along one of several testing directions for undergoing a burn-in test.Type: GrantFiled: December 30, 2011Date of Patent: July 15, 2014Assignee: Chroma Ate Inc.Inventors: Chi-Ren Chen, Chiang-Cheng Fan, Li-Hsun Chen
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Patent number: 8710859Abstract: Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.Type: GrantFiled: September 23, 2011Date of Patent: April 29, 2014Assignee: Powertech Technology Inc.Inventor: Kai-Jun Chang
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Patent number: 8648615Abstract: A method of testing a multi-die integrated circuit (IC) can include testing an inter-die connection of the multi-die IC. The inter-die connection can include a micro-bump coupling a first die to a second die. The method can include detecting whether a fault occurs during testing of the inter-die connection. Responsive to detecting the fault, the multi-die integrated circuit can be designated as including a faulty inter-die connection. Also described is an integrated circuit that includes a first die, a second die on which the first die may be disposed, a plurality of inter-die connections coupling the first die to the second die, and a plurality of probe pads, where each probe pad is coupled to at least one of the inter-die connections.Type: GrantFiled: June 28, 2010Date of Patent: February 11, 2014Assignee: Xilinx, Inc.Inventor: Arifur Rahman
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Patent number: 8609473Abstract: A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.Type: GrantFiled: October 12, 2011Date of Patent: December 17, 2013Assignee: ISC8 Inc.Inventors: Peter Lieu, James Yamaguchi, Randy Bindrup, W. Eric Boyd
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Patent number: 8339150Abstract: A semiconductor integrated circuit includes a bump pad through which data is outputted, a probe test pad having a larger size than the bump pad, a first output drive unit configured to drive the bump pad at a first drivability in response to output data, a second output drive unit configured to drive the probe test pad at a second drivability higher than the first drivability in response to the output data, and a multiplexing unit configured to transfer the output data to the first output drive unit or the second output drive unit in response to a test mode signal.Type: GrantFiled: December 29, 2009Date of Patent: December 25, 2012Assignee: Hynix Semiconductor, Inc.Inventors: Byung-Deuk Jeon, Dong-Geum Kang, Young-Jun Yoon
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Patent number: 8159247Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/NĂ—2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.Type: GrantFiled: October 6, 2009Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Oleg Gluschenkov, Muthukumarasamy Karthikeyan, Yunsheng Song, Tso-Hui Ting, Richard P. Volant, Ping-Chuan Wang
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Patent number: 8154298Abstract: An apparatus for detecting an electrical variable of a rechargeable battery and a method for producing said apparatus, has: a measuring element (1), a printed circuit board (4) and a contact element (5) having a first end (6) and a second end (7), wherein the first end (6) of the contact element (5) is electrically connected to the printed circuit board (4), and the second end (7) of the contact element (5) is electrically connected to the measuring element (1) by a welded joint.Type: GrantFiled: October 27, 2006Date of Patent: April 10, 2012Assignee: Continental Automotive GmbHInventor: Ralf Schimmel