Abstract: A flowmeter measures a fluid velocity and/or direction of a moving multiphase fluid within a hydrocarbon well. The flowmeter includes a microwave front end module comprising transmit and receive antennas and a microwave circuit. The transmit antenna transmits electromagnetic signals towards the fluid at a high frequency ranging from 10 to 100 GHz. The flowmeter includes an analog electronics module converting an analog doppler signal successively into an amplified analog doppler signal and a digital doppler signal. The flowmeter includes a digital processing module comprising a Fast Fourier Transform algorithm for processing the digital doppler signal into a Doppler frequency spectrum. The Doppler spectrum contains information indicative of the fluid velocity and/or direction. A protective shell protects the modules from multiphase fluid.

Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.

Abstract: A powder sensor includes a piezoelectric element, an oscillator circuit, a phase determination circuit, and a powder presence/absence determination circuit. The oscillator circuit applies to the piezoelectric element an output signal having a frequency equal to or near a resonance frequency of the piezoelectric element. The phase determination circuit determines phase of a terminal voltage of the piezoelectric element relative to phase of the output signal from the oscillator circuit. The powder presence/absence determination circuit determines that powder is absent if the phase determination circuit determines, n consecutive times (where “n” is an arbitrary integer satisfying n?2), that the phase of the terminal voltage of the piezoelectric element, relative to the phase of the output signal from the oscillator circuit, satisfies a predetermined condition.

Abstract: A clock-detecting circuit, containing at least a microprocessor, a clock circuit, and a zero-cross detecting circuit. The clock circuit is connected to the microprocessor. The input end of the zero-cross detecting circuit is connected to the utility power AC input. The output end of the zero-cross detecting circuit is connected to the input end of the microprocessor. The zero-cross detecting circuit operates to detect zero crossing points of the utility power AC input. The microprocessor operates to count the number of oscillation periods of the clock circuit in a time interval between two adjacent zero crossing points of the utility power AC input and to detect clock precision of the microprocessor according to the counted number. The circuit according to the invention features simple structure and low production cost, and is reliable and easy to be implemented.

Abstract: A Circuit architecture and a method for rapid and accurate statistical characterization of the variations in the electrical characteristics of CMOS process structures, MOS devices and Circuit parameters is provided. The proposed circuit architecture and method enables a statistical characterization throughput of <1 ms/DC sweep at <2 mV or <1 nA resolution accuracy of variations in voltage or current of the device under test. Salient features of proposed circuit architecture include a programmable ramp voltage generator that stimulates the device under test, a dual input 9-11 bit cyclic ADC that captures input and output DC voltage/current signals to/from the device under test, a 2 Kb latch bank that captures 9-11 bit streams for each measurement point in a DC sweep of programmable granularity and a clocking and control scheme that enables continuous measurement and stream out of digital data blocks from which the analog characteristics of the devices under test are reconstructed post measurement.

Abstract: A circuit for testing phase detectors in a delay locked loop is provided. The circuit uses a second phase detector arranged to receive the signals entering a first phase detector. Particularly, the circuit is routed such that a signal entering the D input of the first phase detector is inputted into the clock input of the second phase detector, and a signal entering the clock input of the first phase detector is inputted into the D input of the second phase detector. The circuit is also coupled to a test controller located on-die or at a high volume manufacturing (HVM) tester.

Abstract: The inverter according to the invention includes a control microcomputer including a protector circuit that stops the inverter when an anomaly is caused, a counter that counts the driving clock signals of the microcomputer from the instance at which the protector circuit starts working, and a conversion circuit that converts the clock signals counted by the counter to a numerical time expression in the time units and outputs the converted numerical time expression. The inverter according to the invention, manufacturable with low manufacturing costs and easy to operate, facilitates informing the installation manager of the period of time from the instance at which the inverter stopped due to an anomaly and such a cause, without impairing the time measurement precision.

Abstract: A broadband receiver exhibiting reduced interference to a frequency counter caused by a local oscillator.

Abstract: A ring oscillation circuit, which can operate the ring oscillation due to a positive feedback stably and continuously, is provided and it is applied to an accurate measurement of delay time and a measurement of timing accuracy in a jitter of a clock signal or the like with a high accuracy. A ring oscillation circuit comprises a delay circuit and a monostable multivibrator. An output of the delay circuit is connected to an input of the monostable multivibrator, an output of the monostable multivibrator is connected to an input of the delay circuit, and the delay circuit and the monostable multivibrator configure a positive feedback loop. An oscillation starting circuit for starting oscillation upon receipt of an input of a trigger pulse for triggering oscillation is provided on the positive feedback loop, or in the inside of the delay circuit or the monostable multivibrator.

Abstract: The present invention provides, a pulse generator, which is configured so as to generate pulses with a predetermined pulse width, comprises: multiple pulsers each of which is configured so as to adjust the pulse width of input pulses, and so as to output pulses with a predetermined pulse width thus adjusted, and which are connected in series; multiple signal acquisition units which are provided corresponding to the multiple pulsers, and each of which allows the pulses output from a corresponding one of the pulsers to be acquired at a position immediately after the output terminal of the corresponding pulser; a selection unit which allows the pulses acquired by one of the multiple signal acquisition units to be selected; a feedback path for inputting the pulses thus selected by the selection unit to the first pulser of the multiple pulsers; and a measurement unit for measuring the pulse width of the pulses thus selected by the selection unit based upon the loop cycle time of the pulse selected by the selection

Abstract: An integrated circuit (1) that comprises an internal clock circuit (12) with a clock output for clocking functional circuits (10) of the integrated circuit (1). The integrated circuit is provided with a counter circuit (16) and a state holding circuit (18) for use during testing. The integrated circuit is switched to a test mode and a start of a test time interval is signalled. Clock pulses from the internal clock circuit 12 are counted from the start of the test time interval and the state holding circuit (18) is locked into a predetermined state if the internal clock circuit has produced more than a predetermined number of clock pulses from the start of the test time interval. Information about whether the state holding circuit (18) has reached the predetermined state in the test time interval is read from the integrated circuit (1) and the information is used by a test evaluation apparatus (2) to accept or reject the integrated circuit (1).

Abstract: In some embodiments, a chip includes clock generation circuitry to create a clock signal, and reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal. The chip includes a counter to change a count value in response to changes in the reference signal; and count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester. Other embodiments are described and claimed.

Abstract: An integrated circuit device comprises internally on-chip an oscillator with a signal output. The device has a reference clock input, a first counter with a count input, a control input and a counter output, a second counter with a count input, a control input and an overflow indication output, and a test control logic circuit. The count input of the first counter is connected to the signal output of the oscillator. The count input of the second counter is connected to the reference clock input. The overflow indication output of the second counter is connected to an input of the test control logic circuit. The test control circuit has an output connected to the control input of the first counter to apply a stop counting control signal to the first counter after it has received an overflow indication signal from the second counter. The first counter after it has received a stop counting control signal provides a count at the counter output which is indicative of the output frequency of the oscillator.

Abstract: A time of an event can be determined by acquiring an amplitude, at the time of the event, of at least two periodic timing signals that are out of phase with each other. The time of the event within a cycle of at least one of the timing signals can be determined as a function of the amplitudes of the timing signals. The phase angle and complex coordinates of at least one of the timing signals can be determined as a function of the amplitudes. The time of the event within a cycle of a timing signal can be determined as a function of the phase angle or complex coordinates of the timing signal at the time of the event.

Abstract: A method and apparatus for acquiring a signal employing a coherent timebase are provided. The method comprises the steps of defining a pattern length count of a repetitive pattern in a signal to be acquired, defining a number of samples per unit interval, and providing data strobes synchronous to a coherent timebase. An arbitrary one of the data strobes is designated as a timing for a potential trigger. A number of subsequent data strobes is counted in accordance with the pattern length count times the samples per unit interval and a portion of the signal corresponding to the pattern length count times the samples per unit interval is acquired beginning at a point in the signal defined by the designated arbitrary data strobe.

Abstract: A circuit for detecting a difference in capacitance between a first capacitor and a second capacitor provided in a sensor includes an oscillator configured to generate an oscillating signal, a phase comparator coupled to the oscillator to output a signal responsive to a phase difference between the oscillating signal delayed by the first capacitor and the oscillating signal delayed by the second capacitor, an integration circuit coupled to the phase comparator to output an integrated signal made by integrating the signal responsive to the phase difference over a time period equal to a predetermined number of cycles of the oscillating signal, and a sample-and-hold circuit coupled to the integration circuit to output a signal made by sampling and holding the integrated signal at substantially an end of the time period.

Abstract: A frequency change measuring device includes frequency divider for frequency dividing a measuring signal to produce frequency-divided signals, first counter for counting the frequency-divided signals to calculate frequency-division numbers, frequency division numbers transmitter for transmitting the frequency division numbers in synchronism with the frequency-divided signals, frequency division numbers receiver for receiving the frequency division numbers transmitted from the frequency division numbers transmitter, second counter for counting outputs of a reference clock generator synchronized with a timekeeping device that keeps the standard time, latch unit for latching a count of frequency outputs of the reference clock generator synchronous for generating reference clocks on the basis of signals synchronous with the frequency division numbers, and operations unit for determining a frequency change on the basis of the count and the frequency division numbers.

Abstract: A pre-conditioner for enabling high-speed time interval measurements in an ATE system having a relatively low-bandwidth pathway between a UUT and a timer/counter includes a frequency divider and a D flip-flop located near the UUT. The frequency divider receives a first input signal from the UUT and produces a first output signal having a frequency equal to 1/N times the frequency of the first input signal. The first output signal connects over the low-bandwidth pathway to a first channel of the timer/counter. The first output signal also connects to the D input of the D flip-flop. The pre-conditioner receives a second input signal from the UUT that drives the CLOCK input of the D flip-flop. The Q output of the D flip-flop supplies a second output of the pre-conditioner. The second output connects over the low-bandwidth pathway to a second channel of the timer/counter.

Abstract: According to an embodiment of the present invention, an input signal is provided to an oscillator, which creates a count signal with a greater frequency than the input signal. The input signal triggers the oscillator to oscillate depending on the value of the input signal. The oscillator output is provided to a counter, which counts the number of oscillations undergone by the oscillator during a single period of the input signal or a number of periods of the input signal, whichever is desired. Since the oscillator frequency is greater than the frequency of the input signal, the oscillator effectively acts like a clock to time the input signal; the counter effectively acts to record the ‘time’ measured by the oscillator (clock). More formally, the counter generates a count value based upon the width of the input signal pulses. The counter output is provided to a decoder, which interprets the count generated by the counter.

Abstract: An engagement detection circuit for a clock recovery circuit consisting of a phase detector (3), a counter element (6) and a flip-flop (8). By employing a low-pass element (12) and a trigger element (13) connected downstream, a preliminary and a final engagement of a phase control circuit can be detected with the engagement detection circuit. This provides a clock recovery circuit for controlling a phase control loop with a phase detector (20), a loop filter (21), a voltage-controlled oscillator (22) and a controllable frequency divider (23).

Abstract: A phase detector for measuring phase differences between K input signals is provided. The phase detector includes a counter, K first registers and a first subtractor. Each first register receives the counter signal of the counter and a respective input signal for updating a counter value in response to timing information on the input signal. The first subtractor receives the counter values to generate phase difference representing values. A frequency detector is also provided. The first subtractor is substituted by a second subtractor and K second registers are included. Each second register is connected to a respective first register. Each second register receives the counter value of its first register and the same input signal as that of its first register for backing-up the counter value as a back-up counter value in response to the timing information on the input signal.